1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
46 class LiveIntervals : public MachineFunctionPass {
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
67 static char ID; // Pass identification, replacement for typeid
68 LiveIntervals() : MachineFunctionPass(ID) {
69 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
72 // Calculate the spill weight to assign to a single instruction.
73 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
75 typedef Reg2IntervalMap::iterator iterator;
76 typedef Reg2IntervalMap::const_iterator const_iterator;
77 const_iterator begin() const { return r2iMap_.begin(); }
78 const_iterator end() const { return r2iMap_.end(); }
79 iterator begin() { return r2iMap_.begin(); }
80 iterator end() { return r2iMap_.end(); }
81 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
83 LiveInterval &getInterval(unsigned reg) {
84 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
85 assert(I != r2iMap_.end() && "Interval does not exist for register");
89 const LiveInterval &getInterval(unsigned reg) const {
90 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
91 assert(I != r2iMap_.end() && "Interval does not exist for register");
95 bool hasInterval(unsigned reg) const {
96 return r2iMap_.count(reg);
99 /// isAllocatable - is the physical register reg allocatable in the current
101 bool isAllocatable(unsigned reg) const {
102 return allocatableRegs_.test(reg);
105 /// getScaledIntervalSize - get the size of an interval in "units,"
106 /// where every function is composed of one thousand units. This
107 /// measure scales properly with empty index slots in the function.
108 double getScaledIntervalSize(LiveInterval& I) {
109 return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
112 /// getFuncInstructionCount - Return the number of instructions in the
113 /// current function.
114 unsigned getFuncInstructionCount() {
115 return indexes_->getFunctionSize();
118 /// getApproximateInstructionCount - computes an estimate of the number
119 /// of instructions in a given LiveInterval.
120 unsigned getApproximateInstructionCount(LiveInterval& I) {
121 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
122 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
126 LiveInterval &getOrCreateInterval(unsigned reg) {
127 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
128 if (I == r2iMap_.end())
129 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
133 /// dupInterval - Duplicate a live interval. The caller is responsible for
134 /// managing the allocated memory.
135 LiveInterval *dupInterval(LiveInterval *li);
137 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
138 /// adds a live range from that instruction to the end of its MBB.
139 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
140 MachineInstr* startInst);
142 /// shrinkToUses - After removing some uses of a register, shrink its live
143 /// range to just the remaining uses. This method does not compute reaching
144 /// defs for new uses, and it doesn't remove dead defs.
145 /// Dead PHIDef values are marked as unused.
146 /// New dead machine instructions are added to the dead vector.
147 /// Return true if the interval may have been separated into multiple
148 /// connected components.
149 bool shrinkToUses(LiveInterval *li,
150 SmallVectorImpl<MachineInstr*> *dead = 0);
154 void removeInterval(unsigned Reg) {
155 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
160 SlotIndexes *getSlotIndexes() const {
164 /// isNotInMIMap - returns true if the specified machine instr has been
165 /// removed or was never entered in the map.
166 bool isNotInMIMap(const MachineInstr* Instr) const {
167 return !indexes_->hasIndex(Instr);
170 /// Returns the base index of the given instruction.
171 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
172 return indexes_->getInstructionIndex(instr);
175 /// Returns the instruction associated with the given index.
176 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
177 return indexes_->getInstructionFromIndex(index);
180 /// Return the first index in the given basic block.
181 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
182 return indexes_->getMBBStartIdx(mbb);
185 /// Return the last index in the given basic block.
186 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
187 return indexes_->getMBBEndIdx(mbb);
190 bool isLiveInToMBB(const LiveInterval &li,
191 const MachineBasicBlock *mbb) const {
192 return li.liveAt(getMBBStartIdx(mbb));
195 LiveRange* findEnteringRange(LiveInterval &li,
196 const MachineBasicBlock *mbb) {
197 return li.getLiveRangeContaining(getMBBStartIdx(mbb));
200 bool isLiveOutOfMBB(const LiveInterval &li,
201 const MachineBasicBlock *mbb) const {
202 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
205 LiveRange* findExitingRange(LiveInterval &li,
206 const MachineBasicBlock *mbb) {
207 return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
210 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
211 return indexes_->getMBBFromIndex(index);
214 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
215 return indexes_->insertMachineInstrInMaps(MI);
218 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
219 indexes_->removeMachineInstrFromMaps(MI);
222 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
223 indexes_->replaceMachineInstrInMaps(MI, NewMI);
226 void InsertMBBInMaps(MachineBasicBlock *MBB) {
227 indexes_->insertMBBInMaps(MBB);
230 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
231 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
232 return indexes_->findLiveInMBBs(Start, End, MBBs);
236 indexes_->renumberIndexes();
239 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
241 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
242 virtual void releaseMemory();
244 /// runOnMachineFunction - pass entry point
245 virtual bool runOnMachineFunction(MachineFunction&);
247 /// print - Implement the dump method.
248 virtual void print(raw_ostream &O, const Module* = 0) const;
250 /// isReMaterializable - Returns true if every definition of MI of every
251 /// val# of the specified interval is re-materializable. Also returns true
252 /// by reference if all of the defs are load instructions.
253 bool isReMaterializable(const LiveInterval &li,
254 const SmallVectorImpl<LiveInterval*> *SpillIs,
257 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
258 /// within a single basic block.
259 bool intervalIsInOneMBB(const LiveInterval &li) const;
261 /// addKillFlags - Add kill flags to any instruction that kills a virtual
265 /// moveInstr - Move MachineInstr mi to insertPt, updating the live
266 /// intervals of mi's operands to reflect the new position. The insertion
267 /// point can be above or below mi, but must be in the same basic block.
268 void moveInstr(MachineBasicBlock::iterator insertPt, MachineInstr* mi);
271 /// computeIntervals - Compute live intervals.
272 void computeIntervals();
274 /// handleRegisterDef - update intervals for a register def
275 /// (calls handlePhysicalRegisterDef and
276 /// handleVirtualRegisterDef)
277 void handleRegisterDef(MachineBasicBlock *MBB,
278 MachineBasicBlock::iterator MI,
280 MachineOperand& MO, unsigned MOIdx);
282 /// isPartialRedef - Return true if the specified def at the specific index
283 /// is partially re-defining the specified live interval. A common case of
284 /// this is a definition of the sub-register.
285 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
286 LiveInterval &interval);
288 /// handleVirtualRegisterDef - update intervals for a virtual
290 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
291 MachineBasicBlock::iterator MI,
292 SlotIndex MIIdx, MachineOperand& MO,
294 LiveInterval& interval);
296 /// handlePhysicalRegisterDef - update intervals for a physical register
298 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
299 MachineBasicBlock::iterator mi,
300 SlotIndex MIIdx, MachineOperand& MO,
301 LiveInterval &interval);
303 /// handleLiveInRegister - Create interval for a livein register.
304 void handleLiveInRegister(MachineBasicBlock* mbb,
306 LiveInterval &interval, bool isAlias = false);
308 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
309 /// only allow one) virtual register operand, then its uses are implicitly
310 /// using the register. Returns the virtual register.
311 unsigned getReMatImplicitUse(const LiveInterval &li,
312 MachineInstr *MI) const;
314 /// isValNoAvailableAt - Return true if the val# of the specified interval
315 /// which reaches the given instruction also reaches the specified use
317 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
318 SlotIndex UseIdx) const;
320 /// isReMaterializable - Returns true if the definition MI of the specified
321 /// val# of the specified interval is re-materializable. Also returns true
322 /// by reference if the def is a load.
323 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
325 const SmallVectorImpl<LiveInterval*> *SpillIs,
328 static LiveInterval* createInterval(unsigned Reg);
330 void printInstrs(raw_ostream &O) const;
331 void dumpInstrs() const;
333 } // End llvm namespace