1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
46 class LiveIntervals : public MachineFunctionPass {
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
66 /// CloneMIs - A list of clones as result of re-materialization.
67 std::vector<MachineInstr*> CloneMIs;
70 static char ID; // Pass identification, replacement for typeid
71 LiveIntervals() : MachineFunctionPass(ID) {
72 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
75 // Calculate the spill weight to assign to a single instruction.
76 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
78 typedef Reg2IntervalMap::iterator iterator;
79 typedef Reg2IntervalMap::const_iterator const_iterator;
80 const_iterator begin() const { return r2iMap_.begin(); }
81 const_iterator end() const { return r2iMap_.end(); }
82 iterator begin() { return r2iMap_.begin(); }
83 iterator end() { return r2iMap_.end(); }
84 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
86 LiveInterval &getInterval(unsigned reg) {
87 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
88 assert(I != r2iMap_.end() && "Interval does not exist for register");
92 const LiveInterval &getInterval(unsigned reg) const {
93 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
94 assert(I != r2iMap_.end() && "Interval does not exist for register");
98 bool hasInterval(unsigned reg) const {
99 return r2iMap_.count(reg);
102 /// isAllocatable - is the physical register reg allocatable in the current
104 bool isAllocatable(unsigned reg) const {
105 return allocatableRegs_.test(reg);
108 /// getScaledIntervalSize - get the size of an interval in "units,"
109 /// where every function is composed of one thousand units. This
110 /// measure scales properly with empty index slots in the function.
111 double getScaledIntervalSize(LiveInterval& I) {
112 return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
115 /// getFuncInstructionCount - Return the number of instructions in the
116 /// current function.
117 unsigned getFuncInstructionCount() {
118 return indexes_->getFunctionSize();
121 /// getApproximateInstructionCount - computes an estimate of the number
122 /// of instructions in a given LiveInterval.
123 unsigned getApproximateInstructionCount(LiveInterval& I) {
124 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
125 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
128 /// conflictsWithPhysReg - Returns true if the specified register is used or
129 /// defined during the duration of the specified interval. Copies to and
130 /// from li.reg are allowed. This method is only able to analyze simple
131 /// ranges that stay within a single basic block. Anything else is
132 /// considered a conflict.
133 bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
136 /// conflictsWithAliasRef - Similar to conflictsWithPhysRegRef except
137 /// it checks for alias uses and defs.
138 bool conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
139 SmallPtrSet<MachineInstr*,32> &JoinedCopies);
142 LiveInterval &getOrCreateInterval(unsigned reg) {
143 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
144 if (I == r2iMap_.end())
145 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
149 /// dupInterval - Duplicate a live interval. The caller is responsible for
150 /// managing the allocated memory.
151 LiveInterval *dupInterval(LiveInterval *li);
153 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
154 /// adds a live range from that instruction to the end of its MBB.
155 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
156 MachineInstr* startInst);
158 /// shrinkToUses - After removing some uses of a register, shrink its live
159 /// range to just the remaining uses. This method does not compute reaching
160 /// defs for new uses, and it doesn't remove dead defs.
161 /// Dead PHIDef values are marked as unused.
162 /// New dead machine instructions are added to the dead vector.
163 void shrinkToUses(LiveInterval *li,
164 SmallVectorImpl<MachineInstr*> *dead = 0);
168 void removeInterval(unsigned Reg) {
169 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
174 SlotIndexes *getSlotIndexes() const {
178 SlotIndex getZeroIndex() const {
179 return indexes_->getZeroIndex();
182 SlotIndex getInvalidIndex() const {
183 return indexes_->getInvalidIndex();
186 /// isNotInMIMap - returns true if the specified machine instr has been
187 /// removed or was never entered in the map.
188 bool isNotInMIMap(const MachineInstr* Instr) const {
189 return !indexes_->hasIndex(Instr);
192 /// Returns the base index of the given instruction.
193 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
194 return indexes_->getInstructionIndex(instr);
197 /// Returns the instruction associated with the given index.
198 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
199 return indexes_->getInstructionFromIndex(index);
202 /// Return the first index in the given basic block.
203 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
204 return indexes_->getMBBStartIdx(mbb);
207 /// Return the last index in the given basic block.
208 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
209 return indexes_->getMBBEndIdx(mbb);
212 bool isLiveInToMBB(const LiveInterval &li,
213 const MachineBasicBlock *mbb) const {
214 return li.liveAt(getMBBStartIdx(mbb));
217 LiveRange* findEnteringRange(LiveInterval &li,
218 const MachineBasicBlock *mbb) {
219 return li.getLiveRangeContaining(getMBBStartIdx(mbb));
222 bool isLiveOutOfMBB(const LiveInterval &li,
223 const MachineBasicBlock *mbb) const {
224 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
227 LiveRange* findExitingRange(LiveInterval &li,
228 const MachineBasicBlock *mbb) {
229 return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
232 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
233 return indexes_->getMBBFromIndex(index);
236 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
237 return indexes_->insertMachineInstrInMaps(MI);
240 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
241 indexes_->removeMachineInstrFromMaps(MI);
244 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
245 indexes_->replaceMachineInstrInMaps(MI, NewMI);
248 void InsertMBBInMaps(MachineBasicBlock *MBB) {
249 indexes_->insertMBBInMaps(MBB);
252 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
253 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
254 return indexes_->findLiveInMBBs(Start, End, MBBs);
258 indexes_->renumberIndexes();
261 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
263 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
264 virtual void releaseMemory();
266 /// runOnMachineFunction - pass entry point
267 virtual bool runOnMachineFunction(MachineFunction&);
269 /// print - Implement the dump method.
270 virtual void print(raw_ostream &O, const Module* = 0) const;
272 /// addIntervalsForSpills - Create new intervals for spilled defs / uses of
273 /// the given interval. FIXME: It also returns the weight of the spill slot
274 /// (if any is created) by reference. This is temporary.
275 std::vector<LiveInterval*>
276 addIntervalsForSpills(const LiveInterval& i,
277 const SmallVectorImpl<LiveInterval*> &SpillIs,
278 const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
280 /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
281 /// around all defs and uses of the specified interval. Return true if it
282 /// was able to cut its interval.
283 bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
284 unsigned PhysReg, VirtRegMap &vrm);
286 /// isReMaterializable - Returns true if every definition of MI of every
287 /// val# of the specified interval is re-materializable. Also returns true
288 /// by reference if all of the defs are load instructions.
289 bool isReMaterializable(const LiveInterval &li,
290 const SmallVectorImpl<LiveInterval*> &SpillIs,
293 /// isReMaterializable - Returns true if the definition MI of the specified
294 /// val# of the specified interval is re-materializable.
295 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
298 /// getRepresentativeReg - Find the largest super register of the specified
299 /// physical register.
300 unsigned getRepresentativeReg(unsigned Reg) const;
302 /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
303 /// specified interval that conflicts with the specified physical register.
304 unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
305 unsigned PhysReg) const;
307 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
308 /// within a single basic block.
309 bool intervalIsInOneMBB(const LiveInterval &li) const;
311 /// getLastSplitPoint - Return the last possible insertion point in mbb for
312 /// spilling and splitting code. This is the first terminator, or the call
313 /// instruction if li is live into a landing pad successor.
314 MachineBasicBlock::iterator getLastSplitPoint(const LiveInterval &li,
315 MachineBasicBlock *mbb) const;
317 /// addKillFlags - Add kill flags to any instruction that kills a virtual
322 /// computeIntervals - Compute live intervals.
323 void computeIntervals();
325 /// handleRegisterDef - update intervals for a register def
326 /// (calls handlePhysicalRegisterDef and
327 /// handleVirtualRegisterDef)
328 void handleRegisterDef(MachineBasicBlock *MBB,
329 MachineBasicBlock::iterator MI,
331 MachineOperand& MO, unsigned MOIdx);
333 /// isPartialRedef - Return true if the specified def at the specific index
334 /// is partially re-defining the specified live interval. A common case of
335 /// this is a definition of the sub-register.
336 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
337 LiveInterval &interval);
339 /// handleVirtualRegisterDef - update intervals for a virtual
341 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
342 MachineBasicBlock::iterator MI,
343 SlotIndex MIIdx, MachineOperand& MO,
345 LiveInterval& interval);
347 /// handlePhysicalRegisterDef - update intervals for a physical register
349 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
350 MachineBasicBlock::iterator mi,
351 SlotIndex MIIdx, MachineOperand& MO,
352 LiveInterval &interval,
353 MachineInstr *CopyMI);
355 /// handleLiveInRegister - Create interval for a livein register.
356 void handleLiveInRegister(MachineBasicBlock* mbb,
358 LiveInterval &interval, bool isAlias = false);
360 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
361 /// only allow one) virtual register operand, then its uses are implicitly
362 /// using the register. Returns the virtual register.
363 unsigned getReMatImplicitUse(const LiveInterval &li,
364 MachineInstr *MI) const;
366 /// isValNoAvailableAt - Return true if the val# of the specified interval
367 /// which reaches the given instruction also reaches the specified use
369 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
370 SlotIndex UseIdx) const;
372 /// isReMaterializable - Returns true if the definition MI of the specified
373 /// val# of the specified interval is re-materializable. Also returns true
374 /// by reference if the def is a load.
375 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
377 const SmallVectorImpl<LiveInterval*> &SpillIs,
380 /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
381 /// slot / to reg or any rematerialized load into ith operand of specified
382 /// MI. If it is successul, MI is updated with the newly created MI and
384 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
385 MachineInstr *DefMI, SlotIndex InstrIdx,
386 SmallVector<unsigned, 2> &Ops,
387 bool isSS, int FrameIndex, unsigned Reg);
389 /// canFoldMemoryOperand - Return true if the specified load / store
390 /// folding is possible.
391 bool canFoldMemoryOperand(MachineInstr *MI,
392 SmallVector<unsigned, 2> &Ops,
393 bool ReMatLoadSS) const;
395 /// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
396 /// VNInfo that's after the specified index but is within the basic block.
397 bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
398 MachineBasicBlock *MBB,
399 SlotIndex Idx) const;
401 /// hasAllocatableSuperReg - Return true if the specified physical register
402 /// has any super register that's allocatable.
403 bool hasAllocatableSuperReg(unsigned Reg) const;
405 /// SRInfo - Spill / restore info.
410 SRInfo(SlotIndex i, unsigned vr, bool f)
411 : index(i), vreg(vr), canFold(f) {}
414 bool alsoFoldARestore(int Id, SlotIndex index, unsigned vr,
415 BitVector &RestoreMBBs,
416 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
417 void eraseRestoreInfo(int Id, SlotIndex index, unsigned vr,
418 BitVector &RestoreMBBs,
419 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
421 /// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
422 /// spilled and create empty intervals for their uses.
423 void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
424 const TargetRegisterClass* rc,
425 std::vector<LiveInterval*> &NewLIs);
427 /// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
428 /// interval on to-be re-materialized operands of MI) with new register.
429 void rewriteImplicitOps(const LiveInterval &li,
430 MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
432 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
433 /// functions for addIntervalsForSpills to rewrite uses / defs for the given
435 bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
436 bool TrySplit, SlotIndex index, SlotIndex end,
437 MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
438 unsigned Slot, int LdSlot,
439 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
440 VirtRegMap &vrm, const TargetRegisterClass* rc,
441 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
442 unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
443 DenseMap<unsigned,unsigned> &MBBVRegsMap,
444 std::vector<LiveInterval*> &NewLIs);
445 void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
446 LiveInterval::Ranges::const_iterator &I,
447 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
448 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
449 VirtRegMap &vrm, const TargetRegisterClass* rc,
450 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
451 BitVector &SpillMBBs,
452 DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
453 BitVector &RestoreMBBs,
454 DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
455 DenseMap<unsigned,unsigned> &MBBVRegsMap,
456 std::vector<LiveInterval*> &NewLIs);
458 static LiveInterval* createInterval(unsigned Reg);
460 void printInstrs(raw_ostream &O) const;
461 void dumpInstrs() const;
463 } // End llvm namespace