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23 The LLVM Target-Independent Code Generator
27 <li><a href="#introduction">Introduction</a>
29 <li><a href="#required">Required components in the code generator</a></li>
30 <li><a href="#high-level-design">The high-level design of the code
32 <li><a href="#tablegen">Using TableGen for target description</a></li>
35 <li><a href="#targetdesc">Target description classes</a>
37 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
38 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
39 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
40 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
41 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
42 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
43 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
44 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
47 <li><a href="#codegendesc">The "Machine" Code Generator classes</a>
49 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
50 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
52 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
55 <li><a href="#mc">The "MC" Layer</a>
57 <li><a href="#mcstreamer">The <tt>MCStreamer</tt> API</a></li>
58 <li><a href="#mccontext">The <tt>MCContext</tt> class</a>
59 <li><a href="#mcsymbol">The <tt>MCSymbol</tt> class</a></li>
60 <li><a href="#mcsection">The <tt>MCSection</tt> class</a></li>
61 <li><a href="#mcinst">The <tt>MCInst</tt> class</a></li>
64 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
66 <li><a href="#instselect">Instruction Selection</a>
68 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
69 <li><a href="#selectiondag_process">SelectionDAG Code Generation
71 <li><a href="#selectiondag_build">Initial SelectionDAG
73 <li><a href="#selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a></li>
74 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
75 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
76 Phase: the DAG Combiner</a></li>
77 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
78 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
80 <li><a href="#selectiondag_future">Future directions for the
83 <li><a href="#liveintervals">Live Intervals</a>
85 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
86 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
88 <li><a href="#regalloc">Register Allocation</a>
90 <li><a href="#regAlloc_represent">How registers are represented in
92 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
94 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
95 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
96 <li><a href="#regAlloc_fold">Instruction folding</a></li>
97 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
99 <li><a href="#codeemit">Code Emission</a></li>
102 <li><a href="#nativeassembler">Implementing a Native Assembler</a></li>
104 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
106 <li><a href="#targetfeatures">Target Feature Matrix</a></li>
107 <li><a href="#tailcallopt">Tail call optimization</a></li>
108 <li><a href="#sibcallopt">Sibling call optimization</a></li>
109 <li><a href="#x86">The X86 backend</a></li>
110 <li><a href="#ppc">The PowerPC backend</a>
112 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
113 <li><a href="#ppc_frame">Frame Layout</a></li>
114 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
115 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
117 <li><a href="#ptx">The PTX backend</a></li>
122 <div class="doc_author">
123 <p>Written by the LLVM Team.</p>
126 <div class="doc_warning">
127 <p>Warning: This is a work in progress.</p>
130 <!-- *********************************************************************** -->
132 <a name="introduction">Introduction</a>
134 <!-- *********************************************************************** -->
138 <p>The LLVM target-independent code generator is a framework that provides a
139 suite of reusable components for translating the LLVM internal representation
140 to the machine code for a specified target—either in assembly form
141 (suitable for a static compiler) or in binary machine code format (usable for
142 a JIT compiler). The LLVM target-independent code generator consists of six
146 <li><a href="#targetdesc">Abstract target description</a> interfaces which
147 capture important properties about various aspects of the machine,
148 independently of how they will be used. These interfaces are defined in
149 <tt>include/llvm/Target/</tt>.</li>
151 <li>Classes used to represent the <a href="#codegendesc">code being
152 generated</a> for a target. These classes are intended to be abstract
153 enough to represent the machine code for <i>any</i> target machine. These
154 classes are defined in <tt>include/llvm/CodeGen/</tt>. At this level,
155 concepts like "constant pool entries" and "jump tables" are explicitly
158 <li>Classes and algorithms used to represent code as the object file level,
159 the <a href="#mc">MC Layer</a>. These classes represent assembly level
160 constructs like labels, sections, and instructions. At this level,
161 concepts like "constant pool entries" and "jump tables" don't exist.</li>
163 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
164 various phases of native code generation (register allocation, scheduling,
165 stack frame representation, etc). This code lives
166 in <tt>lib/CodeGen/</tt>.</li>
168 <li><a href="#targetimpls">Implementations of the abstract target description
169 interfaces</a> for particular targets. These machine descriptions make
170 use of the components provided by LLVM, and can optionally provide custom
171 target-specific passes, to build complete code generators for a specific
172 target. Target descriptions live in <tt>lib/Target/</tt>.</li>
174 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
175 completely target independent (it uses the <tt>TargetJITInfo</tt>
176 structure to interface for target-specific issues. The code for the
177 target-independent JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
180 <p>Depending on which part of the code generator you are interested in working
181 on, different pieces of this will be useful to you. In any case, you should
182 be familiar with the <a href="#targetdesc">target description</a>
183 and <a href="#codegendesc">machine code representation</a> classes. If you
184 want to add a backend for a new target, you will need
185 to <a href="#targetimpls">implement the target description</a> classes for
186 your new target and understand the <a href="LangRef.html">LLVM code
187 representation</a>. If you are interested in implementing a
188 new <a href="#codegenalgs">code generation algorithm</a>, it should only
189 depend on the target-description and machine code representation classes,
190 ensuring that it is portable.</p>
192 <!-- ======================================================================= -->
194 <a name="required">Required components in the code generator</a>
199 <p>The two pieces of the LLVM code generator are the high-level interface to the
200 code generator and the set of reusable components that can be used to build
201 target-specific backends. The two most important interfaces
202 (<a href="#targetmachine"><tt>TargetMachine</tt></a>
203 and <a href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
204 required to be defined for a backend to fit into the LLVM system, but the
205 others must be defined if the reusable code generator components are going to
208 <p>This design has two important implications. The first is that LLVM can
209 support completely non-traditional code generation targets. For example, the
210 C backend does not require register allocation, instruction selection, or any
211 of the other standard components provided by the system. As such, it only
212 implements these two interfaces, and does its own thing. Another example of
213 a code generator like this is a (purely hypothetical) backend that converts
214 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
216 <p>This design also implies that it is possible to design and implement
217 radically different code generators in the LLVM system that do not make use
218 of any of the built-in components. Doing so is not recommended at all, but
219 could be required for radically different targets that do not fit into the
220 LLVM machine description model: FPGAs for example.</p>
224 <!-- ======================================================================= -->
226 <a name="high-level-design">The high-level design of the code generator</a>
231 <p>The LLVM target-independent code generator is designed to support efficient
232 and quality code generation for standard register-based microprocessors.
233 Code generation in this model is divided into the following stages:</p>
236 <li><b><a href="#instselect">Instruction Selection</a></b> — This phase
237 determines an efficient way to express the input LLVM code in the target
238 instruction set. This stage produces the initial code for the program in
239 the target instruction set, then makes use of virtual registers in SSA
240 form and physical registers that represent any required register
241 assignments due to target constraints or calling conventions. This step
242 turns the LLVM code into a DAG of target instructions.</li>
244 <li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> —
245 This phase takes the DAG of target instructions produced by the
246 instruction selection phase, determines an ordering of the instructions,
247 then emits the instructions
248 as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
249 Note that we describe this in the <a href="#instselect">instruction
250 selection section</a> because it operates on
251 a <a href="#selectiondag_intro">SelectionDAG</a>.</li>
253 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> —
254 This optional stage consists of a series of machine-code optimizations
255 that operate on the SSA-form produced by the instruction selector.
256 Optimizations like modulo-scheduling or peephole optimization work
259 <li><b><a href="#regalloc">Register Allocation</a></b> — The target code
260 is transformed from an infinite virtual register file in SSA form to the
261 concrete register file used by the target. This phase introduces spill
262 code and eliminates all virtual register references from the program.</li>
264 <li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> — Once
265 the machine code has been generated for the function and the amount of
266 stack space required is known (used for LLVM alloca's and spill slots),
267 the prolog and epilog code for the function can be inserted and "abstract
268 stack location references" can be eliminated. This stage is responsible
269 for implementing optimizations like frame-pointer elimination and stack
272 <li><b><a href="#latemco">Late Machine Code Optimizations</a></b> —
273 Optimizations that operate on "final" machine code can go here, such as
274 spill code scheduling and peephole optimizations.</li>
276 <li><b><a href="#codeemit">Code Emission</a></b> — The final stage
277 actually puts out the code for the current function, either in the target
278 assembler format or in machine code.</li>
281 <p>The code generator is based on the assumption that the instruction selector
282 will use an optimal pattern matching selector to create high-quality
283 sequences of native instructions. Alternative code generator designs based
284 on pattern expansion and aggressive iterative peephole optimization are much
285 slower. This design permits efficient compilation (important for JIT
286 environments) and aggressive optimization (used when generating code offline)
287 by allowing components of varying levels of sophistication to be used for any
288 step of compilation.</p>
290 <p>In addition to these stages, target implementations can insert arbitrary
291 target-specific passes into the flow. For example, the X86 target uses a
292 special pass to handle the 80x87 floating point stack architecture. Other
293 targets with unusual requirements can be supported with custom passes as
298 <!-- ======================================================================= -->
300 <a name="tablegen">Using TableGen for target description</a>
305 <p>The target description classes require a detailed description of the target
306 architecture. These target descriptions often have a large amount of common
307 information (e.g., an <tt>add</tt> instruction is almost identical to a
308 <tt>sub</tt> instruction). In order to allow the maximum amount of
309 commonality to be factored out, the LLVM code generator uses
310 the <a href="TableGenFundamentals.html">TableGen</a> tool to describe big
311 chunks of the target machine, which allows the use of domain-specific and
312 target-specific abstractions to reduce the amount of repetition.</p>
314 <p>As LLVM continues to be developed and refined, we plan to move more and more
315 of the target description to the <tt>.td</tt> form. Doing so gives us a
316 number of advantages. The most important is that it makes it easier to port
317 LLVM because it reduces the amount of C++ code that has to be written, and
318 the surface area of the code generator that needs to be understood before
319 someone can get something working. Second, it makes it easier to change
320 things. In particular, if tables and other things are all emitted
321 by <tt>tblgen</tt>, we only need a change in one place (<tt>tblgen</tt>) to
322 update all of the targets to a new interface.</p>
328 <!-- *********************************************************************** -->
330 <a name="targetdesc">Target description classes</a>
332 <!-- *********************************************************************** -->
336 <p>The LLVM target description classes (located in the
337 <tt>include/llvm/Target</tt> directory) provide an abstract description of
338 the target machine independent of any particular client. These classes are
339 designed to capture the <i>abstract</i> properties of the target (such as the
340 instructions and registers it has), and do not incorporate any particular
341 pieces of code generation algorithms.</p>
343 <p>All of the target description classes (except the
344 <tt><a href="#targetdata">TargetData</a></tt> class) are designed to be
345 subclassed by the concrete target implementation, and have virtual methods
346 implemented. To get to these implementations, the
347 <tt><a href="#targetmachine">TargetMachine</a></tt> class provides accessors
348 that should be implemented by the target.</p>
350 <!-- ======================================================================= -->
352 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
357 <p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
358 access the target-specific implementations of the various target description
359 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
360 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
361 designed to be specialized by a concrete target implementation
362 (e.g., <tt>X86TargetMachine</tt>) which implements the various virtual
363 methods. The only required target description class is
364 the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the code
365 generator components are to be used, the other interfaces should be
366 implemented as well.</p>
370 <!-- ======================================================================= -->
372 <a name="targetdata">The <tt>TargetData</tt> class</a>
377 <p>The <tt>TargetData</tt> class is the only required target description class,
378 and it is the only class that is not extensible (you cannot derived a new
379 class from it). <tt>TargetData</tt> specifies information about how the
380 target lays out memory for structures, the alignment requirements for various
381 data types, the size of pointers in the target, and whether the target is
382 little-endian or big-endian.</p>
386 <!-- ======================================================================= -->
388 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
393 <p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
394 selectors primarily to describe how LLVM code should be lowered to
395 SelectionDAG operations. Among other things, this class indicates:</p>
398 <li>an initial register class to use for various <tt>ValueType</tt>s,</li>
400 <li>which operations are natively supported by the target machine,</li>
402 <li>the return type of <tt>setcc</tt> operations,</li>
404 <li>the type to use for shift amounts, and</li>
406 <li>various high-level characteristics, like whether it is profitable to turn
407 division by a constant into a multiplication sequence</li>
412 <!-- ======================================================================= -->
414 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
419 <p>The <tt>TargetRegisterInfo</tt> class is used to describe the register file
420 of the target and any interactions between the registers.</p>
422 <p>Registers in the code generator are represented in the code generator by
423 unsigned integers. Physical registers (those that actually exist in the
424 target description) are unique small numbers, and virtual registers are
425 generally large. Note that register #0 is reserved as a flag value.</p>
427 <p>Each register in the processor description has an associated
428 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
429 register (used for assembly output and debugging dumps) and a set of aliases
430 (used to indicate whether one register overlaps with another).</p>
432 <p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
433 class exposes a set of processor specific register classes (instances of the
434 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
435 registers that have the same properties (for example, they are all 32-bit
436 integer registers). Each SSA virtual register created by the instruction
437 selector has an associated register class. When the register allocator runs,
438 it replaces virtual registers with a physical register in the set.</p>
440 <p>The target-specific implementations of these classes is auto-generated from
441 a <a href="TableGenFundamentals.html">TableGen</a> description of the
446 <!-- ======================================================================= -->
448 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
453 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
454 instructions supported by the target. It is essentially an array of
455 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
456 instruction the target supports. Descriptors define things like the mnemonic
457 for the opcode, the number of operands, the list of implicit register uses
458 and defs, whether the instruction has certain target-independent properties
459 (accesses memory, is commutable, etc), and holds any target-specific
464 <!-- ======================================================================= -->
466 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
471 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
472 stack frame layout of the target. It holds the direction of stack growth, the
473 known stack alignment on entry to each function, and the offset to the local
474 area. The offset to the local area is the offset from the stack pointer on
475 function entry to the first location where function data (local variables,
476 spill locations) can be stored.</p>
480 <!-- ======================================================================= -->
482 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
487 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
488 specific chip set being targeted. A sub-target informs code generation of
489 which instructions are supported, instruction latencies and instruction
490 execution itinerary; i.e., which processing units are used, in what order,
491 and for how long.</p>
496 <!-- ======================================================================= -->
498 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
503 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
504 Just-In-Time code generator to perform target-specific activities, such as
505 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
506 should provide one of these objects through the <tt>getJITInfo</tt>
513 <!-- *********************************************************************** -->
515 <a name="codegendesc">Machine code description classes</a>
517 <!-- *********************************************************************** -->
521 <p>At the high-level, LLVM code is translated to a machine specific
522 representation formed out of
523 <a href="#machinefunction"><tt>MachineFunction</tt></a>,
524 <a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>,
525 and <a href="#machineinstr"><tt>MachineInstr</tt></a> instances (defined
526 in <tt>include/llvm/CodeGen</tt>). This representation is completely target
527 agnostic, representing instructions in their most abstract form: an opcode
528 and a series of operands. This representation is designed to support both an
529 SSA representation for machine code, as well as a register allocated, non-SSA
532 <!-- ======================================================================= -->
534 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
539 <p>Target machine instructions are represented as instances of the
540 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
541 representing machine instructions. In particular, it only keeps track of an
542 opcode number and a set of operands.</p>
544 <p>The opcode number is a simple unsigned integer that only has meaning to a
545 specific backend. All of the instructions for a target should be defined in
546 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values are
547 auto-generated from this description. The <tt>MachineInstr</tt> class does
548 not have any information about how to interpret the instruction (i.e., what
549 the semantics of the instruction are); for that you must refer to the
550 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
552 <p>The operands of a machine instruction can be of several different types: a
553 register reference, a constant integer, a basic block reference, etc. In
554 addition, a machine operand should be marked as a def or a use of the value
555 (though only registers are allowed to be defs).</p>
557 <p>By convention, the LLVM code generator orders instruction operands so that
558 all register definitions come before the register uses, even on architectures
559 that are normally printed in other orders. For example, the SPARC add
560 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
561 and stores the result into the "%i3" register. In the LLVM code generator,
562 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
563 destination first.</p>
565 <p>Keeping destination (definition) operands at the beginning of the operand
566 list has several advantages. In particular, the debugging printer will print
567 the instruction like this:</p>
569 <div class="doc_code">
575 <p>Also if the first operand is a def, it is easier to <a href="#buildmi">create
576 instructions</a> whose only def is the first operand.</p>
578 <!-- _______________________________________________________________________ -->
580 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
585 <p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
586 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
587 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
588 instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
590 <div class="doc_code">
592 // Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
593 // instruction. The '1' specifies how many operands will be added.
594 MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
596 // Create the same instr, but insert it at the end of a basic block.
597 MachineBasicBlock &MBB = ...
598 BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
600 // Create the same instr, but insert it before a specified iterator point.
601 MachineBasicBlock::iterator MBBI = ...
602 BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
604 // Create a 'cmp Reg, 0' instruction, no destination reg.
605 MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
606 // Create an 'sahf' instruction which takes no operands and stores nothing.
607 MI = BuildMI(X86::SAHF, 0);
609 // Create a self looping branch instruction.
610 BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
614 <p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
615 have to specify the number of operands that the machine instruction will
616 take. This allows for efficient memory allocation. You also need to specify
617 if operands default to be uses of values, not definitions. If you need to
618 add a definition operand (other than the optional destination register), you
619 must explicitly mark it as such:</p>
621 <div class="doc_code">
623 MI.addReg(Reg, RegState::Define);
629 <!-- _______________________________________________________________________ -->
631 <a name="fixedregs">Fixed (preassigned) registers</a>
636 <p>One important issue that the code generator needs to be aware of is the
637 presence of fixed registers. In particular, there are often places in the
638 instruction stream where the register allocator <em>must</em> arrange for a
639 particular value to be in a particular register. This can occur due to
640 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
641 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like
642 calling conventions. In any case, the instruction selector should emit code
643 that copies a virtual register into or out of a physical register when
646 <p>For example, consider this simple LLVM example:</p>
648 <div class="doc_code">
650 define i32 @test(i32 %X, i32 %Y) {
657 <p>The X86 instruction selector produces this machine code for the <tt>div</tt>
658 and <tt>ret</tt> (use "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to
661 <div class="doc_code">
664 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
665 %reg1027 = sar %reg1024, 31
666 %EDX = mov %reg1027 ;; Sign extend X into EDX
667 idiv %reg1025 ;; Divide by Y (in reg1025)
668 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
671 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
676 <p>By the end of code generation, the register allocator has coalesced the
677 registers and deleted the resultant identity moves producing the following
680 <div class="doc_code">
682 ;; X is in EAX, Y is in ECX
690 <p>This approach is extremely general (if it can handle the X86 architecture, it
691 can handle anything!) and allows all of the target specific knowledge about
692 the instruction stream to be isolated in the instruction selector. Note that
693 physical registers should have a short lifetime for good code generation, and
694 all physical registers are assumed dead on entry to and exit from basic
695 blocks (before register allocation). Thus, if you need a value to be live
696 across basic block boundaries, it <em>must</em> live in a virtual
701 <!-- _______________________________________________________________________ -->
703 <a name="ssa">Machine code in SSA form</a>
708 <p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and are
709 maintained in SSA-form until register allocation happens. For the most part,
710 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
711 become machine code PHI nodes, and virtual registers are only allowed to have
712 a single definition.</p>
714 <p>After register allocation, machine code is no longer in SSA-form because
715 there are no virtual registers left in the code.</p>
721 <!-- ======================================================================= -->
723 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
728 <p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
729 (<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
730 corresponds to the LLVM code input to the instruction selector, but there can
731 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
732 machine basic blocks). The <tt>MachineBasicBlock</tt> class has a
733 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
738 <!-- ======================================================================= -->
740 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
745 <p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
746 (<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
747 corresponds one-to-one with the LLVM function input to the instruction
748 selector. In addition to a list of basic blocks,
749 the <tt>MachineFunction</tt> contains a a <tt>MachineConstantPool</tt>,
750 a <tt>MachineFrameInfo</tt>, a <tt>MachineFunctionInfo</tt>, and a
751 <tt>MachineRegisterInfo</tt>. See
752 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
758 <!-- *********************************************************************** -->
760 <a name="mc">The "MC" Layer</a>
762 <!-- *********************************************************************** -->
767 The MC Layer is used to represent and process code at the raw machine code
768 level, devoid of "high level" information like "constant pools", "jump tables",
769 "global variables" or anything like that. At this level, LLVM handles things
770 like label names, machine instructions, and sections in the object file. The
771 code in this layer is used for a number of important purposes: the tail end of
772 the code generator uses it to write a .s or .o file, and it is also used by the
773 llvm-mc tool to implement standalone machine code assemblers and disassemblers.
777 This section describes some of the important classes. There are also a number
778 of important subsystems that interact at this layer, they are described later
782 <!-- ======================================================================= -->
784 <a name="mcstreamer">The <tt>MCStreamer</tt> API</a>
790 MCStreamer is best thought of as an assembler API. It is an abstract API which
791 is <em>implemented</em> in different ways (e.g. to output a .s file, output an
792 ELF .o file, etc) but whose API correspond directly to what you see in a .s
793 file. MCStreamer has one method per directive, such as EmitLabel,
794 EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which
795 directly correspond to assembly level directives. It also has an
796 EmitInstruction method, which is used to output an MCInst to the streamer.
800 This API is most important for two clients: the llvm-mc stand-alone assembler is
801 effectively a parser that parses a line, then invokes a method on MCStreamer. In
802 the code generator, the <a href="#codeemit">Code Emission</a> phase of the code
803 generator lowers higher level LLVM IR and Machine* constructs down to the MC
804 layer, emitting directives through MCStreamer.</p>
807 On the implementation side of MCStreamer, there are two major implementations:
808 one for writing out a .s file (MCAsmStreamer), and one for writing out a .o
809 file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation
810 that prints out a directive for each method (e.g. EmitValue -> .byte), but
811 MCObjectStreamer implements a full assembler.
816 <!-- ======================================================================= -->
818 <a name="mccontext">The <tt>MCContext</tt> class</a>
824 The MCContext class is the owner of a variety of uniqued data structures at the
825 MC layer, including symbols, sections, etc. As such, this is the class that you
826 interact with to create symbols and sections. This class can not be subclassed.
831 <!-- ======================================================================= -->
833 <a name="mcsymbol">The <tt>MCSymbol</tt> class</a>
839 The MCSymbol class represents a symbol (aka label) in the assembly file. There
840 are two interesting kinds of symbols: assembler temporary symbols, and normal
841 symbols. Assembler temporary symbols are used and processed by the assembler
842 but are discarded when the object file is produced. The distinction is usually
843 represented by adding a prefix to the label, for example "L" labels are
844 assembler temporary labels in MachO.
847 <p>MCSymbols are created by MCContext and uniqued there. This means that
848 MCSymbols can be compared for pointer equivalence to find out if they are the
849 same symbol. Note that pointer inequality does not guarantee the labels will
850 end up at different addresses though. It's perfectly legal to output something
851 like this to the .s file:<p>
859 <p>In this case, both the foo and bar symbols will have the same address.</p>
863 <!-- ======================================================================= -->
865 <a name="mcsection">The <tt>MCSection</tt> class</a>
871 The MCSection class represents an object-file specific section. It is subclassed
872 by object file specific implementations (e.g. <tt>MCSectionMachO</tt>,
873 <tt>MCSectionCOFF</tt>, <tt>MCSectionELF</tt>) and these are created and uniqued
874 by MCContext. The MCStreamer has a notion of the current section, which can be
875 changed with the SwitchToSection method (which corresponds to a ".section"
876 directive in a .s file).
881 <!-- ======================================================================= -->
883 <a name="mcinst">The <tt>MCInst</tt> class</a>
889 The MCInst class is a target-independent representation of an instruction. It
890 is a simple class (much more so than <a href="#machineinstr">MachineInstr</a>)
891 that holds a target-specific opcode and a vector of MCOperands. MCOperand, in
892 turn, is a simple discriminated union of three cases: 1) a simple immediate,
893 2) a target register ID, 3) a symbolic expression (e.g. "Lfoo-Lbar+42") as an
897 <p>MCInst is the common currency used to represent machine instructions at the
898 MC layer. It is the type used by the instruction encoder, the instruction
899 printer, and the type generated by the assembly parser and disassembler.
906 <!-- *********************************************************************** -->
908 <a name="codegenalgs">Target-independent code generation algorithms</a>
910 <!-- *********************************************************************** -->
914 <p>This section documents the phases described in the
915 <a href="#high-level-design">high-level design of the code generator</a>.
916 It explains how they work and some of the rationale behind their design.</p>
918 <!-- ======================================================================= -->
920 <a name="instselect">Instruction Selection</a>
925 <p>Instruction Selection is the process of translating LLVM code presented to
926 the code generator into target-specific machine instructions. There are
927 several well-known ways to do this in the literature. LLVM uses a
928 SelectionDAG based instruction selector.</p>
930 <p>Portions of the DAG instruction selector are generated from the target
931 description (<tt>*.td</tt>) files. Our goal is for the entire instruction
932 selector to be generated from these <tt>.td</tt> files, though currently
933 there are still things that require custom C++ code.</p>
935 <!-- _______________________________________________________________________ -->
937 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
942 <p>The SelectionDAG provides an abstraction for code representation in a way
943 that is amenable to instruction selection using automatic techniques
944 (e.g. dynamic-programming based optimal pattern matching selectors). It is
945 also well-suited to other phases of code generation; in particular,
946 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
947 post-selection). Additionally, the SelectionDAG provides a host
948 representation where a large variety of very-low-level (but
949 target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
950 performed; ones which require extensive information about the instructions
951 efficiently supported by the target.</p>
953 <p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
954 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
955 operation code (Opcode) that indicates what operation the node performs and
956 the operands to the operation. The various operation node types are
957 described at the top of the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
960 <p>Although most operations define a single value, each node in the graph may
961 define multiple values. For example, a combined div/rem operation will
962 define both the dividend and the remainder. Many other situations require
963 multiple values as well. Each node also has some number of operands, which
964 are edges to the node defining the used value. Because nodes may define
965 multiple values, edges are represented by instances of the <tt>SDValue</tt>
966 class, which is a <tt><SDNode, unsigned></tt> pair, indicating the node
967 and result value being used, respectively. Each value produced by
968 an <tt>SDNode</tt> has an associated <tt>MVT</tt> (Machine Value Type)
969 indicating what the type of the value is.</p>
971 <p>SelectionDAGs contain two different kinds of values: those that represent
972 data flow and those that represent control flow dependencies. Data values
973 are simple edges with an integer or floating point value type. Control edges
974 are represented as "chain" edges which are of type <tt>MVT::Other</tt>.
975 These edges provide an ordering between nodes that have side effects (such as
976 loads, stores, calls, returns, etc). All nodes that have side effects should
977 take a token chain as input and produce a new one as output. By convention,
978 token chain inputs are always operand #0, and chain results are always the
979 last value produced by an operation.</p>
981 <p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
982 always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root
983 node is the final side-effecting node in the token chain. For example, in a
984 single basic block function it would be the return node.</p>
986 <p>One important concept for SelectionDAGs is the notion of a "legal" vs.
987 "illegal" DAG. A legal DAG for a target is one that only uses supported
988 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
989 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
990 uses a SREM or UREM operation. The
991 <a href="#selectinodag_legalize_types">legalize types</a> and
992 <a href="#selectiondag_legalize">legalize operations</a> phases are
993 responsible for turning an illegal DAG into a legal DAG.</p>
997 <!-- _______________________________________________________________________ -->
999 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
1004 <p>SelectionDAG-based instruction selection consists of the following steps:</p>
1007 <li><a href="#selectiondag_build">Build initial DAG</a> — This stage
1008 performs a simple translation from the input LLVM code to an illegal
1011 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> — This
1012 stage performs simple optimizations on the SelectionDAG to simplify it,
1013 and recognize meta instructions (like rotates
1014 and <tt>div</tt>/<tt>rem</tt> pairs) for targets that support these meta
1015 operations. This makes the resultant code more efficient and
1016 the <a href="#selectiondag_select">select instructions from DAG</a> phase
1017 (below) simpler.</li>
1019 <li><a href="#selectiondag_legalize_types">Legalize SelectionDAG Types</a>
1020 — This stage transforms SelectionDAG nodes to eliminate any types
1021 that are unsupported on the target.</li>
1023 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> — The
1024 SelectionDAG optimizer is run to clean up redundancies exposed by type
1027 <li><a href="#selectiondag_legalize">Legalize SelectionDAG Ops</a> —
1028 This stage transforms SelectionDAG nodes to eliminate any operations
1029 that are unsupported on the target.</li>
1031 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> — The
1032 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
1033 operation legalization.</li>
1035 <li><a href="#selectiondag_select">Select instructions from DAG</a> —
1036 Finally, the target instruction selector matches the DAG operations to
1037 target instructions. This process translates the target-independent input
1038 DAG into another DAG of target instructions.</li>
1040 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
1041 — The last phase assigns a linear order to the instructions in the
1042 target-instruction DAG and emits them into the MachineFunction being
1043 compiled. This step uses traditional prepass scheduling techniques.</li>
1046 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
1047 rest of the code generation passes are run.</p>
1049 <p>One great way to visualize what is going on here is to take advantage of a
1050 few LLC command line options. The following options pop up a window
1051 displaying the SelectionDAG at specific times (if you only get errors printed
1052 to the console while using this, you probably
1053 <a href="ProgrammersManual.html#ViewGraph">need to configure your system</a>
1054 to add support for it).</p>
1057 <li><tt>-view-dag-combine1-dags</tt> displays the DAG after being built,
1058 before the first optimization pass.</li>
1060 <li><tt>-view-legalize-dags</tt> displays the DAG before Legalization.</li>
1062 <li><tt>-view-dag-combine2-dags</tt> displays the DAG before the second
1063 optimization pass.</li>
1065 <li><tt>-view-isel-dags</tt> displays the DAG before the Select phase.</li>
1067 <li><tt>-view-sched-dags</tt> displays the DAG before Scheduling.</li>
1070 <p>The <tt>-view-sunit-dags</tt> displays the Scheduler's dependency graph.
1071 This graph is based on the final SelectionDAG, with nodes that must be
1072 scheduled together bundled into a single scheduling-unit node, and with
1073 immediate operands and other nodes that aren't relevant for scheduling
1078 <!-- _______________________________________________________________________ -->
1080 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
1085 <p>The initial SelectionDAG is naïvely peephole expanded from the LLVM
1086 input by the <tt>SelectionDAGLowering</tt> class in the
1087 <tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of
1088 this pass is to expose as much low-level, target-specific details to the
1089 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
1090 LLVM <tt>add</tt> turns into an <tt>SDNode add</tt> while a
1091 <tt>getelementptr</tt> is expanded into the obvious arithmetic). This pass
1092 requires target-specific hooks to lower calls, returns, varargs, etc. For
1093 these features, the <tt><a href="#targetlowering">TargetLowering</a></tt>
1094 interface is used.</p>
1098 <!-- _______________________________________________________________________ -->
1100 <a name="selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a>
1105 <p>The Legalize phase is in charge of converting a DAG to only use the types
1106 that are natively supported by the target.</p>
1108 <p>There are two main ways of converting values of unsupported scalar types to
1109 values of supported types: converting small types to larger types
1110 ("promoting"), and breaking up large integer types into smaller ones
1111 ("expanding"). For example, a target might require that all f32 values are
1112 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
1113 target might require that all i64 values be expanded into pairs of i32
1114 values. These changes can insert sign and zero extensions as needed to make
1115 sure that the final code has the same behavior as the input.</p>
1117 <p>There are two main ways of converting values of unsupported vector types to
1118 value of supported types: splitting vector types, multiple times if
1119 necessary, until a legal type is found, and extending vector types by adding
1120 elements to the end to round them out to legal types ("widening"). If a
1121 vector gets split all the way down to single-element parts with no supported
1122 vector type being found, the elements are converted to scalars
1123 ("scalarizing").</p>
1125 <p>A target implementation tells the legalizer which types are supported (and
1126 which register class to use for them) by calling the
1127 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
1131 <!-- _______________________________________________________________________ -->
1133 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
1138 <p>The Legalize phase is in charge of converting a DAG to only use the
1139 operations that are natively supported by the target.</p>
1141 <p>Targets often have weird constraints, such as not supporting every operation
1142 on every supported datatype (e.g. X86 does not support byte conditional moves
1143 and PowerPC does not support sign-extending loads from a 16-bit memory
1144 location). Legalize takes care of this by open-coding another sequence of
1145 operations to emulate the operation ("expansion"), by promoting one type to a
1146 larger type that supports the operation ("promotion"), or by using a
1147 target-specific hook to implement the legalization ("custom").</p>
1149 <p>A target implementation tells the legalizer which operations are not
1150 supported (and which of the above three actions to take) by calling the
1151 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
1154 <p>Prior to the existence of the Legalize passes, we required that every target
1155 <a href="#selectiondag_optimize">selector</a> supported and handled every
1156 operator and type even if they are not natively supported. The introduction
1157 of the Legalize phases allows all of the canonicalization patterns to be
1158 shared across targets, and makes it very easy to optimize the canonicalized
1159 code because it is still in the form of a DAG.</p>
1163 <!-- _______________________________________________________________________ -->
1165 <a name="selectiondag_optimize">
1166 SelectionDAG Optimization Phase: the DAG Combiner
1172 <p>The SelectionDAG optimization phase is run multiple times for code
1173 generation, immediately after the DAG is built and once after each
1174 legalization. The first run of the pass allows the initial code to be
1175 cleaned up (e.g. performing optimizations that depend on knowing that the
1176 operators have restricted type inputs). Subsequent runs of the pass clean up
1177 the messy code generated by the Legalize passes, which allows Legalize to be
1178 very simple (it can focus on making code legal instead of focusing on
1179 generating <em>good</em> and legal code).</p>
1181 <p>One important class of optimizations performed is optimizing inserted sign
1182 and zero extension instructions. We currently use ad-hoc techniques, but
1183 could move to more rigorous techniques in the future. Here are some good
1184 papers on the subject:</p>
1186 <p>"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
1187 integer arithmetic</a>"<br>
1188 Kevin Redwine and Norman Ramsey<br>
1189 International Conference on Compiler Construction (CC) 2004</p>
1191 <p>"<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
1192 sign extension elimination</a>"<br>
1193 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1194 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1195 and Implementation.</p>
1199 <!-- _______________________________________________________________________ -->
1201 <a name="selectiondag_select">SelectionDAG Select Phase</a>
1206 <p>The Select phase is the bulk of the target-specific code for instruction
1207 selection. This phase takes a legal SelectionDAG as input, pattern matches
1208 the instructions supported by the target to this DAG, and produces a new DAG
1209 of target code. For example, consider the following LLVM fragment:</p>
1211 <div class="doc_code">
1213 %t1 = fadd float %W, %X
1214 %t2 = fmul float %t1, %Y
1215 %t3 = fadd float %t2, %Z
1219 <p>This LLVM code corresponds to a SelectionDAG that looks basically like
1222 <div class="doc_code">
1224 (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
1228 <p>If a target supports floating point multiply-and-add (FMA) operations, one of
1229 the adds can be merged with the multiply. On the PowerPC, for example, the
1230 output of the instruction selector might look like this DAG:</p>
1232 <div class="doc_code">
1234 (FMADDS (FADDS W, X), Y, Z)
1238 <p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1239 first two operands and adds the third (as single-precision floating-point
1240 numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1241 add instruction. To perform this pattern match, the PowerPC backend includes
1242 the following instruction definitions:</p>
1244 <div class="doc_code">
1246 def FMADDS : AForm_1<59, 29,
1247 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1248 "fmadds $FRT, $FRA, $FRC, $FRB",
1249 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1250 F4RC:$FRB))</b>]>;
1251 def FADDS : AForm_2<59, 21,
1252 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1253 "fadds $FRT, $FRA, $FRB",
1254 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]>;
1258 <p>The portion of the instruction definition in bold indicates the pattern used
1259 to match the instruction. The DAG operators
1260 (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in
1261 the <tt>include/llvm/Target/TargetSelectionDAG.td</tt> file. "
1262 <tt>F4RC</tt>" is the register class of the input and result values.</p>
1264 <p>The TableGen DAG instruction selector generator reads the instruction
1265 patterns in the <tt>.td</tt> file and automatically builds parts of the
1266 pattern matching code for your target. It has the following strengths:</p>
1269 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1270 you if your patterns make sense or not.</li>
1272 <li>It can handle arbitrary constraints on operands for the pattern match. In
1273 particular, it is straight-forward to say things like "match any immediate
1274 that is a 13-bit sign-extended value". For examples, see the
1275 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1278 <li>It knows several important identities for the patterns defined. For
1279 example, it knows that addition is commutative, so it allows the
1280 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1281 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1282 to specially handle this case.</li>
1284 <li>It has a full-featured type-inferencing system. In particular, you should
1285 rarely have to explicitly tell the system what type parts of your patterns
1286 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1287 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'.
1288 It was able to infer and propagate this knowledge from the fact that
1289 <tt>F4RC</tt> has type 'f32'.</li>
1291 <li>Targets can define their own (and rely on built-in) "pattern fragments".
1292 Pattern fragments are chunks of reusable patterns that get inlined into
1293 your patterns during compiler-compiler time. For example, the integer
1294 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1295 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1296 have a native '<tt>not</tt>' operation. Targets can define their own
1297 short-hand fragments as they see fit. See the definition of
1298 '<tt>not</tt>' and '<tt>ineg</tt>' for examples.</li>
1300 <li>In addition to instructions, targets can specify arbitrary patterns that
1301 map to one or more instructions using the 'Pat' class. For example, the
1302 PowerPC has no way to load an arbitrary integer immediate into a register
1303 in one instruction. To tell tblgen how to do this, it defines:
1306 <div class="doc_code">
1308 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1309 def : Pat<(i32 imm:$imm),
1310 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1314 If none of the single-instruction patterns for loading an immediate into a
1315 register match, this will be used. This rule says "match an arbitrary i32
1316 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1317 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1318 the left 16 bits') instruction". To make this work, the
1319 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate
1320 the input immediate (in this case, take the high or low 16-bits of the
1323 <li>While the system does automate a lot, it still allows you to write custom
1324 C++ code to match special cases if there is something that is hard to
1328 <p>While it has many strengths, the system currently has some limitations,
1329 primarily because it is a work in progress and is not yet finished:</p>
1332 <li>Overall, there is no way to define or match SelectionDAG nodes that define
1333 multiple values (e.g. <tt>SMUL_LOHI</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1334 etc). This is the biggest reason that you currently still <em>have
1335 to</em> write custom C++ code for your instruction selector.</li>
1337 <li>There is no great way to support matching complex addressing modes yet.
1338 In the future, we will extend pattern fragments to allow them to define
1339 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1340 addressing mode</a>, which are currently matched with custom C++ code).
1341 In addition, we'll extend fragments so that a fragment can match multiple
1342 different patterns.</li>
1344 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
1346 <li>We don't automatically generate the set of supported registers and
1347 operations for the <a href="#selectiondag_legalize">Legalizer</a>
1350 <li>We don't have a way of tying in custom legalized nodes yet.</li>
1353 <p>Despite these limitations, the instruction selector generator is still quite
1354 useful for most of the binary and logical operations in typical instruction
1355 sets. If you run into any problems or can't figure out how to do something,
1356 please let Chris know!</p>
1360 <!-- _______________________________________________________________________ -->
1362 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
1367 <p>The scheduling phase takes the DAG of target instructions from the selection
1368 phase and assigns an order. The scheduler can pick an order depending on
1369 various constraints of the machines (i.e. order for minimal register pressure
1370 or try to cover instruction latencies). Once an order is established, the
1371 DAG is converted to a list
1372 of <tt><a href="#machineinstr">MachineInstr</a></tt>s and the SelectionDAG is
1375 <p>Note that this phase is logically separate from the instruction selection
1376 phase, but is tied to it closely in the code because it operates on
1381 <!-- _______________________________________________________________________ -->
1383 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1389 <li>Optional function-at-a-time selection.</li>
1391 <li>Auto-generate entire selector from <tt>.td</tt> file.</li>
1398 <!-- ======================================================================= -->
1400 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1402 <div><p>To Be Written</p></div>
1404 <!-- ======================================================================= -->
1406 <a name="liveintervals">Live Intervals</a>
1411 <p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1412 They are used by some <a href="#regalloc">register allocator</a> passes to
1413 determine if two or more virtual registers which require the same physical
1414 register are live at the same point in the program (i.e., they conflict).
1415 When this situation occurs, one virtual register must be <i>spilled</i>.</p>
1417 <!-- _______________________________________________________________________ -->
1419 <a name="livevariable_analysis">Live Variable Analysis</a>
1424 <p>The first step in determining the live intervals of variables is to calculate
1425 the set of registers that are immediately dead after the instruction (i.e.,
1426 the instruction calculates the value, but it is never used) and the set of
1427 registers that are used by the instruction, but are never used after the
1428 instruction (i.e., they are killed). Live variable information is computed
1429 for each <i>virtual</i> register and <i>register allocatable</i> physical
1430 register in the function. This is done in a very efficient manner because it
1431 uses SSA to sparsely compute lifetime information for virtual registers
1432 (which are in SSA form) and only has to track physical registers within a
1433 block. Before register allocation, LLVM can assume that physical registers
1434 are only live within a single basic block. This allows it to do a single,
1435 local analysis to resolve physical register lifetimes within each basic
1436 block. If a physical register is not register allocatable (e.g., a stack
1437 pointer or condition codes), it is not tracked.</p>
1439 <p>Physical registers may be live in to or out of a function. Live in values are
1440 typically arguments in registers. Live out values are typically return values
1441 in registers. Live in values are marked as such, and are given a dummy
1442 "defining" instruction during live intervals analysis. If the last basic
1443 block of a function is a <tt>return</tt>, then it's marked as using all live
1444 out values in the function.</p>
1446 <p><tt>PHI</tt> nodes need to be handled specially, because the calculation of
1447 the live variable information from a depth first traversal of the CFG of the
1448 function won't guarantee that a virtual register used by the <tt>PHI</tt>
1449 node is defined before it's used. When a <tt>PHI</tt> node is encountered,
1450 only the definition is handled, because the uses will be handled in other
1453 <p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1454 assignment at the end of the current basic block and traverse the successor
1455 basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1456 the <tt>PHI</tt> node's operands is coming from the current basic block, then
1457 the variable is marked as <i>alive</i> within the current basic block and all
1458 of its predecessor basic blocks, until the basic block with the defining
1459 instruction is encountered.</p>
1463 <!-- _______________________________________________________________________ -->
1465 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1470 <p>We now have the information available to perform the live intervals analysis
1471 and build the live intervals themselves. We start off by numbering the basic
1472 blocks and machine instructions. We then handle the "live-in" values. These
1473 are in physical registers, so the physical register is assumed to be killed
1474 by the end of the basic block. Live intervals for virtual registers are
1475 computed for some ordering of the machine instructions <tt>[1, N]</tt>. A
1476 live interval is an interval <tt>[i, j)</tt>, where <tt>1 <= i <= j
1477 < N</tt>, for which a variable is live.</p>
1479 <p><i><b>More to come...</b></i></p>
1485 <!-- ======================================================================= -->
1487 <a name="regalloc">Register Allocation</a>
1492 <p>The <i>Register Allocation problem</i> consists in mapping a program
1493 <i>P<sub>v</sub></i>, that can use an unbounded number of virtual registers,
1494 to a program <i>P<sub>p</sub></i> that contains a finite (possibly small)
1495 number of physical registers. Each target architecture has a different number
1496 of physical registers. If the number of physical registers is not enough to
1497 accommodate all the virtual registers, some of them will have to be mapped
1498 into memory. These virtuals are called <i>spilled virtuals</i>.</p>
1500 <!-- _______________________________________________________________________ -->
1503 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1508 <p>In LLVM, physical registers are denoted by integer numbers that normally
1509 range from 1 to 1023. To see how this numbering is defined for a particular
1510 architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that
1511 architecture. For instance, by
1512 inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the
1513 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register
1514 <tt>MM0</tt> is mapped to 48.</p>
1516 <p>Some architectures contain registers that share the same physical location. A
1517 notable example is the X86 platform. For instance, in the X86 architecture,
1518 the registers <tt>EAX</tt>, <tt>AX</tt> and <tt>AL</tt> share the first eight
1519 bits. These physical registers are marked as <i>aliased</i> in LLVM. Given a
1520 particular architecture, you can check which registers are aliased by
1521 inspecting its <tt>RegisterInfo.td</tt> file. Moreover, the method
1522 <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1523 all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1525 <p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1526 Elements in the same register class are functionally equivalent, and can be
1527 interchangeably used. Each virtual register can only be mapped to physical
1528 registers of a particular class. For instance, in the X86 architecture, some
1529 virtuals can only be allocated to 8 bit registers. A register class is
1530 described by <tt>TargetRegisterClass</tt> objects. To discover if a virtual
1531 register is compatible with a given physical, this code can be used:</p>
1533 <div class="doc_code">
1535 bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1538 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
1539 "Target register must be physical");
1540 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1541 return trc->contains(p_reg);
1546 <p>Sometimes, mostly for debugging purposes, it is useful to change the number
1547 of physical registers available in the target architecture. This must be done
1548 statically, inside the <tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt>
1549 for <tt>RegisterClass</tt>, the last parameter of which is a list of
1550 registers. Just commenting some out is one simple way to avoid them being
1551 used. A more polite way is to explicitly exclude some registers from
1552 the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
1553 class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
1556 <p>Virtual registers are also denoted by integer numbers. Contrary to physical
1557 registers, different virtual registers never share the same number. Whereas
1558 physical registers are statically defined in a <tt>TargetRegisterInfo.td</tt>
1559 file and cannot be created by the application developer, that is not the case
1560 with virtual registers. In order to create new virtual registers, use the
1561 method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
1562 will return a new virtual register. Use an <tt>IndexedMap<Foo,
1563 VirtReg2IndexFunctor></tt> to hold information per virtual register. If you
1564 need to enumerate all virtual registers, use the function
1565 <tt>TargetRegisterInfo::index2VirtReg()</tt> to find the virtual register
1568 <div class="doc_code">
1570 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1571 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
1577 <p>Before register allocation, the operands of an instruction are mostly virtual
1578 registers, although physical registers may also be used. In order to check if
1579 a given machine operand is a register, use the boolean
1580 function <tt>MachineOperand::isRegister()</tt>. To obtain the integer code of
1581 a register, use <tt>MachineOperand::getReg()</tt>. An instruction may define
1582 or use a register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1583 defines the registers 1024, and uses registers 1025 and 1026. Given a
1584 register operand, the method <tt>MachineOperand::isUse()</tt> informs if that
1585 register is being used by the instruction. The
1586 method <tt>MachineOperand::isDef()</tt> informs if that registers is being
1589 <p>We will call physical registers present in the LLVM bitcode before register
1590 allocation <i>pre-colored registers</i>. Pre-colored registers are used in
1591 many different situations, for instance, to pass parameters of functions
1592 calls, and to store results of particular instructions. There are two types
1593 of pre-colored registers: the ones <i>implicitly</i> defined, and
1594 those <i>explicitly</i> defined. Explicitly defined registers are normal
1595 operands, and can be accessed
1596 with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In order to check
1597 which registers are implicitly defined by an instruction, use
1598 the <tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>,
1599 where <tt>opcode</tt> is the opcode of the target instruction. One important
1600 difference between explicit and implicit physical registers is that the
1601 latter are defined statically for each instruction, whereas the former may
1602 vary depending on the program being compiled. For example, an instruction
1603 that represents a function call will always implicitly define or use the same
1604 set of physical registers. To read the registers implicitly used by an
1606 use <tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1607 registers impose constraints on any register allocation algorithm. The
1608 register allocator must make sure that none of them are overwritten by
1609 the values of virtual registers while still alive.</p>
1613 <!-- _______________________________________________________________________ -->
1616 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1621 <p>There are two ways to map virtual registers to physical registers (or to
1622 memory slots). The first way, that we will call <i>direct mapping</i>, is
1623 based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
1624 and <tt>MachineOperand</tt>. The second way, that we will call <i>indirect
1625 mapping</i>, relies on the <tt>VirtRegMap</tt> class in order to insert loads
1626 and stores sending and getting values to and from memory.</p>
1628 <p>The direct mapping provides more flexibility to the developer of the register
1629 allocator; however, it is more error prone, and demands more implementation
1630 work. Basically, the programmer will have to specify where load and store
1631 instructions should be inserted in the target function being compiled in
1632 order to get and store values in memory. To assign a physical register to a
1633 virtual register present in a given operand,
1634 use <tt>MachineOperand::setReg(p_reg)</tt>. To insert a store instruction,
1635 use <tt>TargetInstrInfo::storeRegToStackSlot(...)</tt>, and to insert a
1636 load instruction, use <tt>TargetInstrInfo::loadRegFromStackSlot</tt>.</p>
1638 <p>The indirect mapping shields the application developer from the complexities
1639 of inserting load and store instructions. In order to map a virtual register
1640 to a physical one, use <tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In
1641 order to map a certain virtual register to memory,
1642 use <tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will return
1643 the stack slot where <tt>vreg</tt>'s value will be located. If it is
1644 necessary to map another virtual register to the same stack slot,
1645 use <tt>VirtRegMap::assignVirt2StackSlot(vreg, stack_location)</tt>. One
1646 important point to consider when using the indirect mapping, is that even if
1647 a virtual register is mapped to memory, it still needs to be mapped to a
1648 physical register. This physical register is the location where the virtual
1649 register is supposed to be found before being stored or after being
1652 <p>If the indirect strategy is used, after all the virtual registers have been
1653 mapped to physical registers or stack slots, it is necessary to use a spiller
1654 object to place load and store instructions in the code. Every virtual that
1655 has been mapped to a stack slot will be stored to memory after been defined
1656 and will be loaded before being used. The implementation of the spiller tries
1657 to recycle load/store instructions, avoiding unnecessary instructions. For an
1658 example of how to invoke the spiller,
1659 see <tt>RegAllocLinearScan::runOnMachineFunction</tt>
1660 in <tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1664 <!-- _______________________________________________________________________ -->
1666 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1671 <p>With very rare exceptions (e.g., function calls), the LLVM machine code
1672 instructions are three address instructions. That is, each instruction is
1673 expected to define at most one register, and to use at most two registers.
1674 However, some architectures use two address instructions. In this case, the
1675 defined register is also one of the used register. For instance, an
1676 instruction such as <tt>ADD %EAX, %EBX</tt>, in X86 is actually equivalent
1677 to <tt>%EAX = %EAX + %EBX</tt>.</p>
1679 <p>In order to produce correct code, LLVM must convert three address
1680 instructions that represent two address instructions into true two address
1681 instructions. LLVM provides the pass <tt>TwoAddressInstructionPass</tt> for
1682 this specific purpose. It must be run before register allocation takes
1683 place. After its execution, the resulting code may no longer be in SSA
1684 form. This happens, for instance, in situations where an instruction such
1685 as <tt>%a = ADD %b %c</tt> is converted to two instructions such as:</p>
1687 <div class="doc_code">
1694 <p>Notice that, internally, the second instruction is represented as
1695 <tt>ADD %a[def/use] %c</tt>. I.e., the register operand <tt>%a</tt> is both
1696 used and defined by the instruction.</p>
1700 <!-- _______________________________________________________________________ -->
1702 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1707 <p>An important transformation that happens during register allocation is called
1708 the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many analyses
1709 that are performed on the control flow graph of programs. However,
1710 traditional instruction sets do not implement PHI instructions. Thus, in
1711 order to generate executable code, compilers must replace PHI instructions
1712 with other instructions that preserve their semantics.</p>
1714 <p>There are many ways in which PHI instructions can safely be removed from the
1715 target code. The most traditional PHI deconstruction algorithm replaces PHI
1716 instructions with copy instructions. That is the strategy adopted by
1717 LLVM. The SSA deconstruction algorithm is implemented
1718 in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to invoke this pass, the
1719 identifier <tt>PHIEliminationID</tt> must be marked as required in the code
1720 of the register allocator.</p>
1724 <!-- _______________________________________________________________________ -->
1726 <a name="regAlloc_fold">Instruction folding</a>
1731 <p><i>Instruction folding</i> is an optimization performed during register
1732 allocation that removes unnecessary copy instructions. For instance, a
1733 sequence of instructions such as:</p>
1735 <div class="doc_code">
1737 %EBX = LOAD %mem_address
1742 <p>can be safely substituted by the single instruction:</p>
1744 <div class="doc_code">
1746 %EAX = LOAD %mem_address
1750 <p>Instructions can be folded with
1751 the <tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1752 taken when folding instructions; a folded instruction can be quite different
1754 instruction. See <tt>LiveIntervals::addIntervalsForSpills</tt>
1755 in <tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its
1760 <!-- _______________________________________________________________________ -->
1763 <a name="regAlloc_builtIn">Built in register allocators</a>
1768 <p>The LLVM infrastructure provides the application developer with three
1769 different register allocators:</p>
1772 <li><i>Fast</i> — This register allocator is the default for debug
1773 builds. It allocates registers on a basic block level, attempting to keep
1774 values in registers and reusing registers as appropriate.</li>
1776 <li><i>Basic</i> — This is an incremental approach to register
1777 allocation. Live ranges are assigned to registers one at a time in
1778 an order that is driven by heuristics. Since code can be rewritten
1779 on-the-fly during allocation, this framework allows interesting
1780 allocators to be developed as extensions. It is not itself a
1781 production register allocator but is a potentially useful
1782 stand-alone mode for triaging bugs and as a performance baseline.
1784 <li><i>Greedy</i> — <i>The default allocator</i>. This is a
1785 highly tuned implementation of the <i>Basic</i> allocator that
1786 incorporates global live range splitting. This allocator works hard
1787 to minimize the cost of spill code.
1789 <li><i>PBQP</i> — A Partitioned Boolean Quadratic Programming (PBQP)
1790 based register allocator. This allocator works by constructing a PBQP
1791 problem representing the register allocation problem under consideration,
1792 solving this using a PBQP solver, and mapping the solution back to a
1793 register assignment.</li>
1796 <p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1797 command line option <tt>-regalloc=...</tt>:</p>
1799 <div class="doc_code">
1801 $ llc -regalloc=linearscan file.bc -o ln.s;
1802 $ llc -regalloc=fast file.bc -o fa.s;
1803 $ llc -regalloc=pbqp file.bc -o pbqp.s;
1811 <!-- ======================================================================= -->
1813 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1816 <!-- _______________________________________________________________________ -->
1818 <a name="compact_unwind">Compact Unwind</a>
1823 <p>Throwing an exception requires <em>unwinding</em> out of a function. The
1824 information on how to unwind a given function is traditionally expressed in
1825 DWARF unwind (a.k.a. frame) info. But that format was originally developed
1826 for debuggers to backtrace, and each Frame Description Entry (FDE) requires
1827 ~20-30 bytes per function. There is also the cost of mapping from an address
1828 in a function to the corresponding FDE at runtime. An alternative unwind
1829 encoding is called <em>compact unwind</em> and requires just 4-bytes per
1832 <p>The compact unwind encoding is a 32-bit value, which is encoded in an
1833 architecture-specific way. It specifies which registers to restore and from
1834 where, and how to unwind out of the function. When the linker creates a final
1835 linked image, it will create a <code>__TEXT,__unwind_info</code>
1836 section. This section is a small and fast way for the runtime to access
1837 unwind info for any given function. If we emit compact unwind info for the
1838 function, that compact unwind info will be encoded in
1839 the <code>__TEXT,__unwind_info</code> section. If we emit DWARF unwind info,
1840 the <code>__TEXT,__unwind_info</code> section will contain the offset of the
1841 FDE in the <code>__TEXT,__eh_frame</code> section in the final linked
1844 <p>For X86, there are three modes for the compact unwind encoding:</p>
1847 <dt><i>Function with a Frame Pointer (<code>EBP</code> or <code>RBP</code>)</i></dt>
1848 <dd><p><code>EBP/RBP</code>-based frame, where <code>EBP/RBP</code> is pushed
1849 onto the stack immediately after the return address,
1850 then <code>ESP/RSP</code> is moved to <code>EBP/RBP</code>. Thus to
1851 unwind, <code>ESP/RSP</code> is restored with the
1852 current <code>EBP/RBP</code> value, then <code>EBP/RBP</code> is restored
1853 by popping the stack, and the return is done by popping the stack once
1854 more into the PC. All non-volatile registers that need to be restored must
1855 have been saved in a small range on the stack that
1856 starts <code>EBP-4</code> to <code>EBP-1020</code> (<code>RBP-8</code>
1857 to <code>RBP-1020</code>). The offset (divided by 4 in 32-bit mode and 8
1858 in 64-bit mode) is encoded in bits 16-23 (mask: <code>0x00FF0000</code>).
1859 The registers saved are encoded in bits 0-14
1860 (mask: <code>0x00007FFF</code>) as five 3-bit entries from the following
1862 <table border="1" cellspacing="0">
1864 <th>Compact Number</th>
1865 <th>i386 Register</th>
1866 <th>x86-64 Regiser</th>
1870 <td><code>EBX</code></td>
1871 <td><code>RBX</code></td>
1875 <td><code>ECX</code></td>
1876 <td><code>R12</code></td>
1880 <td><code>EDX</code></td>
1881 <td><code>R13</code></td>
1885 <td><code>EDI</code></td>
1886 <td><code>R14</code></td>
1890 <td><code>ESI</code></td>
1891 <td><code>R15</code></td>
1895 <td><code>EBP</code></td>
1896 <td><code>RBP</code></td>
1902 <dt><i>Frameless with a Small Constant Stack Size (<code>EBP</code>
1903 or <code>RBP</code> is not used as a frame pointer)</i></dt>
1904 <dd><p>To return, a constant (encoded in the compact unwind encoding) is added
1905 to the <code>ESP/RSP</code>. Then the return is done by popping the stack
1906 into the PC. All non-volatile registers that need to be restored must have
1907 been saved on the stack immediately after the return address. The stack
1908 size (divided by 4 in 32-bit mode and 8 in 64-bit mode) is encoded in bits
1909 16-23 (mask: <code>0x00FF0000</code>). There is a maximum stack size of
1910 1024 bytes in 32-bit mode and 2048 in 64-bit mode. The number of registers
1911 saved is encoded in bits 9-12 (mask: <code>0x00001C00</code>). Bits 0-9
1912 (mask: <code>0x000003FF</code>) contain which registers were saved and
1914 the <code>encodeCompactUnwindRegistersWithoutFrame()</code> function
1915 in <code>lib/Target/X86FrameLowering.cpp</code> for the encoding
1916 algorithm.)</p></dd>
1918 <dt><i>Frameless with a Large Constant Stack Size (<code>EBP</code>
1919 or <code>RBP</code> is not used as a frame pointer)</i></dt>
1920 <dd><p>This case is like the "Frameless with a Small Constant Stack Size"
1921 case, but the stack size is too large to encode in the compact unwind
1922 encoding. Instead it requires that the function contains "<code>subl
1923 $nnnnnn, %esp</code>" in its prolog. The compact encoding contains the
1924 offset to the <code>$nnnnnn</code> value in the function in bits 9-12
1925 (mask: <code>0x00001C00</code>).</p></dd>
1930 <!-- ======================================================================= -->
1932 <a name="latemco">Late Machine Code Optimizations</a>
1934 <div><p>To Be Written</p></div>
1936 <!-- ======================================================================= -->
1938 <a name="codeemit">Code Emission</a>
1943 <p>The code emission step of code generation is responsible for lowering from
1944 the code generator abstractions (like <a
1945 href="#machinefunction">MachineFunction</a>, <a
1946 href="#machineinstr">MachineInstr</a>, etc) down
1947 to the abstractions used by the MC layer (<a href="#mcinst">MCInst</a>,
1948 <a href="#mcstreamer">MCStreamer</a>, etc). This is
1949 done with a combination of several different classes: the (misnamed)
1950 target-independent AsmPrinter class, target-specific subclasses of AsmPrinter
1951 (such as SparcAsmPrinter), and the TargetLoweringObjectFile class.</p>
1953 <p>Since the MC layer works at the level of abstraction of object files, it
1954 doesn't have a notion of functions, global variables etc. Instead, it thinks
1955 about labels, directives, and instructions. A key class used at this time is
1956 the MCStreamer class. This is an abstract API that is implemented in different
1957 ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively
1958 an "assembler API". MCStreamer has one method per directive, such as EmitLabel,
1959 EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly
1963 <p>If you are interested in implementing a code generator for a target, there
1964 are three important things that you have to implement for your target:</p>
1967 <li>First, you need a subclass of AsmPrinter for your target. This class
1968 implements the general lowering process converting MachineFunction's into MC
1969 label constructs. The AsmPrinter base class provides a number of useful methods
1970 and routines, and also allows you to override the lowering process in some
1971 important ways. You should get much of the lowering for free if you are
1972 implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile
1973 class implements much of the common logic.</li>
1975 <li>Second, you need to implement an instruction printer for your target. The
1976 instruction printer takes an <a href="#mcinst">MCInst</a> and renders it to a
1977 raw_ostream as text. Most of this is automatically generated from the .td file
1978 (when you specify something like "<tt>add $dst, $src1, $src2</tt>" in the
1979 instructions), but you need to implement routines to print operands.</li>
1981 <li>Third, you need to implement code that lowers a <a
1982 href="#machineinstr">MachineInstr</a> to an MCInst, usually implemented in
1983 "<target>MCInstLower.cpp". This lowering process is often target
1984 specific, and is responsible for turning jump table entries, constant pool
1985 indices, global variable addresses, etc into MCLabels as appropriate. This
1986 translation layer is also responsible for expanding pseudo ops used by the code
1987 generator into the actual machine instructions they correspond to. The MCInsts
1988 that are generated by this are fed into the instruction printer or the encoder.
1993 <p>Finally, at your choosing, you can also implement an subclass of
1994 MCCodeEmitter which lowers MCInst's into machine code bytes and relocations.
1995 This is important if you want to support direct .o file emission, or would like
1996 to implement an assembler for your target.</p>
2002 <!-- *********************************************************************** -->
2004 <a name="nativeassembler">Implementing a Native Assembler</a>
2006 <!-- *********************************************************************** -->
2010 <p>Though you're probably reading this because you want to write or maintain a
2011 compiler backend, LLVM also fully supports building a native assemblers too.
2012 We've tried hard to automate the generation of the assembler from the .td files
2013 (in particular the instruction syntax and encodings), which means that a large
2014 part of the manual and repetitive data entry can be factored and shared with the
2017 <!-- ======================================================================= -->
2018 <h3 id="na_instparsing">Instruction Parsing</h3>
2020 <div><p>To Be Written</p></div>
2023 <!-- ======================================================================= -->
2024 <h3 id="na_instaliases">
2025 Instruction Alias Processing
2029 <p>Once the instruction is parsed, it enters the MatchInstructionImpl function.
2030 The MatchInstructionImpl function performs alias processing and then does
2031 actual matching.</p>
2033 <p>Alias processing is the phase that canonicalizes different lexical forms of
2034 the same instructions down to one representation. There are several different
2035 kinds of alias that are possible to implement and they are listed below in the
2036 order that they are processed (which is in order from simplest/weakest to most
2037 complex/powerful). Generally you want to use the first alias mechanism that
2038 meets the needs of your instruction, because it will allow a more concise
2041 <!-- _______________________________________________________________________ -->
2042 <h4>Mnemonic Aliases</h4>
2046 <p>The first phase of alias processing is simple instruction mnemonic
2047 remapping for classes of instructions which are allowed with two different
2048 mnemonics. This phase is a simple and unconditionally remapping from one input
2049 mnemonic to one output mnemonic. It isn't possible for this form of alias to
2050 look at the operands at all, so the remapping must apply for all forms of a
2051 given mnemonic. Mnemonic aliases are defined simply, for example X86 has:
2054 <div class="doc_code">
2056 def : MnemonicAlias<"cbw", "cbtw">;
2057 def : MnemonicAlias<"smovq", "movsq">;
2058 def : MnemonicAlias<"fldcww", "fldcw">;
2059 def : MnemonicAlias<"fucompi", "fucomip">;
2060 def : MnemonicAlias<"ud2a", "ud2">;
2064 <p>... and many others. With a MnemonicAlias definition, the mnemonic is
2065 remapped simply and directly. Though MnemonicAlias's can't look at any aspect
2066 of the instruction (such as the operands) they can depend on global modes (the
2067 same ones supported by the matcher), through a Requires clause:</p>
2069 <div class="doc_code">
2071 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
2072 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
2076 <p>In this example, the mnemonic gets mapped into different a new one depending
2077 on the current instruction set.</p>
2081 <!-- _______________________________________________________________________ -->
2082 <h4>Instruction Aliases</h4>
2086 <p>The most general phase of alias processing occurs while matching is
2087 happening: it provides new forms for the matcher to match along with a specific
2088 instruction to generate. An instruction alias has two parts: the string to
2089 match and the instruction to generate. For example:
2092 <div class="doc_code">
2094 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8 :$src)>;
2095 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
2096 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8 :$src)>;
2097 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)>;
2098 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8 :$src)>;
2099 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)>;
2100 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)>;
2104 <p>This shows a powerful example of the instruction aliases, matching the
2105 same mnemonic in multiple different ways depending on what operands are present
2106 in the assembly. The result of instruction aliases can include operands in a
2107 different order than the destination instruction, and can use an input
2108 multiple times, for example:</p>
2110 <div class="doc_code">
2112 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
2113 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
2114 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
2115 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
2119 <p>This example also shows that tied operands are only listed once. In the X86
2120 backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
2121 to the output). InstAliases take a flattened operand list without duplicates
2122 for tied operands. The result of an instruction alias can also use immediates
2123 and fixed physical registers which are added as simple immediate operands in the
2124 result, for example:</p>
2126 <div class="doc_code">
2128 // Fixed Immediate operand.
2129 def : InstAlias<"aad", (AAD8i8 10)>;
2131 // Fixed register operand.
2132 def : InstAlias<"fcomi", (COM_FIr ST1)>;
2135 def : InstAlias<"fcomi $reg", (COM_FIr RST:$reg)>;
2140 <p>Instruction aliases can also have a Requires clause to make them
2141 subtarget specific.</p>
2143 <p>If the back-end supports it, the instruction printer can automatically emit
2144 the alias rather than what's being aliased. It typically leads to better,
2145 more readable code. If it's better to print out what's being aliased, then
2146 pass a '0' as the third parameter to the InstAlias definition.</p>
2152 <!-- ======================================================================= -->
2153 <h3 id="na_matching">Instruction Matching</h3>
2155 <div><p>To Be Written</p></div>
2159 <!-- *********************************************************************** -->
2161 <a name="targetimpls">Target-specific Implementation Notes</a>
2163 <!-- *********************************************************************** -->
2167 <p>This section of the document explains features or design decisions that are
2168 specific to the code generator for a particular target. First we start
2169 with a table that summarizes what features are supported by each target.</p>
2171 <!-- ======================================================================= -->
2173 <a name="targetfeatures">Target Feature Matrix</a>
2178 <p>Note that this table does not include the C backend or Cpp backends, since
2179 they do not use the target independent code generator infrastructure. It also
2180 doesn't list features that are not supported fully by any target yet. It
2181 considers a feature to be supported if at least one subtarget supports it. A
2182 feature being supported means that it is useful and works for most cases, it
2183 does not indicate that there are zero known bugs in the implementation. Here
2187 <table border="1" cellspacing="0">
2191 <th>Partial Support</th>
2192 <th>Complete Support</th>
2195 <td class="unknown"></td>
2196 <td class="no"></td>
2197 <td class="partial"></td>
2198 <td class="yes"></td>
2202 <p>Here is the table:</p>
2204 <table width="689" border="1" cellspacing="0">
2206 <td colspan="13" align="center" style="background-color:#ffc">Target</td>
2224 <td><a href="#feat_reliable">is generally reliable</a></td>
2225 <td class="yes"></td> <!-- ARM -->
2226 <td class="unknown"></td> <!-- Alpha -->
2227 <td class="no"></td> <!-- CellSPU -->
2228 <td class="no"></td> <!-- MBlaze -->
2229 <td class="unknown"></td> <!-- MSP430 -->
2230 <td class="no"></td> <!-- Mips -->
2231 <td class="no"></td> <!-- PTX -->
2232 <td class="yes"></td> <!-- PowerPC -->
2233 <td class="yes"></td> <!-- Sparc -->
2234 <td class="yes"></td> <!-- X86 -->
2235 <td class="unknown"></td> <!-- XCore -->
2239 <td><a href="#feat_asmparser">assembly parser</a></td>
2240 <td class="no"></td> <!-- ARM -->
2241 <td class="no"></td> <!-- Alpha -->
2242 <td class="no"></td> <!-- CellSPU -->
2243 <td class="yes"></td> <!-- MBlaze -->
2244 <td class="no"></td> <!-- MSP430 -->
2245 <td class="no"></td> <!-- Mips -->
2246 <td class="no"></td> <!-- PTX -->
2247 <td class="no"></td> <!-- PowerPC -->
2248 <td class="no"></td> <!-- Sparc -->
2249 <td class="yes"></td> <!-- X86 -->
2250 <td class="no"></td> <!-- XCore -->
2254 <td><a href="#feat_disassembler">disassembler</a></td>
2255 <td class="yes"></td> <!-- ARM -->
2256 <td class="no"></td> <!-- Alpha -->
2257 <td class="no"></td> <!-- CellSPU -->
2258 <td class="yes"></td> <!-- MBlaze -->
2259 <td class="no"></td> <!-- MSP430 -->
2260 <td class="no"></td> <!-- Mips -->
2261 <td class="no"></td> <!-- PTX -->
2262 <td class="no"></td> <!-- PowerPC -->
2263 <td class="no"></td> <!-- Sparc -->
2264 <td class="yes"></td> <!-- X86 -->
2265 <td class="no"></td> <!-- XCore -->
2269 <td><a href="#feat_inlineasm">inline asm</a></td>
2270 <td class="yes"></td> <!-- ARM -->
2271 <td class="unknown"></td> <!-- Alpha -->
2272 <td class="no"></td> <!-- CellSPU -->
2273 <td class="yes"></td> <!-- MBlaze -->
2274 <td class="unknown"></td> <!-- MSP430 -->
2275 <td class="no"></td> <!-- Mips -->
2276 <td class="unknown"></td> <!-- PTX -->
2277 <td class="yes"></td> <!-- PowerPC -->
2278 <td class="unknown"></td> <!-- Sparc -->
2279 <td class="yes"></td> <!-- X86 -->
2280 <td class="unknown"></td> <!-- XCore -->
2284 <td><a href="#feat_jit">jit</a></td>
2285 <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
2286 <td class="no"></td> <!-- Alpha -->
2287 <td class="no"></td> <!-- CellSPU -->
2288 <td class="no"></td> <!-- MBlaze -->
2289 <td class="unknown"></td> <!-- MSP430 -->
2290 <td class="no"></td> <!-- Mips -->
2291 <td class="unknown"></td> <!-- PTX -->
2292 <td class="yes"></td> <!-- PowerPC -->
2293 <td class="unknown"></td> <!-- Sparc -->
2294 <td class="yes"></td> <!-- X86 -->
2295 <td class="unknown"></td> <!-- XCore -->
2299 <td><a href="#feat_objectwrite">.o file writing</a></td>
2300 <td class="no"></td> <!-- ARM -->
2301 <td class="no"></td> <!-- Alpha -->
2302 <td class="no"></td> <!-- CellSPU -->
2303 <td class="yes"></td> <!-- MBlaze -->
2304 <td class="no"></td> <!-- MSP430 -->
2305 <td class="no"></td> <!-- Mips -->
2306 <td class="no"></td> <!-- PTX -->
2307 <td class="no"></td> <!-- PowerPC -->
2308 <td class="no"></td> <!-- Sparc -->
2309 <td class="yes"></td> <!-- X86 -->
2310 <td class="no"></td> <!-- XCore -->
2314 <td><a href="#feat_tailcall">tail calls</a></td>
2315 <td class="yes"></td> <!-- ARM -->
2316 <td class="unknown"></td> <!-- Alpha -->
2317 <td class="no"></td> <!-- CellSPU -->
2318 <td class="no"></td> <!-- MBlaze -->
2319 <td class="unknown"></td> <!-- MSP430 -->
2320 <td class="no"></td> <!-- Mips -->
2321 <td class="unknown"></td> <!-- PTX -->
2322 <td class="yes"></td> <!-- PowerPC -->
2323 <td class="unknown"></td> <!-- Sparc -->
2324 <td class="yes"></td> <!-- X86 -->
2325 <td class="unknown"></td> <!-- XCore -->
2331 <!-- _______________________________________________________________________ -->
2332 <h4 id="feat_reliable">Is Generally Reliable</h4>
2335 <p>This box indicates whether the target is considered to be production quality.
2336 This indicates that the target has been used as a static compiler to
2337 compile large amounts of code by a variety of different people and is in
2341 <!-- _______________________________________________________________________ -->
2342 <h4 id="feat_asmparser">Assembly Parser</h4>
2345 <p>This box indicates whether the target supports parsing target specific .s
2346 files by implementing the MCAsmParser interface. This is required for llvm-mc
2347 to be able to act as a native assembler and is required for inline assembly
2348 support in the native .o file writer.</p>
2353 <!-- _______________________________________________________________________ -->
2354 <h4 id="feat_disassembler">Disassembler</h4>
2357 <p>This box indicates whether the target supports the MCDisassembler API for
2358 disassembling machine opcode bytes into MCInst's.</p>
2362 <!-- _______________________________________________________________________ -->
2363 <h4 id="feat_inlineasm">Inline Asm</h4>
2366 <p>This box indicates whether the target supports most popular inline assembly
2367 constraints and modifiers.</p>
2371 <!-- _______________________________________________________________________ -->
2372 <h4 id="feat_jit">JIT Support</h4>
2375 <p>This box indicates whether the target supports the JIT compiler through
2376 the ExecutionEngine interface.</p>
2378 <p id="feat_jit_arm">The ARM backend has basic support for integer code
2379 in ARM codegen mode, but lacks NEON and full Thumb support.</p>
2383 <!-- _______________________________________________________________________ -->
2384 <h4 id="feat_objectwrite">.o File Writing</h4>
2388 <p>This box indicates whether the target supports writing .o files (e.g. MachO,
2389 ELF, and/or COFF) files directly from the target. Note that the target also
2390 must include an assembly parser and general inline assembly support for full
2391 inline assembly support in the .o writer.</p>
2393 <p>Targets that don't support this feature can obviously still write out .o
2394 files, they just rely on having an external assembler to translate from a .s
2395 file to a .o file (as is the case for many C compilers).</p>
2399 <!-- _______________________________________________________________________ -->
2400 <h4 id="feat_tailcall">Tail Calls</h4>
2404 <p>This box indicates whether the target supports guaranteed tail calls. These
2405 are calls marked "<a href="LangRef.html#i_call">tail</a>" and use the fastcc
2406 calling convention. Please see the <a href="#tailcallopt">tail call section
2407 more more details</a>.</p>
2413 <!-- ======================================================================= -->
2415 <a name="tailcallopt">Tail call optimization</a>
2420 <p>Tail call optimization, callee reusing the stack of the caller, is currently
2421 supported on x86/x86-64 and PowerPC. It is performed if:</p>
2424 <li>Caller and callee have the calling convention <tt>fastcc</tt> or
2425 <tt>cc 10</tt> (GHC call convention).</li>
2427 <li>The call is a tail call - in tail position (ret immediately follows call
2428 and ret uses value of call or is void).</li>
2430 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
2432 <li>Platform specific constraints are met.</li>
2435 <p>x86/x86-64 constraints:</p>
2438 <li>No variable argument lists are used.</li>
2440 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility
2441 = hidden or protected) are supported.</li>
2444 <p>PowerPC constraints:</p>
2447 <li>No variable argument lists are used.</li>
2449 <li>No byval parameters are used.</li>
2451 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
2456 <p>Call as <tt>llc -tailcallopt test.ll</tt>.</p>
2458 <div class="doc_code">
2460 declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
2462 define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
2463 %l1 = add i32 %in1, %in2
2464 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
2470 <p>Implications of <tt>-tailcallopt</tt>:</p>
2472 <p>To support tail call optimization in situations where the callee has more
2473 arguments than the caller a 'callee pops arguments' convention is used. This
2474 currently causes each <tt>fastcc</tt> call that is not tail call optimized
2475 (because one or more of above constraints are not met) to be followed by a
2476 readjustment of the stack. So performance might be worse in such cases.</p>
2479 <!-- ======================================================================= -->
2481 <a name="sibcallopt">Sibling call optimization</a>
2486 <p>Sibling call optimization is a restricted form of tail call optimization.
2487 Unlike tail call optimization described in the previous section, it can be
2488 performed automatically on any tail calls when <tt>-tailcallopt</tt> option
2489 is not specified.</p>
2491 <p>Sibling call optimization is currently performed on x86/x86-64 when the
2492 following constraints are met:</p>
2495 <li>Caller and callee have the same calling convention. It can be either
2496 <tt>c</tt> or <tt>fastcc</tt>.
2498 <li>The call is a tail call - in tail position (ret immediately follows call
2499 and ret uses value of call or is void).</li>
2501 <li>Caller and callee have matching return type or the callee result is not
2504 <li>If any of the callee arguments are being passed in stack, they must be
2505 available in caller's own incoming argument stack and the frame offsets
2510 <div class="doc_code">
2512 declare i32 @bar(i32, i32)
2514 define i32 @foo(i32 %a, i32 %b, i32 %c) {
2516 %0 = tail call i32 @bar(i32 %a, i32 %b)
2523 <!-- ======================================================================= -->
2525 <a name="x86">The X86 backend</a>
2530 <p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
2531 code generator is capable of targeting a variety of x86-32 and x86-64
2532 processors, and includes support for ISA extensions such as MMX and SSE.</p>
2534 <!-- _______________________________________________________________________ -->
2536 <a name="x86_tt">X86 Target Triples supported</a>
2541 <p>The following are the known target triples that are supported by the X86
2542 backend. This is not an exhaustive list, and it would be useful to add those
2543 that people test.</p>
2546 <li><b>i686-pc-linux-gnu</b> — Linux</li>
2548 <li><b>i386-unknown-freebsd5.3</b> — FreeBSD 5.3</li>
2550 <li><b>i686-pc-cygwin</b> — Cygwin on Win32</li>
2552 <li><b>i686-pc-mingw32</b> — MingW on Win32</li>
2554 <li><b>i386-pc-mingw32msvc</b> — MingW crosscompiler on Linux</li>
2556 <li><b>i686-apple-darwin*</b> — Apple Darwin on X86</li>
2558 <li><b>x86_64-unknown-linux-gnu</b> — Linux</li>
2563 <!-- _______________________________________________________________________ -->
2565 <a name="x86_cc">X86 Calling Conventions supported</a>
2571 <p>The following target-specific calling conventions are known to backend:</p>
2574 <li><b>x86_StdCall</b> — stdcall calling convention seen on Microsoft
2575 Windows platform (CC ID = 64).</li>
2576 <li><b>x86_FastCall</b> — fastcall calling convention seen on Microsoft
2577 Windows platform (CC ID = 65).</li>
2578 <li><b>x86_ThisCall</b> — Similar to X86_StdCall. Passes first argument
2579 in ECX, others via stack. Callee is responsible for stack cleaning. This
2580 convention is used by MSVC by default for methods in its ABI
2586 <!-- _______________________________________________________________________ -->
2588 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
2593 <p>The x86 has a very flexible way of accessing memory. It is capable of
2594 forming memory addresses of the following expression directly in integer
2595 instructions (which use ModR/M addressing):</p>
2597 <div class="doc_code">
2599 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
2603 <p>In order to represent this, LLVM tracks no less than 5 operands for each
2604 memory operand of this form. This means that the "load" form of
2605 '<tt>mov</tt>' has the following <tt>MachineOperand</tt>s in this order:</p>
2607 <div class="doc_code">
2609 Index: 0 | 1 2 3 4 5
2610 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
2611 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
2615 <p>Stores, and all other instructions, treat the four memory operands in the
2616 same way and in the same order. If the segment register is unspecified
2617 (regno = 0), then no segment override is generated. "Lea" operations do not
2618 have a segment register specified, so they only have 4 operands for their
2619 memory reference.</p>
2623 <!-- _______________________________________________________________________ -->
2625 <a name="x86_memory">X86 address spaces supported</a>
2630 <p>x86 has a feature which provides
2631 the ability to perform loads and stores to different address spaces
2632 via the x86 segment registers. A segment override prefix byte on an
2633 instruction causes the instruction's memory access to go to the specified
2634 segment. LLVM address space 0 is the default address space, which includes
2635 the stack, and any unqualified memory accesses in a program. Address spaces
2636 1-255 are currently reserved for user-defined code. The GS-segment is
2637 represented by address space 256, while the FS-segment is represented by
2638 address space 257. Other x86 segments have yet to be allocated address space
2641 <p>While these address spaces may seem similar to TLS via the
2642 <tt>thread_local</tt> keyword, and often use the same underlying hardware,
2643 there are some fundamental differences.</p>
2645 <p>The <tt>thread_local</tt> keyword applies to global variables and
2646 specifies that they are to be allocated in thread-local memory. There are
2647 no type qualifiers involved, and these variables can be pointed to with
2648 normal pointers and accessed with normal loads and stores.
2649 The <tt>thread_local</tt> keyword is target-independent at the LLVM IR
2650 level (though LLVM doesn't yet have implementations of it for some
2653 <p>Special address spaces, in contrast, apply to static types. Every
2654 load and store has a particular address space in its address operand type,
2655 and this is what determines which address space is accessed.
2656 LLVM ignores these special address space qualifiers on global variables,
2657 and does not provide a way to directly allocate storage in them.
2658 At the LLVM IR level, the behavior of these special address spaces depends
2659 in part on the underlying OS or runtime environment, and they are specific
2660 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
2662 <p>Some operating systems and runtime environments use (or may in the future
2663 use) the FS/GS-segment registers for various low-level purposes, so care
2664 should be taken when considering them.</p>
2668 <!-- _______________________________________________________________________ -->
2670 <a name="x86_names">Instruction naming</a>
2675 <p>An instruction name consists of the base name, a default operand size, and a
2676 a character per operand with an optional special size. For example:</p>
2678 <div class="doc_code">
2680 ADD8rr -> add, 8-bit register, 8-bit register
2681 IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
2682 IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
2683 MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
2691 <!-- ======================================================================= -->
2693 <a name="ppc">The PowerPC backend</a>
2698 <p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
2699 code generation is retargetable to several variations or <i>subtargets</i> of
2700 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
2702 <!-- _______________________________________________________________________ -->
2704 <a name="ppc_abi">LLVM PowerPC ABI</a>
2709 <p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
2710 relative (PIC) or static addressing for accessing global values, so no TOC
2711 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
2712 of a stack frame. LLVM takes advantage of having no TOC to provide space to
2713 save the frame pointer in the PowerPC linkage area of the caller frame.
2714 Other details of PowerPC ABI can be found at <a href=
2715 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
2716 >PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The 64 bit ABI
2717 is similar except space for GPRs are 8 bytes wide (not 4) and r13 is reserved
2722 <!-- _______________________________________________________________________ -->
2724 <a name="ppc_frame">Frame Layout</a>
2729 <p>The size of a PowerPC frame is usually fixed for the duration of a
2730 function's invocation. Since the frame is fixed size, all references
2731 into the frame can be accessed via fixed offsets from the stack pointer. The
2732 exception to this is when dynamic alloca or variable sized arrays are
2733 present, then a base pointer (r31) is used as a proxy for the stack pointer
2734 and stack pointer is free to grow or shrink. A base pointer is also used if
2735 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
2736 always aligned to 16 bytes, so that space allocated for altivec vectors will
2737 be properly aligned.</p>
2739 <p>An invocation frame is laid out as follows (low memory at top);</p>
2741 <table class="layout">
2743 <td>Linkage<br><br></td>
2746 <td>Parameter area<br><br></td>
2749 <td>Dynamic area<br><br></td>
2752 <td>Locals area<br><br></td>
2755 <td>Saved registers area<br><br></td>
2757 <tr style="border-style: none hidden none hidden;">
2761 <td>Previous Frame<br><br></td>
2765 <p>The <i>linkage</i> area is used by a callee to save special registers prior
2766 to allocating its own frame. Only three entries are relevant to LLVM. The
2767 first entry is the previous stack pointer (sp), aka link. This allows
2768 probing tools like gdb or exception handlers to quickly scan the frames in
2769 the stack. A function epilog can also use the link to pop the frame from the
2770 stack. The third entry in the linkage area is used to save the return
2771 address from the lr register. Finally, as mentioned above, the last entry is
2772 used to save the previous frame pointer (r31.) The entries in the linkage
2773 area are the size of a GPR, thus the linkage area is 24 bytes long in 32 bit
2774 mode and 48 bytes in 64 bit mode.</p>
2776 <p>32 bit linkage area</p>
2778 <table class="layout">
2781 <td>Saved SP (r1)</td>
2801 <td>Saved FP (r31)</td>
2805 <p>64 bit linkage area</p>
2807 <table class="layout">
2810 <td>Saved SP (r1)</td>
2830 <td>Saved FP (r31)</td>
2834 <p>The <i>parameter area</i> is used to store arguments being passed to a callee
2835 function. Following the PowerPC ABI, the first few arguments are actually
2836 passed in registers, with the space in the parameter area unused. However,
2837 if there are not enough registers or the callee is a thunk or vararg
2838 function, these register arguments can be spilled into the parameter area.
2839 Thus, the parameter area must be large enough to store all the parameters for
2840 the largest call sequence made by the caller. The size must also be
2841 minimally large enough to spill registers r3-r10. This allows callees blind
2842 to the call signature, such as thunks and vararg functions, enough space to
2843 cache the argument registers. Therefore, the parameter area is minimally 32
2844 bytes (64 bytes in 64 bit mode.) Also note that since the parameter area is
2845 a fixed offset from the top of the frame, that a callee can access its spilt
2846 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
2848 <p>Combining the information about the linkage, parameter areas and alignment. A
2849 stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
2852 <p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
2853 alloca then space is added to the stack, the linkage and parameter areas are
2854 shifted to top of stack, and the new space is available immediately below the
2855 linkage and parameter areas. The cost of shifting the linkage and parameter
2856 areas is minor since only the link value needs to be copied. The link value
2857 can be easily fetched by adding the original frame size to the base pointer.
2858 Note that allocations in the dynamic space need to observe 16 byte
2861 <p>The <i>locals area</i> is where the llvm compiler reserves space for local
2864 <p>The <i>saved registers area</i> is where the llvm compiler spills callee
2865 saved registers on entry to the callee.</p>
2869 <!-- _______________________________________________________________________ -->
2871 <a name="ppc_prolog">Prolog/Epilog</a>
2876 <p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
2877 the following exceptions. Callee saved registers are spilled after the frame
2878 is created. This allows the llvm epilog/prolog support to be common with
2879 other targets. The base pointer callee saved register r31 is saved in the
2880 TOC slot of linkage area. This simplifies allocation of space for the base
2881 pointer and makes it convenient to locate programatically and during
2886 <!-- _______________________________________________________________________ -->
2888 <a name="ppc_dynamic">Dynamic Allocation</a>
2893 <p><i>TODO - More to come.</i></p>
2899 <!-- ======================================================================= -->
2901 <a name="ptx">The PTX backend</a>
2906 <p>The PTX code generator lives in the lib/Target/PTX directory. It is
2907 currently a work-in-progress, but already supports most of the code
2908 generation functionality needed to generate correct PTX kernels for
2911 <p>The code generator can target PTX 2.0+, and shader model 1.0+. The
2912 PTX ISA Reference Manual is used as the primary source of ISA
2913 information, though an effort is made to make the output of the code
2914 generator match the output of the NVidia nvcc compiler, whenever
2917 <p>Code Generator Options:</p>
2918 <table border="1" cellspacing="0">
2921 <th>Description</th>
2924 <td><code>double</code></td>
2925 <td align="left">If enabled, the map_f64_to_f32 directive is
2926 disabled in the PTX output, allowing native double-precision
2930 <td><code>no-fma</code></td>
2931 <td align="left">Disable generation of Fused-Multiply Add
2932 instructions, which may be beneficial for some devices</td>
2935 <td><code>smxy / computexy</code></td>
2936 <td align="left">Set shader model/compute capability to x.y,
2937 e.g. sm20 or compute13</td>
2943 <li>Arithmetic instruction selection (including combo FMA)</li>
2944 <li>Bitwise instruction selection</li>
2945 <li>Control-flow instruction selection</li>
2946 <li>Function calls (only on SM 2.0+ and no return arguments)</li>
2947 <li>Addresses spaces (0 = global, 1 = constant, 2 = local, 4 =
2949 <li>Thread synchronization (bar.sync)</li>
2950 <li>Special register reads ([N]TID, [N]CTAID, PMx, CLOCK, etc.)</li>
2955 <li>Robust call instruction selection</li>
2956 <li>Stack frame allocation</li>
2957 <li>Device-specific instruction scheduling optimizations</li>
2965 <!-- *********************************************************************** -->
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2973 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
2974 <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a><br>
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