clk: fractional-divider: cast parent_rate to u64 before multiplying

On 32bit architectures, like ARM calculating the fractional rate will
do the multiplication before converting the value to u64 when it gets
assigned to ret, which can produce overflows.

The error in question happened with a parent_rate of 386MHz, m = 3000,
n = 60000, which resulted in a wrong rate value of 15812Hz.

Therefore cast parent_rate to u64 to make sure the multiplication
happens in a 64bit space and produces the correct 192MHz in the example.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index ede685ca0d20b03ef5b9b6e6bd37c4d57e0db625..82a59d0086cc79d654c4ceaf4aa42a8491467dbc 100644 (file)
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -36,7 +36,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
        m = (val & fd->mmask) >> fd->mshift;
        n = (val & fd->nmask) >> fd->nshift;
 
-       ret = parent_rate * m;
+       ret = (u64)parent_rate * m;
        do_div(ret, n);
 
        return ret;