arm: rockchip: rk3228: dts: add DMAC support
authorXiao Feng <xf@rock-chips.com>
Sat, 10 Oct 2015 06:46:01 +0000 (14:46 +0800)
committerXiao Feng <xf@rock-chips.com>
Sat, 10 Oct 2015 07:32:26 +0000 (15:32 +0800)
Change-Id: Ic6f8a106e8ecdcdf153873a65b90567b3edb48ad
Signed-off-by: Xiao Feng <xf@rock-chips.com>
arch/arm/boot/dts/rk3228-fpga.dts
arch/arm/boot/dts/rk3228.dtsi

index 96534df8e2e8277dc88ff1919f25f0a87259d88d..ccbd7ba8f6ca49c1096e2d35e38597d1e90c90b8 100644 (file)
 
                        <&clk_gates1 3>;/*clk_jtag*/
        };
+
+       amba {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "arm,amba-bus";
+               interrupt-parent = <&gic>;
+               ranges;
+
+               pdma: pdma@110f0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x110f0000 0x4000>;
+                       clocks = <&clk_gates8 2>;
+                       clock-names = "apb_pclk";
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+               };
+       };
 };
index 5c552144d493cca7cf4e02bd72df8bb5b116b4ff..444ac875f2bf2cdf3f0cc92e8a588cb47a324ceb 100644 (file)
 
                        <&clk_gates1 3>;/*clk_jtag*/
        };
+
+       amba {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "arm,amba-bus";
+               interrupt-parent = <&gic>;
+               ranges;
+
+               pdma: pdma@110f0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x110f0000 0x4000>;
+                       clocks = <&clk_gates8 2>;
+                       clock-names = "apb_pclk";
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+               };
+       };
 };