arch/arm/boot/dts/rk3228-fpga.dts

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5
   6 #include "skeleton.dtsi"
   7 #include "rk3228-clocks.dtsi"
   8
   9 / {
  10         compatible = "rockchip,rk3228";
  11         interrupt-parent = <&gic>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu@0 {
  18                         device_type = "cpu";
  19                         compatible = "arm,cortex-a7";
  20                         reg = <0xf00>;
  21                 };
  22         };
  23
  24         gic: interrupt-controller@32010000 {
  25                 compatible = "arm,cortex-a15-gic";
  26                 interrupt-controller;
  27                 #interrupt-cells = <3>;
  28                 #address-cells = <0>;
  29                 reg = <0x32011000 0x1000>,
  30                       <0x32012000 0x1000>;
  31         };
  32
  33         timer {
  34                 compatible = "arm,armv7-timer";
  35                 interrupts = <GIC_PPI 13
  36                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  37                              <GIC_PPI 14
  38                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  39                 clock-frequency = <24000000>;
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <0x60000000 0x10000000>;
  45         };
  46
  47         chosen {
  48                 bootargs = "initrd=0x62000000,0x00180000 init=/init console=ttyFIQ0,115200 earlyprintk=uart8250-32bit,0x11030000";
  49         };
  50
  51         aliases {
  52                 serial2 = &uart_dbg;
  53         };
  54
  55         uart_dbg: serial@11030000 {
  56                 compatible = "rockchip,serial";
  57                 reg = <0x11030000 0x100>;
  58                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  59                 clock-frequency = <24000000>;
  60                 clocks = <&xin24m>, <&xin24m>;
  61                 clock-names = "sclk_uart", "pclk_uart";
  62                 reg-shift = <2>;
  63                 reg-io-width = <4>;
  64                 status = "disabled";
  65         };
  66
  67         fiq-debugger {
  68                 compatible = "rockchip,fiq-debugger";
  69                 rockchip,serial-id = <2>;
  70                 rockchip,signal-irq = <159>;
  71                 rockchip,wake-irq = <0>;
  72                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  73                 rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
  74                 //status = "disabled";
  75         };
  76
  77         ion {
  78                 compatible = "rockchip,ion";
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 /*
  83                 ion_carveout: rockchip,ion-heap@2 {
  84                         compatible = "rockchip,ion-heap";
  85                         rockchip,ion_heap = <2>;
  86                         reg = <0x42000000 0xc00000>;
  87                 };
  88                          */
  89                 ion_cma: rockchip,ion-heap@4 {
  90                         compatible = "rockchip,ion-heap";
  91                         rockchip,ion_heap = <4>;
  92                         reg = <0x00000000 0x4000000>;
  93                 };
  94                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
  95                         compatible = "rockchip,ion-heap";
  96                         rockchip,ion_heap = <0>;
  97                 };
  98         };
  99
 100         backlight: backlight {
 101                 compatible = "pwm-backlight";
 102                 brightness-levels = <255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240
 103                      239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220
 104                      219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200
 105                      199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180
 106                      179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
 107                      159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140
 108                      139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120
 109                      119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
 110                      99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70
 111                      69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
 112                      39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
 113                      9 8 7 6 5 4 3 2 1 0>;
 114                 default-brightness-level = <200>;
 115         };
 116
 117         vop: vop@20020000 {
 118                 compatible = "rockchip,rk3228-lcdc";
 119                 backlight = <&backlight>;
 120
 121                 rockchip,cabc_mode = <0>;
 122                 rockchip,prop = <1>;
 123                 rockchip,pwr18 = <0>;
 124                 rockchip,iommu-enabled = <1>;
 125                 reg = <0x20050000 0x300>;
 126                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 127                 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
 128                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 129         };
 130
 131         vop_mmu {
 132                 dbgname = "vop";
 133                 compatible = "rockchip,vop_mmu";
 134                 reg = <0x20053f00 0x100>;
 135                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 136                 interrupt-names = "vopb_mmu";
 137         };
 138
 139         fb: fb{
 140                 compatible = "rockchip,rk-fb";
 141                 rockchip,disp-mode = <0>;
 142         };
 143
 144         rk_screen: rk_screen{
 145                 compatible = "rockchip,screen";
 146                 disp_timings: display-timings {
 147                         native-mode = <&timing0>;
 148                         timing0: timing0 {
 149                                 screen-type = <SCREEN_RGB>;
 150                                 out-face    = <OUT_P888>;
 151                                 clock-frequency = <27000000>;
 152                                 hactive = <800>;
 153                                 vactive = <480>;
 154                                 hback-porch = <206>;
 155                                 hfront-porch = <40>;
 156                                 vback-porch = <25>;
 157                                 vfront-porch = <10>;
 158                                 hsync-len = <10>;
 159                                 vsync-len = <10>;
 160                                 hsync-active = <0>;
 161                                 vsync-active = <0>;
 162                                 de-active = <0>;
 163                                 pixelclk-active = <0>;
 164                                 swap-rb = <0>;
 165                                 swap-rg = <0>;
 166                                 swap-gb = <0>;
 167                         };
 168                 };
 169         };
 170
 171         rockchip_clocks_init: clocks-init{
 172                 compatible = "rockchip,clocks-init";
 173                 rockchip,clocks-init-parent =
 174                         <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
 175                         <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
 176                         <&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
 177                         <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
 178                         <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
 179                         <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
 180                         <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
 181                 rockchip,clocks-init-rate =
 182                         <&clk_gpll 600000000>, <&clk_core 700000000>,
 183                         <&clk_cpll 500000000>, <&aclk_bus 250000000>,
 184                         <&hclk_bus 125000000>, <&pclk_bus 62500000>,
 185                         <&aclk_peri 250000000>, <&hclk_peri 125000000>,
 186                         <&pclk_peri 62500000>, <&clk_mac 125000000>,
 187                         <&aclk_iep 250000000>, <&hclk_vio 125000000>,
 188                         <&aclk_rga 250000000>, <&aclk_gpu 250000000>,
 189                         <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
 190                         <&clk_vdec_cabac 250000000>;
 191 /*
 192                 rockchip,clocks-uboot-has-init =
 193                         <&aclk_vio0>;
 194 */
 195         };
 196
 197         rockchip_clocks_enable: clocks-enable {
 198                 compatible = "rockchip,clocks-enable";
 199                 clocks =
 200                         /*PLL*/
 201                         <&clk_apll>,
 202                         <&clk_dpll>,
 203                         <&clk_gpll>,
 204                         <&clk_cpll>,
 205
 206                         /*PD_CORE*/
 207                         <&clk_core>,
 208                         <&pclk_dbg>,
 209                         <&aclk_core>,
 210                         <&clk_gates4 2>,
 211
 212                         /*PD_BUS*/
 213                         <&aclk_bus>,
 214                         <&hclk_bus>,
 215                         <&pclk_bus>,
 216                         <&clk_gates8 0>,/*aclk_intmem*/
 217                         <&clk_gates8 1>,/*clk_intmem_mbist*/
 218                         <&clk_gates8 3>,/*aclk_dmac_bus*/
 219                         <&clk_gates10 1>,/*g_aclk_bus*/
 220                         <&clk_gates13 9>,/*aclk_gic400*/
 221                         <&clk_gates8 3>,/*hclk_rom*/
 222                         <&clk_gates8 4>,/*pclk_ddrupctl*/
 223                         <&clk_gates8 6>,/*pclk_ddrmon*/
 224                         <&clk_gates9 4>,/*pclk_timer0*/
 225                         <&clk_gates9 5>,/*pclk_stimer*/
 226                         <&clk_gates10 0>,/*pclk_grf*/
 227                         <&clk_gates10 4>,/*pclk_cru*/
 228                         <&clk_gates10 6>,/*pclk_sgrf*/
 229                         <&clk_gates10 3>,/*pclk_ddrphy*/
 230                         <&clk_gates10 9>,/*pclk_phy_noc*/
 231
 232                         /*PD_PERI*/
 233                         <&aclk_peri>,
 234                         <&hclk_peri>,
 235                         <&pclk_peri>,
 236                         <&clk_gates12 0>,/*aclk_peri_noc*/
 237                         <&clk_gates12 1>,/*hclk_peri_noc*/
 238                         <&clk_gates12 2>,/*pclk_peri_noc*/
 239
 240                         <&clk_gates6 5>, /* g_clk_timer0 */
 241                         <&clk_gates6 6>, /* g_clk_timer1 */
 242
 243                         <&clk_gates7 14>, /* g_aclk_gpu */
 244                         <&clk_gates7 15>, /* g_aclk_gpu_noc */
 245
 246                         <&clk_gates1 3>;/*clk_jtag*/
 247         };
 248
 249         amba {
 250                 #address-cells = <1>;
 251                 #size-cells = <1>;
 252                 compatible = "arm,amba-bus";
 253                 interrupt-parent = <&gic>;
 254                 ranges;
 255
 256                 pdma: pdma@110f0000 {
 257                         compatible = "arm,pl330", "arm,primecell";
 258                         reg = <0x110f0000 0x4000>;
 259                         clocks = <&clk_gates8 2>;
 260                         clock-names = "apb_pclk";
 261                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 262                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 263                         #dma-cells = <1>;
 264                 };
 265         };
 266 };