ARM64: dts: rockchip: rk3368: add cpu dvfs support for sheep board

Change-Id: Id0361d55f970ea814c6965b2772f7cdc3a004bfc
Signed-off-by: Xiao Feng <xf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts b/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
index 0bdbb3bae8d8d57595256b9816e10e477cc37c5e..9251d6808365bbddfe94e253a9b0b8391bfab907 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
@@ -72,3 +72,11 @@
 &rk818 {
        status = "okay";
 };
+
+&cpu_l0 {
+       cpu-supply = <&syr827>;
+};
+
+&cpu_b0 {
+       cpu-supply = <&syr827>;
+};

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 33e628d997a39fbff15b0cef1fa7873dc0e7abac..7a1e33415fbaafd4cd52ad5fb7846295848546be 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -126,6 +126,8 @@
                        reg = <0x0 0x0>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKL>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu_l1: cpu@1 {
@@ -134,6 +136,7 @@
                        reg = <0x0 0x1>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu_l2: cpu@2 {
@@ -142,6 +145,7 @@
                        reg = <0x0 0x2>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu_l3: cpu@3 {
@@ -150,6 +154,7 @@
                        reg = <0x0 0x3>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu_b0: cpu@100 {
@@ -158,6 +163,8 @@
                        reg = <0x0 0x100>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLKB>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu_b1: cpu@101 {
@@ -166,6 +173,7 @@
                        reg = <0x0 0x101>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu_b2: cpu@102 {
@@ -174,6 +182,7 @@
                        reg = <0x0 0x102>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu_b3: cpu@103 {
@@ -182,6 +191,59 @@
                        reg = <0x0 0x103>;
                        cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+       };
+
+       cluster0_opp: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <408000000>;
+                       opp-microvolt = <1200000>;
+                       clock-latency-ns = <40000>;
+                       opp-suspend;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1200000>;
+               };
+       };
+
+       cluster1_opp: opp_table1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <408000000>;
+                       opp-microvolt = <1200000>;
+                       clock-latency-ns = <40000>;
+                       opp-suspend;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <1200000>;
                };
        };