arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3368-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3368";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 serial0 = &uart0;
  65                 serial1 = &uart1;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 serial4 = &uart4;
  69                 spi0 = &spi0;
  70                 spi1 = &spi1;
  71                 spi2 = &spi2;
  72                 lcdc = &lcdc;
  73         };
  74
  75         cpus {
  76                 #address-cells = <0x2>;
  77                 #size-cells = <0x0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_b0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_b1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_b2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_b3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_l0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_l1>;
 101                                 };
 102                                 core2 {
 103                                         cpu = <&cpu_l2>;
 104                                 };
 105                                 core3 {
 106                                         cpu = <&cpu_l3>;
 107                                 };
 108                         };
 109                 };
 110
 111                 idle-states {
 112                         entry-method = "psci";
 113
 114                         cpu_sleep: cpu-sleep-0 {
 115                                 compatible = "arm,idle-state";
 116                                 arm,psci-suspend-param = <0x1010000>;
 117                                 entry-latency-us = <0x3fffffff>;
 118                                 exit-latency-us = <0x40000000>;
 119                                 min-residency-us = <0xffffffff>;
 120                         };
 121                 };
 122
 123                 cpu_l0: cpu@0 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53", "arm,armv8";
 126                         reg = <0x0 0x0>;
 127                         cpu-idle-states = <&cpu_sleep>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         operating-points-v2 = <&cluster1_opp>;
 131                 };
 132
 133                 cpu_l1: cpu@1 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x1>;
 137                         cpu-idle-states = <&cpu_sleep>;
 138                         enable-method = "psci";
 139                         operating-points-v2 = <&cluster1_opp>;
 140                 };
 141
 142                 cpu_l2: cpu@2 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53", "arm,armv8";
 145                         reg = <0x0 0x2>;
 146                         cpu-idle-states = <&cpu_sleep>;
 147                         enable-method = "psci";
 148                         operating-points-v2 = <&cluster1_opp>;
 149                 };
 150
 151                 cpu_l3: cpu@3 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53", "arm,armv8";
 154                         reg = <0x0 0x3>;
 155                         cpu-idle-states = <&cpu_sleep>;
 156                         enable-method = "psci";
 157                         operating-points-v2 = <&cluster1_opp>;
 158                 };
 159
 160                 cpu_b0: cpu@100 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a53", "arm,armv8";
 163                         reg = <0x0 0x100>;
 164                         cpu-idle-states = <&cpu_sleep>;
 165                         enable-method = "psci";
 166                         clocks = <&cru ARMCLKB>;
 167                         operating-points-v2 = <&cluster0_opp>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a53", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         cpu-idle-states = <&cpu_sleep>;
 175                         enable-method = "psci";
 176                         operating-points-v2 = <&cluster0_opp>;
 177                 };
 178
 179                 cpu_b2: cpu@102 {
 180                         device_type = "cpu";
 181                         compatible = "arm,cortex-a53", "arm,armv8";
 182                         reg = <0x0 0x102>;
 183                         cpu-idle-states = <&cpu_sleep>;
 184                         enable-method = "psci";
 185                         operating-points-v2 = <&cluster0_opp>;
 186                 };
 187
 188                 cpu_b3: cpu@103 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a53", "arm,armv8";
 191                         reg = <0x0 0x103>;
 192                         cpu-idle-states = <&cpu_sleep>;
 193                         enable-method = "psci";
 194                         operating-points-v2 = <&cluster0_opp>;
 195                 };
 196         };
 197
 198         cluster0_opp: opp_table0 {
 199                 compatible = "operating-points-v2";
 200                 opp-shared;
 201
 202                 opp00 {
 203                         opp-hz = /bits/ 64 <408000000>;
 204                         opp-microvolt = <1200000>;
 205                         clock-latency-ns = <40000>;
 206                         opp-suspend;
 207                 };
 208                 opp01 {
 209                         opp-hz = /bits/ 64 <600000000>;
 210                         opp-microvolt = <1200000>;
 211                 };
 212                 opp02 {
 213                         opp-hz = /bits/ 64 <816000000>;
 214                         opp-microvolt = <1200000>;
 215                 };
 216                 opp03 {
 217                         opp-hz = /bits/ 64 <1008000000>;
 218                         opp-microvolt = <1200000>;
 219                 };
 220                 opp04 {
 221                         opp-hz = /bits/ 64 <1200000000>;
 222                         opp-microvolt = <1200000>;
 223                 };
 224         };
 225
 226         cluster1_opp: opp_table1 {
 227                 compatible = "operating-points-v2";
 228                 opp-shared;
 229
 230                 opp00 {
 231                         opp-hz = /bits/ 64 <408000000>;
 232                         opp-microvolt = <1200000>;
 233                         clock-latency-ns = <40000>;
 234                         opp-suspend;
 235                 };
 236                 opp01 {
 237                         opp-hz = /bits/ 64 <600000000>;
 238                         opp-microvolt = <1200000>;
 239                 };
 240                 opp02 {
 241                         opp-hz = /bits/ 64 <816000000>;
 242                         opp-microvolt = <1200000>;
 243                 };
 244                 opp03 {
 245                         opp-hz = /bits/ 64 <1008000000>;
 246                         opp-microvolt = <1200000>;
 247                 };
 248         };
 249
 250         arm-pmu {
 251                 compatible = "arm,armv8-pmuv3";
 252                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 260                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 261                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 262                                      <&cpu_b2>, <&cpu_b3>;
 263         };
 264
 265         amba {
 266                 compatible = "arm,amba-bus";
 267                 #address-cells = <2>;
 268                 #size-cells = <2>;
 269                 ranges;
 270
 271                 dmac_peri: dma-controller@ff250000 {
 272                         compatible = "arm,pl330", "arm,primecell";
 273                         reg = <0x0 0xff250000 0x0 0x4000>;
 274                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 276                         #dma-cells = <1>;
 277                         clocks = <&cru ACLK_DMAC_PERI>;
 278                         clock-names = "apb_pclk";
 279                 };
 280
 281                 dmac_bus: dma-controller@ff600000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff600000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC_BUS>;
 288                         clock-names = "apb_pclk";
 289                 };
 290         };
 291
 292         psci {
 293                 compatible = "arm,psci-0.2";
 294                 method = "smc";
 295         };
 296
 297         timer {
 298                 compatible = "arm,armv8-timer";
 299                 interrupts = <GIC_PPI 13
 300                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 301                              <GIC_PPI 14
 302                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 303                              <GIC_PPI 11
 304                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 305                              <GIC_PPI 10
 306                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 307         };
 308
 309         xin24m: oscillator {
 310                 compatible = "fixed-clock";
 311                 clock-frequency = <24000000>;
 312                 clock-output-names = "xin24m";
 313                 #clock-cells = <0>;
 314         };
 315
 316         sdmmc: rksdmmc@ff0c0000 {
 317                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 318                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 319                 clock-freq-min-max = <400000 150000000>;
 320                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 321                 clock-names = "biu", "ciu";
 322                 fifo-depth = <0x100>;
 323                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 324                 status = "disabled";
 325         };
 326
 327         sdio0: dwmmc@ff0d0000 {
 328                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 329                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 330                 clock-freq-min-max = <400000 150000000>;
 331                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 332                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 333                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 334                 fifo-depth = <0x100>;
 335                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 336                 status = "disabled";
 337         };
 338
 339         emmc: rksdmmc@ff0f0000 {
 340                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 341                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 342                 clock-freq-min-max = <400000 150000000>;
 343                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 344                 clock-names = "biu", "ciu";
 345                 fifo-depth = <0x100>;
 346                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 347                 status = "disabled";
 348         };
 349
 350         saradc: saradc@ff100000 {
 351                 compatible = "rockchip,saradc";
 352                 reg = <0x0 0xff100000 0x0 0x100>;
 353                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 354                 #io-channel-cells = <1>;
 355                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 356                 clock-names = "saradc", "apb_pclk";
 357                 status = "disabled";
 358         };
 359
 360         spi0: spi@ff110000 {
 361                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 362                 reg = <0x0 0xff110000 0x0 0x1000>;
 363                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 364                 clock-names = "spiclk", "apb_pclk";
 365                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 status = "disabled";
 371         };
 372
 373         spi1: spi@ff120000 {
 374                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 375                 reg = <0x0 0xff120000 0x0 0x1000>;
 376                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 377                 clock-names = "spiclk", "apb_pclk";
 378                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 status = "disabled";
 384         };
 385
 386         spi2: spi@ff130000 {
 387                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 388                 reg = <0x0 0xff130000 0x0 0x1000>;
 389                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 390                 clock-names = "spiclk", "apb_pclk";
 391                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 status = "disabled";
 397         };
 398
 399         i2c0: i2c@ff650000 {
 400                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 401                 reg = <0x0 0xff650000 0x0 0x1000>;
 402                 clocks = <&cru PCLK_I2C0>;
 403                 clock-names = "i2c";
 404                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&i2c0_xfer>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 status = "disabled";
 410         };
 411
 412         i2c2: i2c@ff140000 {
 413                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 414                 reg = <0x0 0xff140000 0x0 0x1000>;
 415                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clock-names = "i2c";
 419                 clocks = <&cru PCLK_I2C2>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&i2c2_xfer>;
 422                 status = "disabled";
 423         };
 424
 425         i2c3: i2c@ff150000 {
 426                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 427                 reg = <0x0 0xff150000 0x0 0x1000>;
 428                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clock-names = "i2c";
 432                 clocks = <&cru PCLK_I2C3>;
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&i2c3_xfer>;
 435                 status = "disabled";
 436         };
 437
 438         i2c4: i2c@ff160000 {
 439                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 440                 reg = <0x0 0xff160000 0x0 0x1000>;
 441                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 clock-names = "i2c";
 445                 clocks = <&cru PCLK_I2C4>;
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&i2c4_xfer>;
 448                 status = "disabled";
 449         };
 450
 451         i2c5: i2c@ff170000 {
 452                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 453                 reg = <0x0 0xff170000 0x0 0x1000>;
 454                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 clock-names = "i2c";
 458                 clocks = <&cru PCLK_I2C5>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&i2c5_xfer>;
 461                 status = "disabled";
 462         };
 463
 464         uart0: serial@ff180000 {
 465                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 466                 reg = <0x0 0xff180000 0x0 0x100>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 status = "disabled";
 474         };
 475
 476         uart1: serial@ff190000 {
 477                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 478                 reg = <0x0 0xff190000 0x0 0x100>;
 479                 clock-frequency = <24000000>;
 480                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 481                 clock-names = "baudclk", "apb_pclk";
 482                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 483                 reg-shift = <2>;
 484                 reg-io-width = <4>;
 485                 status = "disabled";
 486         };
 487
 488         uart3: serial@ff1b0000 {
 489                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 490                 reg = <0x0 0xff1b0000 0x0 0x100>;
 491                 clock-frequency = <24000000>;
 492                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 493                 clock-names = "baudclk", "apb_pclk";
 494                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 495                 reg-shift = <2>;
 496                 reg-io-width = <4>;
 497                 status = "disabled";
 498         };
 499
 500         uart4: serial@ff1c0000 {
 501                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 502                 reg = <0x0 0xff1c0000 0x0 0x100>;
 503                 clock-frequency = <24000000>;
 504                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 505                 clock-names = "baudclk", "apb_pclk";
 506                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 507                 reg-shift = <2>;
 508                 reg-io-width = <4>;
 509                 status = "disabled";
 510         };
 511
 512         gmac: ethernet@ff290000 {
 513                 compatible = "rockchip,rk3368-gmac";
 514                 reg = <0x0 0xff290000 0x0 0x10000>;
 515                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 516                 interrupt-names = "macirq";
 517                 rockchip,grf = <&grf>;
 518                 clocks = <&cru SCLK_MAC>,
 519                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 520                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 521                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 522                 clock-names = "stmmaceth",
 523                         "mac_clk_rx", "mac_clk_tx",
 524                         "clk_mac_ref", "clk_mac_refout",
 525                         "aclk_mac", "pclk_mac";
 526                 status = "disabled";
 527         };
 528
 529         usb_host0_ehci: usb@ff500000 {
 530                 compatible = "generic-ehci";
 531                 reg = <0x0 0xff500000 0x0 0x100>;
 532                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&cru HCLK_HOST0>;
 534                 clock-names = "usbhost";
 535                 status = "disabled";
 536         };
 537
 538         usb_otg: usb@ff580000 {
 539                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 540                                 "snps,dwc2";
 541                 reg = <0x0 0xff580000 0x0 0x40000>;
 542                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 543                 clocks = <&cru HCLK_OTG0>;
 544                 clock-names = "otg";
 545                 dr_mode = "otg";
 546                 g-np-tx-fifo-size = <16>;
 547                 g-rx-fifo-size = <275>;
 548                 g-tx-fifo-size = <256 128 128 64 64 32>;
 549                 g-use-dma;
 550                 status = "disabled";
 551         };
 552
 553         ddrpctl: syscon@ff610000 {
 554                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 555                 reg = <0x0 0xff610000 0x0 0x400>;
 556         };
 557
 558         i2c1: i2c@ff660000 {
 559                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 560                 reg = <0x0 0xff660000 0x0 0x1000>;
 561                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 clock-names = "i2c";
 565                 clocks = <&cru PCLK_I2C1>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c1_xfer>;
 568                 status = "disabled";
 569         };
 570
 571         pwm0: pwm@ff680000 {
 572                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 573                 reg = <0x0 0xff680000 0x0 0x10>;
 574                 #pwm-cells = <3>;
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&pwm0_pin>;
 577                 clocks = <&cru PCLK_PWM1>;
 578                 clock-names = "pwm";
 579                 status = "disabled";
 580         };
 581
 582         pwm1: pwm@ff680010 {
 583                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 584                 reg = <0x0 0xff680010 0x0 0x10>;
 585                 #pwm-cells = <3>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&pwm1_pin>;
 588                 clocks = <&cru PCLK_PWM1>;
 589                 clock-names = "pwm";
 590                 status = "disabled";
 591         };
 592
 593         pwm2: pwm@ff680020 {
 594                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 595                 reg = <0x0 0xff680020 0x0 0x10>;
 596                 #pwm-cells = <3>;
 597                 clocks = <&cru PCLK_PWM1>;
 598                 clock-names = "pwm";
 599                 status = "disabled";
 600         };
 601
 602         pwm3: pwm@ff680030 {
 603                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 604                 reg = <0x0 0xff680030 0x0 0x10>;
 605                 #pwm-cells = <3>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&pwm3_pin>;
 608                 clocks = <&cru PCLK_PWM1>;
 609                 clock-names = "pwm";
 610                 status = "disabled";
 611         };
 612
 613         uart2: serial@ff690000 {
 614                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 615                 reg = <0x0 0xff690000 0x0 0x100>;
 616                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 617                 clock-names = "baudclk", "apb_pclk";
 618                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&uart2_xfer>;
 621                 reg-shift = <2>;
 622                 reg-io-width = <4>;
 623                 status = "disabled";
 624         };
 625
 626         pmu: power-management@ff730000 {
 627                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 628                 reg = <0x0 0xff730000 0x0 0x1000>;
 629
 630                 power: power-controller {
 631                         status = "disabled";
 632                         compatible = "rockchip,rk3368-power-controller";
 633                         #power-domain-cells = <1>;
 634                         #address-cells = <1>;
 635                         #size-cells = <0>;
 636
 637                         /*
 638                          * Note: Although SCLK_* are the working clocks
 639                          * of device without including on the NOC, needed for
 640                          * synchronous reset.
 641                          *
 642                          * The clocks on the which NOC:
 643                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 644                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 645                          * ACLK_RGA is on ACLK_RGA_NIU.
 646                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 647                          *
 648                          * Which clock are device clocks:
 649                          *      clocks          devices
 650                          *      *_IEP           IEP:Image Enhancement Processor
 651                          *      *_ISP           ISP:Image Signal Processing
 652                          *      *_VIP           VIP:Video Input Processor
 653                          *      *_VOP*          VOP:Visual Output Processor
 654                          *      *_RGA           RGA
 655                          *      *_EDP*          EDP
 656                          *      *_DPHY*         LVDS
 657                          *      *_HDMI          HDMI
 658                          *      *_MIPI_*        MIPI
 659                          */
 660                         pd_vio {
 661                                 reg = <RK3368_PD_VIO>;
 662                                 clocks = <&cru ACLK_IEP>,
 663                                          <&cru ACLK_ISP>,
 664                                          <&cru ACLK_VIP>,
 665                                          <&cru ACLK_RGA>,
 666                                          <&cru ACLK_VOP>,
 667                                          <&cru ACLK_VOP_IEP>,
 668                                          <&cru DCLK_VOP>,
 669                                          <&cru HCLK_IEP>,
 670                                          <&cru HCLK_ISP>,
 671                                          <&cru HCLK_RGA>,
 672                                          <&cru HCLK_VIP>,
 673                                          <&cru HCLK_VOP>,
 674                                          <&cru HCLK_VIO_HDCPMMU>,
 675                                          <&cru PCLK_EDP_CTRL>,
 676                                          <&cru PCLK_HDMI_CTRL>,
 677                                          <&cru PCLK_HDCP>,
 678                                          <&cru PCLK_ISP>,
 679                                          <&cru PCLK_VIP>,
 680                                          <&cru PCLK_DPHYRX>,
 681                                          <&cru PCLK_DPHYTX0>,
 682                                          <&cru PCLK_MIPI_CSI>,
 683                                          <&cru PCLK_MIPI_DSI0>,
 684                                          <&cru SCLK_VOP0_PWM>,
 685                                          <&cru SCLK_EDP_24M>,
 686                                          <&cru SCLK_EDP>,
 687                                          <&cru SCLK_HDCP>,
 688                                          <&cru SCLK_ISP>,
 689                                          <&cru SCLK_RGA>,
 690                                          <&cru SCLK_HDMI_CEC>,
 691                                          <&cru SCLK_HDMI_HDCP>;
 692                         };
 693                         /*
 694                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 695                          * (video endecoder & decoder) clocks that on the
 696                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 697                          */
 698                         pd_video {
 699                                 reg = <RK3368_PD_VIDEO>;
 700                                 clocks = <&cru ACLK_VIDEO>,
 701                                          <&cru HCLK_VIDEO>,
 702                                          <&cru SCLK_HEVC_CABAC>,
 703                                          <&cru SCLK_HEVC_CORE>;
 704                         };
 705                         /*
 706                          * Note: ACLK_GPU is the GPU clock,
 707                          * and on the ACLK_GPU_NIU (NOC).
 708                          */
 709                         pd_gpu_1 {
 710                                 reg = <RK3368_PD_GPU_1>;
 711                                 clocks = <&cru ACLK_GPU_CFG>,
 712                                          <&cru ACLK_GPU_MEM>,
 713                                          <&cru SCLK_GPU_CORE>;
 714                         };
 715                 };
 716         };
 717
 718         pmugrf: syscon@ff738000 {
 719                 compatible = "rockchip,rk3368-pmugrf", "syscon";
 720                 reg = <0x0 0xff738000 0x0 0x1000>;
 721         };
 722
 723         cru: clock-controller@ff760000 {
 724                 compatible = "rockchip,rk3368-cru";
 725                 reg = <0x0 0xff760000 0x0 0x1000>;
 726                 rockchip,grf = <&grf>;
 727                 #clock-cells = <1>;
 728                 #reset-cells = <1>;
 729         };
 730
 731         grf: syscon@ff770000 {
 732                 compatible = "rockchip,rk3368-grf", "syscon";
 733                 reg = <0x0 0xff770000 0x0 0x1000>;
 734         };
 735
 736         wdt: watchdog@ff800000 {
 737                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 738                 reg = <0x0 0xff800000 0x0 0x100>;
 739                 clocks = <&cru PCLK_WDT>;
 740                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 741                 status = "disabled";
 742         };
 743
 744         gic: interrupt-controller@ffb71000 {
 745                 compatible = "arm,gic-400";
 746                 interrupt-controller;
 747                 #interrupt-cells = <3>;
 748                 #address-cells = <0>;
 749
 750                 reg = <0x0 0xffb71000 0x0 0x1000>,
 751                       <0x0 0xffb72000 0x0 0x1000>,
 752                       <0x0 0xffb74000 0x0 0x2000>,
 753                       <0x0 0xffb76000 0x0 0x2000>;
 754                 interrupts = <GIC_PPI 9
 755                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 756         };
 757
 758         gpu: rogue-g6110@ffa30000 {
 759                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 760                 reg = <0x0 0xffa30000 0x0 0x10000>;
 761                 clocks =
 762                         <&cru SCLK_GPU_CORE>,
 763                         <&cru ACLK_GPU_MEM>,
 764                         <&cru ACLK_GPU_CFG>;
 765                 clock-names =
 766                         "clk_gpu",
 767                         "aclk_gpu_mem",
 768                         "aclk_gpu_cfg";
 769                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 770                 interrupt-names = "rogue-g6110-irq";
 771         };
 772
 773         i2s_2ch: i2s-2ch@ff890000 {
 774                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 775                 reg = <0x0 0xff898000 0x0 0x1000>;
 776                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 777                 #address-cells = <2>;
 778                 #size-cells = <0>;
 779                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 780                 dma-names = "tx", "rx";
 781                 clock-names = "i2s_hclk", "i2s_clk";
 782                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 783                 status = "disabled";
 784         };
 785
 786         i2s_8ch: i2s-8ch@ff898000 {
 787                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 788                 reg = <0x0 0xff898000 0x0 0x1000>;
 789                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 790                 #address-cells = <1>;
 791                 #size-cells = <0>;
 792                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 793                 dma-names = "tx", "rx";
 794                 clock-names = "i2s_hclk", "i2s_clk";
 795                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 796                 pinctrl-names = "default";
 797                 pinctrl-0 = <&i2s_8ch_bus>;
 798                 status = "disabled";
 799         };
 800
 801         pinctrl: pinctrl {
 802                 compatible = "rockchip,rk3368-pinctrl";
 803                 rockchip,grf = <&grf>;
 804                 rockchip,pmu = <&pmugrf>;
 805                 #address-cells = <0x2>;
 806                 #size-cells = <0x2>;
 807                 ranges;
 808
 809                 gpio0: gpio0@ff750000 {
 810                         compatible = "rockchip,gpio-bank";
 811                         reg = <0x0 0xff750000 0x0 0x100>;
 812                         clocks = <&cru PCLK_GPIO0>;
 813                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 814
 815                         gpio-controller;
 816                         #gpio-cells = <0x2>;
 817
 818                         interrupt-controller;
 819                         #interrupt-cells = <0x2>;
 820                 };
 821
 822                 gpio1: gpio1@ff780000 {
 823                         compatible = "rockchip,gpio-bank";
 824                         reg = <0x0 0xff780000 0x0 0x100>;
 825                         clocks = <&cru PCLK_GPIO1>;
 826                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 827
 828                         gpio-controller;
 829                         #gpio-cells = <0x2>;
 830
 831                         interrupt-controller;
 832                         #interrupt-cells = <0x2>;
 833                 };
 834
 835                 gpio2: gpio2@ff790000 {
 836                         compatible = "rockchip,gpio-bank";
 837                         reg = <0x0 0xff790000 0x0 0x100>;
 838                         clocks = <&cru PCLK_GPIO2>;
 839                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 840
 841                         gpio-controller;
 842                         #gpio-cells = <0x2>;
 843
 844                         interrupt-controller;
 845                         #interrupt-cells = <0x2>;
 846                 };
 847
 848                 gpio3: gpio3@ff7a0000 {
 849                         compatible = "rockchip,gpio-bank";
 850                         reg = <0x0 0xff7a0000 0x0 0x100>;
 851                         clocks = <&cru PCLK_GPIO3>;
 852                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 853
 854                         gpio-controller;
 855                         #gpio-cells = <0x2>;
 856
 857                         interrupt-controller;
 858                         #interrupt-cells = <0x2>;
 859                 };
 860
 861                 pcfg_pull_up: pcfg-pull-up {
 862                         bias-pull-up;
 863                 };
 864
 865                 pcfg_pull_down: pcfg-pull-down {
 866                         bias-pull-down;
 867                 };
 868
 869                 pcfg_pull_none: pcfg-pull-none {
 870                         bias-disable;
 871                 };
 872
 873                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 874                         bias-disable;
 875                         drive-strength = <12>;
 876                 };
 877
 878                 emmc {
 879                         emmc_clk: emmc-clk {
 880                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 881                         };
 882
 883                         emmc_cmd: emmc-cmd {
 884                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 885                         };
 886
 887                         emmc_pwr: emmc-pwr {
 888                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 889                         };
 890
 891                         emmc_bus1: emmc-bus1 {
 892                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 893                         };
 894
 895                         emmc_bus4: emmc-bus4 {
 896                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 897                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 898                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 899                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 900                         };
 901
 902                         emmc_bus8: emmc-bus8 {
 903                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 904                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 905                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 906                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
 907                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
 908                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
 909                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
 910                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
 911                         };
 912                 };
 913
 914                 gmac {
 915                         rgmii_pins: rgmii-pins {
 916                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 917                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 918                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 919                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 920                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 921                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
 922                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
 923                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
 924                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 925                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 926                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 927                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
 928                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
 929                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
 930                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
 931                         };
 932
 933                         rmii_pins: rmii-pins {
 934                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 935                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 936                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 937                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 938                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 939                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 940                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 941                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 942                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
 943                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
 944                         };
 945                 };
 946
 947                 i2c0 {
 948                         i2c0_xfer: i2c0-xfer {
 949                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 950                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 951                         };
 952                 };
 953
 954                 i2c1 {
 955                         i2c1_xfer: i2c1-xfer {
 956                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
 957                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
 958                         };
 959                 };
 960
 961                 i2c2 {
 962                         i2c2_xfer: i2c2-xfer {
 963                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
 964                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
 965                         };
 966                 };
 967
 968                 i2c3 {
 969                         i2c3_xfer: i2c3-xfer {
 970                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
 971                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
 972                         };
 973                 };
 974
 975                 i2c4 {
 976                         i2c4_xfer: i2c4-xfer {
 977                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
 978                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
 979                         };
 980                 };
 981
 982                 i2c5 {
 983                         i2c5_xfer: i2c5-xfer {
 984                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
 985                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
 986                         };
 987                 };
 988
 989                 i2s {
 990                         i2s_8ch_bus: i2s-8ch-bus {
 991                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
 992                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
 993                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
 994                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
 995                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 996                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 997                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
 998                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
 999                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1000                         };
1001                 };
1002
1003                 sdio0 {
1004                         sdio0_bus1: sdio0-bus1 {
1005                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1006                         };
1007
1008                         sdio0_bus4: sdio0-bus4 {
1009                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1010                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1011                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1012                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1013                         };
1014
1015                         sdio0_cmd: sdio0-cmd {
1016                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1017                         };
1018
1019                         sdio0_clk: sdio0-clk {
1020                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1021                         };
1022
1023                         sdio0_cd: sdio0-cd {
1024                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1025                         };
1026
1027                         sdio0_wp: sdio0-wp {
1028                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1029                         };
1030
1031                         sdio0_pwr: sdio0-pwr {
1032                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1033                         };
1034
1035                         sdio0_bkpwr: sdio0-bkpwr {
1036                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1037                         };
1038
1039                         sdio0_int: sdio0-int {
1040                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1041                         };
1042                 };
1043
1044                 sdmmc {
1045                         sdmmc_clk: sdmmc-clk {
1046                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1047                         };
1048
1049                         sdmmc_cmd: sdmmc-cmd {
1050                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1051                         };
1052
1053                         sdmmc_cd: sdmcc-cd {
1054                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1055                         };
1056
1057                         sdmmc_bus1: sdmmc-bus1 {
1058                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1059                         };
1060
1061                         sdmmc_bus4: sdmmc-bus4 {
1062                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1063                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1064                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1065                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1066                         };
1067                 };
1068
1069                 spi0 {
1070                         spi0_clk: spi0-clk {
1071                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1072                         };
1073                         spi0_cs0: spi0-cs0 {
1074                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1075                         };
1076                         spi0_cs1: spi0-cs1 {
1077                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1078                         };
1079                         spi0_tx: spi0-tx {
1080                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1081                         };
1082                         spi0_rx: spi0-rx {
1083                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1084                         };
1085                 };
1086
1087                 spi1 {
1088                         spi1_clk: spi1-clk {
1089                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1090                         };
1091                         spi1_cs0: spi1-cs0 {
1092                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1093                         };
1094                         spi1_cs1: spi1-cs1 {
1095                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1096                         };
1097                         spi1_rx: spi1-rx {
1098                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1099                         };
1100                         spi1_tx: spi1-tx {
1101                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1102                         };
1103                 };
1104
1105                 spi2 {
1106                         spi2_clk: spi2-clk {
1107                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1108                         };
1109                         spi2_cs0: spi2-cs0 {
1110                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1111                         };
1112                         spi2_rx: spi2-rx {
1113                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1114                         };
1115                         spi2_tx: spi2-tx {
1116                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1117                         };
1118                 };
1119
1120                 uart0 {
1121                         uart0_xfer: uart0-xfer {
1122                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1123                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1124                         };
1125
1126                         uart0_cts: uart0-cts {
1127                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129
1130                         uart0_rts: uart0-rts {
1131                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1132                         };
1133                 };
1134
1135                 uart1 {
1136                         uart1_xfer: uart1-xfer {
1137                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1138                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1139                         };
1140
1141                         uart1_cts: uart1-cts {
1142                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1143                         };
1144
1145                         uart1_rts: uart1-rts {
1146                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1147                         };
1148                 };
1149
1150                 uart2 {
1151                         uart2_xfer: uart2-xfer {
1152                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1153                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1154                         };
1155                         /* no rts / cts for uart2 */
1156                 };
1157
1158                 uart3 {
1159                         uart3_xfer: uart3-xfer {
1160                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1161                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1162                         };
1163
1164                         uart3_cts: uart3-cts {
1165                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1166                         };
1167
1168                         uart3_rts: uart3-rts {
1169                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 uart4 {
1174                         uart4_xfer: uart4-xfer {
1175                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1176                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1177                         };
1178
1179                         uart4_cts: uart4-cts {
1180                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1181                         };
1182
1183                         uart4_rts: uart4-rts {
1184                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1185                         };
1186                 };
1187
1188                 pwm0 {
1189                         pwm0_pin: pwm0-pin {
1190                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1191                         };
1192
1193                         vop_pwm_pin: vop-pwm {
1194                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1195                         };
1196                 };
1197
1198                 pwm1 {
1199                         pwm1_pin: pwm1-pin {
1200                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1201                         };
1202                 };
1203
1204                 pwm3 {
1205                         pwm3_pin: pwm3-pin {
1206                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1207                         };
1208                 };
1209
1210                 lcdc {
1211                         lcdc_lcdc: lcdc-lcdc {
1212                                 rockchip,pins =
1213                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1214                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1215                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1216                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1217                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1218                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1219                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1220                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1221                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1222                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1223                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1224                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1225                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1226                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1227                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1228                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1229                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1230                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1231                         };
1232
1233                         lcdc_gpio: lcdc-gpio {
1234                                 rockchip,pins =
1235                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1236                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1237                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1238                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1239                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1240                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1241                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1242                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1243                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1244                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1245                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1246                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1247                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1248                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1249                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1250                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1251                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1252                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1253                         };
1254                 };
1255         };
1256
1257         fb: fb {
1258                 compatible = "rockchip,rk-fb";
1259                 rockchip,disp-mode = <NO_DUAL>;
1260                 status = "disabled";
1261         };
1262
1263         rk_screen: screen {
1264                 compatible = "rockchip,screen";
1265                 status = "disabled";
1266         };
1267
1268         lcdc: lcdc@ff930000 {
1269                 compatible = "rockchip,rk3368-lcdc";
1270                 rockchip,grf = <&grf>;
1271                 rockchip,pmugrf = <&pmugrf>;
1272                 rockchip,cru = <&cru>;
1273                 rockchip,prop = <PRMRY>;
1274                 rockchip,pwr18 = <0>;
1275                 rockchip,iommu-enabled = <1>;
1276                 reg = <0x0 0xff930000 0x0 0x10000>;
1277                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1278                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1279                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1280                 /*power-domains = <&power PD_VIO>;*/
1281                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1282                 reset-names = "axi", "ahb", "dclk";
1283                 status = "disabled";
1284         };
1285
1286         mipi: mipi@ff960000 {
1287                 compatible = "rockchip,rk3368-dsi";
1288                 rockchip,prop = <0>;
1289                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1290                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1291                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1292                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1293                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1294                 /*power-domains = <&power PD_VIO>;*/
1295                 status = "disabled";
1296         };
1297
1298         lvds: lvds@ff968000 {
1299                 compatible = "rockchip,rk3368-lvds";
1300                 rockchip,grf = <&grf>;
1301                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1302                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1303                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1304                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1305                 /*power-domains = <&power PD_VIO>;*/
1306                 status = "disabled";
1307         };
1308
1309         edp: edp@ff970000 {
1310                 compatible = "rockchip,rk32-edp";
1311                 reg = <0x0 0xff970000 0x0 0x4000>;
1312                 rockchip,grf = <&grf>;
1313                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1314                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1315                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1316                 /*power-domains = <&power PD_VIO>;*/
1317                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1318                 reset-names = "edp_24m", "edp_apb";
1319                 status = "disabled";
1320         };
1321
1322         iep_mmu: iep-mmu {
1323                 dbgname = "iep";
1324                 compatible = "rockchip,iep_mmu";
1325                 reg = <0x0 0xff900800 0x0 0x100>;
1326                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1327                 interrupt-names = "iep_mmu";
1328                 status = "disabled";
1329         };
1330
1331         vip_mmu: vip-mmu {
1332                 dbgname = "vip";
1333                 compatible = "rockchip,vip_mmu";
1334                 reg = <0x0 0xff950800 0x0 0x100>;
1335                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1336                 interrupt-names = "vip_mmu";
1337                 status = "disabled";
1338         };
1339
1340         vopb_mmu: vopb-mmu {
1341                 dbgname = "vop";
1342                 compatible = "rockchip,vopb_mmu";
1343                 reg = <0x0 0xff930300 0x0 0x100>;
1344                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1345                 interrupt-names = "vop_mmu";
1346                 status = "disabled";
1347         };
1348
1349         isp_mmu: isp-mmu {
1350                 dbgname = "isp_mmu";
1351                 compatible = "rockchip,isp_mmu";
1352                 reg = <0x0 0xff914000 0x0 0x100>,
1353                       <0x0 0xff915000 0x0 0x100>;
1354                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1355                 interrupt-names = "isp_mmu";
1356                 status = "disabled";
1357         };
1358
1359         hdcp_mmu: hdcp-mmu {
1360                  dbgname = "hdcp_mmu";
1361                  compatible = "rockchip,hdcp_mmu";
1362                  reg = <0x0 0xff940000 0x0 0x100>;
1363                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1364                  interrupt-names = "hdcp_mmu";
1365                 status = "disabled";
1366         };
1367
1368         hevc_mmu: hevc-mmu {
1369                 dbgname = "hevc";
1370                 compatible = "rockchip,hevc_mmu";
1371                 reg = <0x0 0xff9a0440 0x0 0x40>,
1372                       <0x0 0xff9a0480 0x0 0x40>;
1373                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1374                 interrupt-names = "hevc_mmu";
1375                 status = "disabled";
1376         };
1377
1378         vpu_mmu: vpu-mmu {
1379                 dbgname = "vpu";
1380                 compatible = "rockchip,vpu_mmu";
1381                 reg = <0x0 0xff9a0800 0x0 0x100>;
1382                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1383                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1384                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1385                 status = "disabled";
1386         };
1387 };