clk: rockchip: rk3328: add pclk for acodec
authorSugar Zhang <sugar.zhang@rock-chips.com>
Fri, 7 Apr 2017 03:33:50 +0000 (11:33 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Mon, 10 Apr 2017 06:27:59 +0000 (14:27 +0800)
Change-Id: Ia07f22997875e874037cb06fea6a3f25e6ab46dc
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
drivers/clk/rockchip/clk-rk3328.c

index 8ee7730..5b17087 100644 (file)
@@ -795,6 +795,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
        GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
        GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
        GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
+       GATE(PCLK_ACODEC, "pclk_acodec", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
        GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
        GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
        GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),