clk: rockchip: rk3399: add some aclk/dclk IDs for vop0/vop1

Change-Id: If59b057892ad8bfe250ac763905150518cdc8631
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 42c63c395aa40ef858800571f2257790a23046da..bd84ef15097fa8dd82d0c25e05be241c45fdf1d3 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1101,7 +1101,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(11), 7, GFLAGS),
 
        /* vop0 */
                        RK3399_CLKGATE_CON(11), 7, GFLAGS),
 
        /* vop0 */

-       COMPOSITE(0, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,

                        RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 8, GFLAGS),
        COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
                        RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 8, GFLAGS),
        COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,


@@ -1118,7 +1118,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(28), 0, GFLAGS),
 
        GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(28), 0, GFLAGS),
 

-       COMPOSITE(0, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,

                        RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 12, GFLAGS),
 
                        RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 12, GFLAGS),
 


@@ -1131,7 +1131,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(10), 14, GFLAGS),
 
        /* vop1 */
                        RK3399_CLKGATE_CON(10), 14, GFLAGS),
 
        /* vop1 */

-       COMPOSITE(0, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,

                        RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 10, GFLAGS),
        COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
                        RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 10, GFLAGS),
        COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,


@@ -1148,7 +1148,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(28), 4, GFLAGS),
 
        GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(28), 4, GFLAGS),
 

-       COMPOSITE(0, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,

                        RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 13, GFLAGS),
 
                        RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 13, GFLAGS),
 

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 51122c0146c177ce37533b512af8a0e2e2164f98..244746e7dc4cf3347a01bfac5679f5fb59280211 100644 (file)
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -132,7 +132,9 @@
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181

-#define DCLK_M0_PERILP                 182
+#define DCLK_VOP0_DIV                  182
+#define DCLK_VOP1_DIV                  183
+#define DCLK_M0_PERILP                 184

 
 #define FCLK_CM0S                      190
 
 
 #define FCLK_CM0S                      190
 


@@ -208,6 +210,8 @@
 #define ACLK_PERF_CORE_L               260
 #define ACLK_PERF_CORE_B               261
 #define ACLK_GIC_PRE                   262
 #define ACLK_PERF_CORE_L               260
 #define ACLK_PERF_CORE_B               261
 #define ACLK_GIC_PRE                   262

+#define ACLK_VOP0_PRE                  263
+#define ACLK_VOP1_PRE                  264

 
 /* pclk gates */
 #define PCLK_PERIHP                    320
 
 /* pclk gates */
 #define PCLK_PERIHP                    320