2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk-provider.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
24 #define RK3399_PMUGRF_SOC_CON0 0x180
25 #define RK3399_PMUCRU_PCLK_GATE_MASK 0x1
26 #define RK3399_PMUCRU_PCLK_GATE_SHIFT 4
27 #define RK3399_PMUCRU_PCLK_ALIVE_MASK 0x1
28 #define RK3399_PMUCRU_PCLK_ALIVE_SHIFT 6
31 lpll, bpll, dpll, cpll, gpll, npll, vpll,
34 enum rk3399_pmu_plls {
38 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
39 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
40 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
43 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
44 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
45 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
46 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
47 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
48 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
80 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
81 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
82 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
83 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
84 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
85 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
86 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
95 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
96 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
97 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
99 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
100 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
101 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
102 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
103 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
104 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
105 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
106 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
107 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
112 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
114 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
115 "clk_core_l_bpll_src",
116 "clk_core_l_dpll_src",
117 "clk_core_l_gpll_src" };
118 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
119 "clk_core_b_bpll_src",
120 "clk_core_b_dpll_src",
121 "clk_core_b_gpll_src" };
122 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
125 "vpll_aclk_cci_src" };
126 PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" };
127 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", "npll_cs"};
128 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
130 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
131 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
132 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
133 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
134 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", "ppll" };
136 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", "xin24m" };
137 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", "clk_usbphy_480m" };
138 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
139 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", "upll", "xin24m" };
140 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
142 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
143 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", "npll" };
144 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", "xin24m" };
146 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", "dclk_vop0_frac" };
147 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", "dclk_vop1_frac" };
149 PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" };
151 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
152 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
153 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", "cpll", "gpll" };
154 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", "clk_pcie_core_phy" };
156 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" };
158 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" };
160 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", "gpll_fclk_cm0s_src" };
162 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" };
164 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
165 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
167 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", "clk_usbphy1_480m_src" };
168 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" };
169 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
170 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
171 "clkin_i2s", "xin12m" };
172 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
173 "clkin_i2s", "xin12m" };
174 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
175 "clkin_i2s", "xin12m" };
176 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
177 "clkin_i2s", "xin12m" };
178 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", "clk_i2s2" };
179 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
181 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
182 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
183 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
184 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
186 /* PMU CRU parents */
187 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
188 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
189 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
190 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
191 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", "xin24m" };
192 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
194 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
195 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
196 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
197 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
198 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
199 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
200 RK3399_PLL_CON(19), 8, 31, 0, NULL),
201 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
202 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
203 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
204 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
205 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
206 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
207 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
208 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
211 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
212 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
213 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
216 #define MFLAGS CLK_MUX_HIWORD_MASK
217 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
218 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
219 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
221 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
222 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
223 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
225 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
226 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
227 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
229 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
230 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
231 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
233 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
234 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
235 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
237 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
238 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
239 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
241 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
242 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
243 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
245 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
246 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
247 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
249 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
250 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
251 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
253 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
254 .core_reg = RK3399_CLKSEL_CON(0),
256 .div_core_mask = 0x1f,
260 .mux_core_mask = 0x3,
263 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
264 .core_reg = RK3399_CLKSEL_CON(2),
266 .div_core_mask = 0x1f,
270 .mux_core_mask = 0x3,
273 #define RK3399_DIV_ACLKM_MASK 0x1f
274 #define RK3399_DIV_ACLKM_SHIFT 8
275 #define RK3399_DIV_ATCLK_MASK 0x1f
276 #define RK3399_DIV_ATCLK_SHIFT 0
277 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
278 #define RK3399_DIV_PCLK_DBG_SHIFT 8
280 #define RK3399_CLKSEL0(_offs, _aclkm) \
282 .reg = RK3399_CLKSEL_CON(0 + _offs), \
283 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
284 RK3399_DIV_ACLKM_SHIFT), \
286 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
288 .reg = RK3399_CLKSEL_CON(1 + _offs), \
289 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
290 RK3399_DIV_ATCLK_SHIFT) | \
291 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
292 RK3399_DIV_PCLK_DBG_SHIFT), \
295 /* cluster_l: aclkm in clksel0, rest in clksel1 */
296 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
298 .prate = _prate##U, \
300 RK3399_CLKSEL0(0, _aclkm), \
301 RK3399_CLKSEL1(0, _atclk, _pdbg), \
305 /* cluster_b: aclkm in clksel2, rest in clksel3 */
306 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
308 .prate = _prate##U, \
310 RK3399_CLKSEL0(2, _aclkm), \
311 RK3399_CLKSEL1(2, _atclk, _pdbg), \
315 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
316 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
317 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
318 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
319 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
320 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
321 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
322 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
323 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
324 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
325 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
326 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
327 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
328 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
331 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
332 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
333 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
334 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
335 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
336 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
337 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
338 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
339 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
340 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
341 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
342 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
343 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
344 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
345 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
346 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
347 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
348 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
349 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
350 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
353 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
355 * CRU Clock-Architecture
359 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
360 RK3399_CLKGATE_CON(6), 5, GFLAGS),
361 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
362 RK3399_CLKGATE_CON(6), 6, GFLAGS),
364 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
365 RK3399_CLKGATE_CON(13), 12, GFLAGS),
366 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
367 RK3399_CLKGATE_CON(13), 12, GFLAGS),
368 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
369 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
371 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
372 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
374 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, CLK_IGNORE_UNUSED,
375 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
376 RK3399_CLKGATE_CON(6), 4, GFLAGS),
378 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
379 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
380 RK3399_CLKGATE_CON(12), 0, GFLAGS),
381 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
382 RK3399_CLKGATE_CON(30), 0, GFLAGS),
383 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLK_IGNORE_UNUSED,
384 RK3399_CLKGATE_CON(30), 1, GFLAGS),
385 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLK_IGNORE_UNUSED,
386 RK3399_CLKGATE_CON(30), 2, GFLAGS),
387 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLK_IGNORE_UNUSED,
388 RK3399_CLKGATE_CON(30), 3, GFLAGS),
389 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLK_IGNORE_UNUSED,
390 RK3399_CLKGATE_CON(30), 4, GFLAGS),
392 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLK_IGNORE_UNUSED,
393 RK3399_CLKGATE_CON(12), 1, GFLAGS),
394 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLK_IGNORE_UNUSED,
395 RK3399_CLKGATE_CON(12), 2, GFLAGS),
397 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
398 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
399 RK3399_CLKGATE_CON(12), 3, GFLAGS),
401 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
402 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
403 RK3399_CLKGATE_CON(12), 4, GFLAGS),
405 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
406 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
407 RK3399_CLKGATE_CON(13), 4, GFLAGS),
409 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
410 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
411 RK3399_CLKGATE_CON(13), 5, GFLAGS),
413 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
414 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
415 RK3399_CLKGATE_CON(13), 6, GFLAGS),
417 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
418 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
419 RK3399_CLKGATE_CON(13), 7, GFLAGS),
422 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
423 RK3399_CLKGATE_CON(0), 0, GFLAGS),
424 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
425 RK3399_CLKGATE_CON(0), 1, GFLAGS),
426 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
427 RK3399_CLKGATE_CON(0), 2, GFLAGS),
428 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
429 RK3399_CLKGATE_CON(0), 3, GFLAGS),
431 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
432 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
433 RK3399_CLKGATE_CON(0), 4, GFLAGS),
434 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
435 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
436 RK3399_CLKGATE_CON(0), 5, GFLAGS),
437 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
438 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
439 RK3399_CLKGATE_CON(0), 6, GFLAGS),
441 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
442 RK3399_CLKGATE_CON(14), 12, GFLAGS),
443 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
444 RK3399_CLKGATE_CON(14), 13, GFLAGS),
446 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
447 RK3399_CLKGATE_CON(14), 9, GFLAGS),
448 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
449 RK3399_CLKGATE_CON(14), 10, GFLAGS),
450 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
451 RK3399_CLKGATE_CON(14), 11, GFLAGS),
452 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
453 RK3399_CLKGATE_CON(0), 7, GFLAGS),
456 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
457 RK3399_CLKGATE_CON(1), 0, GFLAGS),
458 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
459 RK3399_CLKGATE_CON(1), 1, GFLAGS),
460 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
461 RK3399_CLKGATE_CON(1), 2, GFLAGS),
462 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
463 RK3399_CLKGATE_CON(1), 3, GFLAGS),
465 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
466 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
467 RK3399_CLKGATE_CON(1), 4, GFLAGS),
468 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
469 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
470 RK3399_CLKGATE_CON(1), 5, GFLAGS),
471 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
472 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
473 RK3399_CLKGATE_CON(1), 6, GFLAGS),
475 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
476 RK3399_CLKGATE_CON(14), 5, GFLAGS),
477 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
478 RK3399_CLKGATE_CON(14), 6, GFLAGS),
480 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
481 RK3399_CLKGATE_CON(14), 1, GFLAGS),
482 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
483 RK3399_CLKGATE_CON(14), 3, GFLAGS),
484 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
485 RK3399_CLKGATE_CON(14), 4, GFLAGS),
487 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
488 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
490 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
491 RK3399_CLKGATE_CON(14), 2, GFLAGS),
493 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
494 RK3399_CLKGATE_CON(1), 7, GFLAGS),
497 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
498 RK3399_CLKGATE_CON(6), 9, GFLAGS),
499 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
500 RK3399_CLKGATE_CON(6), 8, GFLAGS),
501 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, CLK_IGNORE_UNUSED,
502 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
503 RK3399_CLKGATE_CON(6), 10, GFLAGS),
505 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
506 RK3399_CLKGATE_CON(32), 0, GFLAGS),
507 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
508 RK3399_CLKGATE_CON(32), 1, GFLAGS),
509 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
510 RK3399_CLKGATE_CON(32), 4, GFLAGS),
512 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
513 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
514 RK3399_CLKGATE_CON(6), 11, GFLAGS),
515 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
516 RK3399_CLKGATE_CON(32), 2, GFLAGS),
517 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
518 RK3399_CLKGATE_CON(32), 3, GFLAGS),
520 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
521 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
522 RK3399_CLKGATE_CON(5), 5, GFLAGS),
524 MUX(0, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
525 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
526 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLK_IGNORE_UNUSED,
527 RK3399_CLKGATE_CON(5), 6, GFLAGS),
528 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLK_IGNORE_UNUSED,
529 RK3399_CLKGATE_CON(5), 7, GFLAGS),
530 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLK_IGNORE_UNUSED,
531 RK3399_CLKGATE_CON(5), 8, GFLAGS),
532 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLK_IGNORE_UNUSED,
533 RK3399_CLKGATE_CON(5), 9, GFLAGS),
536 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
537 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
538 RK3399_CLKGATE_CON(8), 13, GFLAGS),
539 COMPOSITE_FRAC(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
540 RK3399_CLKSEL_CON(99), 0,
541 RK3399_CLKGATE_CON(8), 14, GFLAGS),
542 COMPOSITE_NODIV(SCLK_SPDIF_8CH, "clk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
543 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS,
544 RK3399_CLKGATE_CON(8), 15, GFLAGS),
546 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
547 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
548 RK3399_CLKGATE_CON(10), 6, GFLAGS),
550 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
551 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
552 RK3399_CLKGATE_CON(8), 3, GFLAGS),
553 COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
554 RK3399_CLKSEL_CON(96), 0,
555 RK3399_CLKGATE_CON(8), 4, GFLAGS),
556 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
557 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS),
558 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_IGNORE_UNUSED,
559 RK3399_CLKGATE_CON(8), 5, GFLAGS),
561 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
562 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
563 RK3399_CLKGATE_CON(8), 6, GFLAGS),
564 COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
565 RK3399_CLKSEL_CON(97), 0,
566 RK3399_CLKGATE_CON(8), 7, GFLAGS),
567 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
568 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS),
569 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_IGNORE_UNUSED,
570 RK3399_CLKGATE_CON(8), 8, GFLAGS),
572 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
573 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
574 RK3399_CLKGATE_CON(8), 9, GFLAGS),
575 COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
576 RK3399_CLKSEL_CON(98), 0,
577 RK3399_CLKGATE_CON(8), 10, GFLAGS),
578 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
579 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS),
580 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_IGNORE_UNUSED,
581 RK3399_CLKGATE_CON(8), 11, GFLAGS),
583 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
584 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
585 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, 0,
586 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
587 RK3399_CLKGATE_CON(8), 12, GFLAGS),
590 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
591 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
592 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
593 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
594 RK3399_CLKGATE_CON(9), 0, GFLAGS),
595 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
596 RK3399_CLKSEL_CON(100), 0,
597 RK3399_CLKGATE_CON(9), 1, GFLAGS,
598 &rk3399_uart0_fracmux),
600 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
601 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
602 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
603 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
604 RK3399_CLKGATE_CON(9), 2, GFLAGS),
605 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
606 RK3399_CLKSEL_CON(101), 0,
607 RK3399_CLKGATE_CON(9), 3, GFLAGS,
608 &rk3399_uart1_fracmux),
610 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
611 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
612 RK3399_CLKGATE_CON(9), 4, GFLAGS),
613 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
614 RK3399_CLKSEL_CON(102), 0,
615 RK3399_CLKGATE_CON(9), 5, GFLAGS,
616 &rk3399_uart2_fracmux),
618 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
619 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
620 RK3399_CLKGATE_CON(9), 6, GFLAGS),
621 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
622 RK3399_CLKSEL_CON(103), 0,
623 RK3399_CLKGATE_CON(9), 7, GFLAGS,
624 &rk3399_uart3_fracmux),
626 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
627 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
628 RK3399_CLKGATE_CON(3), 4, GFLAGS),
630 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
631 RK3399_CLKGATE_CON(18), 10, GFLAGS),
632 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
633 RK3399_CLKGATE_CON(18), 12, GFLAGS),
634 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
635 RK3399_CLKGATE_CON(18), 15, GFLAGS),
636 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
637 RK3399_CLKGATE_CON(19), 2, GFLAGS),
639 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
640 RK3399_CLKGATE_CON(4), 11, GFLAGS),
641 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
642 RK3399_CLKGATE_CON(3), 5, GFLAGS),
643 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
644 RK3399_CLKGATE_CON(3), 6, GFLAGS),
647 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
648 RK3399_CLKGATE_CON(2), 0, GFLAGS),
649 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
650 RK3399_CLKGATE_CON(2), 1, GFLAGS),
651 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
652 RK3399_CLKGATE_CON(2), 2, GFLAGS),
653 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
654 RK3399_CLKGATE_CON(2), 3, GFLAGS),
656 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
657 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
658 RK3399_CLKGATE_CON(2), 4, GFLAGS),
660 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
661 RK3399_CLKGATE_CON(15), 0, GFLAGS),
662 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
663 RK3399_CLKGATE_CON(15), 1, GFLAGS),
664 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
665 RK3399_CLKGATE_CON(15), 2, GFLAGS),
666 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
667 RK3399_CLKGATE_CON(15), 3, GFLAGS),
668 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
669 RK3399_CLKGATE_CON(15), 4, GFLAGS),
670 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
671 RK3399_CLKGATE_CON(15), 7, GFLAGS),
673 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
674 RK3399_CLKGATE_CON(2), 5, GFLAGS),
675 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
676 RK3399_CLKGATE_CON(2), 6, GFLAGS),
677 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
678 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
679 RK3399_CLKGATE_CON(2), 7, GFLAGS),
681 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
682 RK3399_CLKGATE_CON(2), 8, GFLAGS),
683 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
684 RK3399_CLKGATE_CON(2), 9, GFLAGS),
685 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
686 RK3399_CLKGATE_CON(2), 10, GFLAGS),
687 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
688 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
689 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
690 RK3399_CLKGATE_CON(15), 5, GFLAGS),
691 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
692 RK3399_CLKGATE_CON(15), 6, GFLAGS),
695 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
696 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
697 RK3399_CLKGATE_CON(4), 0, GFLAGS),
698 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
699 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
700 RK3399_CLKGATE_CON(4), 1, GFLAGS),
701 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
702 RK3399_CLKGATE_CON(17), 2, GFLAGS),
703 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
704 RK3399_CLKGATE_CON(17), 3, GFLAGS),
706 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
707 RK3399_CLKGATE_CON(17), 0, GFLAGS),
708 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
709 RK3399_CLKGATE_CON(17), 1, GFLAGS),
712 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
713 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
714 RK3399_CLKGATE_CON(4), 4, GFLAGS),
715 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
716 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
717 RK3399_CLKGATE_CON(4), 5, GFLAGS),
719 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
720 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
721 RK3399_CLKGATE_CON(4), 2, GFLAGS),
722 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
723 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
724 RK3399_CLKGATE_CON(4), 3, GFLAGS),
725 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
726 RK3399_CLKGATE_CON(17), 10, GFLAGS),
727 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
728 RK3399_CLKGATE_CON(17), 11, GFLAGS),
730 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
731 RK3399_CLKGATE_CON(17), 8, GFLAGS),
732 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
733 RK3399_CLKGATE_CON(17), 9, GFLAGS),
736 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
737 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
738 RK3399_CLKGATE_CON(4), 6, GFLAGS),
739 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
740 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
741 RK3399_CLKGATE_CON(4), 7, GFLAGS),
742 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", CLK_IGNORE_UNUSED,
743 RK3399_CLKGATE_CON(16), 2, GFLAGS),
744 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
745 RK3399_CLKGATE_CON(16), 3, GFLAGS),
747 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", CLK_IGNORE_UNUSED,
748 RK3399_CLKGATE_CON(16), 0, GFLAGS),
749 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
750 RK3399_CLKGATE_CON(16), 1, GFLAGS),
753 COMPOSITE(0, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
754 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
755 RK3399_CLKGATE_CON(4), 10, GFLAGS),
757 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
758 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
759 RK3399_CLKGATE_CON(4), 8, GFLAGS),
760 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
761 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
762 RK3399_CLKGATE_CON(4), 9, GFLAGS),
763 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", CLK_IGNORE_UNUSED,
764 RK3399_CLKGATE_CON(16), 10, GFLAGS),
765 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
766 RK3399_CLKGATE_CON(16), 11, GFLAGS),
768 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", CLK_IGNORE_UNUSED,
769 RK3399_CLKGATE_CON(16), 8, GFLAGS),
770 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
771 RK3399_CLKGATE_CON(16), 9, GFLAGS),
774 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
775 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
776 RK3399_CLKGATE_CON(3), 7, GFLAGS),
777 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
778 RK3399_CLKGATE_CON(19), 0, GFLAGS),
779 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
780 RK3399_CLKGATE_CON(19), 1, GFLAGS),
783 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
784 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
785 RK3399_CLKGATE_CON(13), 0, GFLAGS),
786 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
787 RK3399_CLKGATE_CON(30), 8, GFLAGS),
788 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
789 RK3399_CLKGATE_CON(30), 10, GFLAGS),
790 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
791 RK3399_CLKGATE_CON(30), 11, GFLAGS),
792 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", CLK_IGNORE_UNUSED,
793 RK3399_CLKGATE_CON(13), 1, GFLAGS),
796 GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
797 RK3399_CLKGATE_CON(5), 0, GFLAGS),
798 GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
799 RK3399_CLKGATE_CON(5), 1, GFLAGS),
800 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
801 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
802 RK3399_CLKGATE_CON(5), 2, GFLAGS),
803 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
804 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
805 RK3399_CLKGATE_CON(5), 3, GFLAGS),
806 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
807 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
808 RK3399_CLKGATE_CON(5), 4, GFLAGS),
810 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
811 RK3399_CLKGATE_CON(20), 2, GFLAGS),
812 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
813 RK3399_CLKGATE_CON(20), 10, GFLAGS),
814 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
815 RK3399_CLKGATE_CON(20), 12, GFLAGS),
817 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", CLK_IGNORE_UNUSED,
818 RK3399_CLKGATE_CON(20), 5, GFLAGS),
819 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
820 RK3399_CLKGATE_CON(20), 6, GFLAGS),
821 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", CLK_IGNORE_UNUSED,
822 RK3399_CLKGATE_CON(20), 7, GFLAGS),
823 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
824 RK3399_CLKGATE_CON(20), 8, GFLAGS),
825 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", CLK_IGNORE_UNUSED,
826 RK3399_CLKGATE_CON(20), 9, GFLAGS),
827 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
828 RK3399_CLKGATE_CON(20), 13, GFLAGS),
829 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
830 RK3399_CLKGATE_CON(20), 15, GFLAGS),
832 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
833 RK3399_CLKGATE_CON(20), 4, GFLAGS),
834 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLK_IGNORE_UNUSED,
835 RK3399_CLKGATE_CON(20), 11, GFLAGS),
836 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
837 RK3399_CLKGATE_CON(20), 14, GFLAGS),
838 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", CLK_IGNORE_UNUSED,
839 RK3399_CLKGATE_CON(31), 8, GFLAGS),
842 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
843 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
844 RK3399_CLKGATE_CON(12), 13, GFLAGS),
845 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLK_IGNORE_UNUSED,
846 RK3399_CLKGATE_CON(33), 8, GFLAGS),
847 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
848 RK3399_CLKGATE_CON(33), 9, GFLAGS),
850 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
851 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
852 RK3399_CLKGATE_CON(6), 0, GFLAGS),
854 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
855 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
856 RK3399_CLKGATE_CON(6), 1, GFLAGS),
858 MMC(SCLK_SDMMC_DRV, "emmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
859 MMC(SCLK_SDMMC_SAMPLE, "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
861 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
862 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
865 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, CLK_IGNORE_UNUSED,
866 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
867 RK3399_CLKGATE_CON(6), 2, GFLAGS),
869 COMPOSITE_NOMUX(0, "clk_pciephy_ref100m", "npll", CLK_IGNORE_UNUSED,
870 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
871 RK3399_CLKGATE_CON(12), 6, GFLAGS),
872 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
873 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
875 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
876 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
877 RK3399_CLKGATE_CON(6), 3, GFLAGS),
878 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
879 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
882 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, CLK_IGNORE_UNUSED,
883 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
884 RK3399_CLKGATE_CON(6), 14, GFLAGS),
886 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
887 RK3399_CLKGATE_CON(6), 12, GFLAGS),
888 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
889 RK3399_CLKGATE_CON(6), 13, GFLAGS),
890 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
891 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
892 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
893 RK3399_CLKGATE_CON(32), 8, GFLAGS),
894 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
895 RK3399_CLKGATE_CON(32), 9, GFLAGS),
896 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
897 RK3399_CLKGATE_CON(32), 10, GFLAGS),
900 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
901 RK3399_CLKGATE_CON(7), 1, GFLAGS),
902 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
903 RK3399_CLKGATE_CON(7), 0, GFLAGS),
904 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
905 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
906 RK3399_CLKGATE_CON(7), 2, GFLAGS),
907 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
908 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
909 RK3399_CLKGATE_CON(7), 3, GFLAGS),
910 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
911 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
912 RK3399_CLKGATE_CON(7), 4, GFLAGS),
914 /* aclk_perilp0 gates */
915 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
916 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
917 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
918 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
919 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
920 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
921 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
922 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
923 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
924 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
925 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
926 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 7, GFLAGS),
928 /* hclk_perilp0 gates */
929 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
930 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 5, GFLAGS),
931 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 6, GFLAGS),
932 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 14, GFLAGS),
933 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 15, GFLAGS),
934 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
936 /* pclk_perilp0 gates */
937 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
940 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
941 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
942 RK3399_CLKGATE_CON(7), 7, GFLAGS),
944 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
945 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
946 RK3399_CLKGATE_CON(7), 8, GFLAGS),
949 GATE(0, "cpll_fclk_cm0s_src", "cpll", CLK_IGNORE_UNUSED,
950 RK3399_CLKGATE_CON(7), 6, GFLAGS),
951 GATE(0, "gpll_fclk_cm0s_src", "gpll", CLK_IGNORE_UNUSED,
952 RK3399_CLKGATE_CON(7), 5, GFLAGS),
953 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, CLK_IGNORE_UNUSED,
954 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
955 RK3399_CLKGATE_CON(7), 9, GFLAGS),
957 /* fclk_cm0s gates */
958 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 8, GFLAGS),
959 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 9, GFLAGS),
960 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 10, GFLAGS),
961 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 11, GFLAGS),
962 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
965 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
966 RK3399_CLKGATE_CON(8), 1, GFLAGS),
967 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
968 RK3399_CLKGATE_CON(8), 0, GFLAGS),
969 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
970 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
971 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
972 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
973 RK3399_CLKGATE_CON(8), 2, GFLAGS),
975 /* hclk_perilp1 gates */
976 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
977 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
978 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 0, GFLAGS),
979 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 1, GFLAGS),
980 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 2, GFLAGS),
981 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 3, GFLAGS),
982 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 4, GFLAGS),
983 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 5, GFLAGS),
984 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
986 /* pclk_perilp1 gates */
987 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
988 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
989 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
990 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
991 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
992 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
993 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
994 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
995 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
996 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
997 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
998 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
999 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1000 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1001 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1002 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1003 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1004 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1005 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1006 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1007 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1010 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1011 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1012 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1015 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, CLK_IGNORE_UNUSED,
1016 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1017 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1020 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1021 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1022 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1023 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1024 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1026 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1027 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1028 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1029 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1030 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1033 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1034 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1035 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1036 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1037 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1038 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1040 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1041 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1043 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", CLK_IGNORE_UNUSED,
1044 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1045 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", CLK_IGNORE_UNUSED,
1046 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1047 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1048 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1051 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1052 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1053 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1054 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1055 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1056 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1057 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1058 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1059 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1061 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1062 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1063 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", CLK_IGNORE_UNUSED,
1064 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1066 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1067 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1068 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", CLK_IGNORE_UNUSED,
1069 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1071 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1072 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1073 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1074 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1075 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1076 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1077 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", CLK_IGNORE_UNUSED,
1078 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1079 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", CLK_IGNORE_UNUSED,
1080 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1083 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1084 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1085 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1087 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1088 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1089 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1090 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1091 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1092 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLK_IGNORE_UNUSED,
1093 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1096 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLK_IGNORE_UNUSED,
1097 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1099 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, CLK_IGNORE_UNUSED,
1100 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1101 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1104 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1105 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1106 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1107 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1108 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1109 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1111 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1112 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1113 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1114 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1116 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1117 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1118 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1119 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1121 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1122 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1123 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1125 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1126 RK3399_CLKSEL_CON(106), 0,
1127 &rk3399_dclk_vop0_fracmux),
1129 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1130 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1131 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1134 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1135 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1136 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1137 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1138 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1139 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1141 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1142 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1143 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1144 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1146 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1147 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1148 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1149 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1151 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1152 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1153 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1155 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1156 RK3399_CLKSEL_CON(107), 0,
1157 &rk3399_dclk_vop1_fracmux),
1159 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1160 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1161 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1164 COMPOSITE(0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1165 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1166 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1167 COMPOSITE_NOMUX(0, "hclk_isp0", "aclk_isp0", 0,
1168 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1169 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1171 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1172 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1173 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1174 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1175 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1176 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1178 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1179 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1180 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", CLK_IGNORE_UNUSED,
1181 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1183 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1184 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1185 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1187 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1188 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1189 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1190 COMPOSITE_NOMUX(0, "hclk_isp1", "aclk_isp1", 0,
1191 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1192 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1194 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1195 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1197 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1198 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1199 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", CLK_IGNORE_UNUSED,
1200 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1202 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1203 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1204 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1207 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1208 * so we ignore the mux and make clocks nodes as following,
1210 * pclkin_cifinv --|-------\
1211 * |GSC20_9|-- pclkin_cifmux
1212 * pclkin_cif --|-------/
1214 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cifmux", CLK_IGNORE_UNUSED,
1215 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1218 COMPOSITE(0, "clk_cifout_div", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1219 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 0, 5, DFLAGS,
1220 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1221 MUX(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
1222 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS),
1225 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1226 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1227 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1229 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1230 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1231 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1232 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1233 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1234 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1237 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1238 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1239 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1241 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1242 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1243 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1244 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1245 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1247 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1248 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1249 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1250 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1251 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1252 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1253 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1254 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1255 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1257 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1258 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1260 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1261 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1262 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1263 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1266 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1267 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1268 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1269 RK3399_CLKSEL_CON(105), 0,
1270 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1272 DIV(0, "clk_test_24m", "xin24m", 0,
1273 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1276 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1277 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1278 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1280 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1281 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1282 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1284 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1285 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1286 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1288 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1289 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1290 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1292 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1293 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1294 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1297 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1298 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1299 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1301 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1302 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1303 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1305 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1306 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1307 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1309 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1310 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1311 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1313 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1314 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1315 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1317 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1318 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1319 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1322 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1323 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1324 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1325 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1326 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1327 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1328 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1329 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1330 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1331 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1332 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1333 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1336 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1337 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1338 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1339 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1342 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1344 * PMU CRU Clock-Architecture
1347 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IGNORE_UNUSED,
1348 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1350 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IGNORE_UNUSED,
1351 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1353 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1354 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1355 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1357 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1358 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1359 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1361 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1362 RK3399_PMU_CLKSEL_CON(7), 0,
1363 &rk3399_pmuclk_wifi_fracmux),
1365 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1366 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1368 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1369 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1370 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1372 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1373 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1374 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1376 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1377 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1378 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1380 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1381 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1382 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1383 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1385 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1386 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1387 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1389 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1390 RK3399_PMU_CLKSEL_CON(6), 0,
1391 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1392 &rk3399_uart4_pmu_fracmux),
1394 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1395 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1397 /* pmu clock gates */
1398 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1399 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1401 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1403 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1404 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1405 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1406 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1407 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1408 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1409 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1410 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1411 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1412 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1413 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1414 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1415 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1416 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1417 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1418 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1420 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1421 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1422 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1423 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1424 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1427 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1444 "aclk_dmac0_perilp",
1445 "gpll_hclk_perilp1_src",
1446 "gpll_aclk_perilp0_src",
1447 "gpll_aclk_perihp_src",
1450 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1453 "fclk_cm0s_src_pmu",
1454 "clk_timer_src_pmu",
1457 static void __init rk3399_clk_init(struct device_node *np)
1459 struct rockchip_clk_provider *ctx;
1460 void __iomem *reg_base;
1462 reg_base = of_iomap(np, 0);
1464 pr_err("%s: could not map cru region\n", __func__);
1468 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1470 pr_err("%s: rockchip clk init failed\n", __func__);
1474 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1475 ARRAY_SIZE(rk3399_pll_clks), -1);
1477 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1478 ARRAY_SIZE(rk3399_clk_branches));
1480 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1481 ARRAY_SIZE(rk3399_cru_critical_clocks));
1483 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1484 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1485 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1486 ARRAY_SIZE(rk3399_cpuclkl_rates));
1488 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1489 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1490 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1491 ARRAY_SIZE(rk3399_cpuclkb_rates));
1493 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1494 ROCKCHIP_SOFTRST_HIWORD_MASK);
1496 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1498 rockchip_clk_of_add_provider(np, ctx);
1500 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1502 static void __init rk3399_pmu_clk_init(struct device_node *np)
1504 struct rockchip_clk_provider *ctx;
1505 void __iomem *reg_base;
1508 reg_base = of_iomap(np, 0);
1510 pr_err("%s: could not map cru pmu region\n", __func__);
1514 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1516 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1520 grf = rockchip_clk_get_grf(ctx);
1522 pr_err("%s: pmugrf regmap not available\n", __func__);
1526 /* enable gate for pclk_pmu_src */
1527 regmap_write(grf, RK3399_PMUGRF_SOC_CON0,
1528 HIWORD_UPDATE(0, RK3399_PMUCRU_PCLK_GATE_MASK,
1529 RK3399_PMUCRU_PCLK_GATE_SHIFT));
1531 /* enable pclk_alive_gpll_src gate */
1532 regmap_write(grf, RK3399_PMUGRF_SOC_CON0,
1533 HIWORD_UPDATE(0, RK3399_PMUCRU_PCLK_ALIVE_MASK,
1534 RK3399_PMUCRU_PCLK_ALIVE_SHIFT));
1536 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1537 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1539 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1540 ARRAY_SIZE(rk3399_clk_pmu_branches));
1542 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1543 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1545 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1546 ROCKCHIP_SOFTRST_HIWORD_MASK);
1548 rockchip_clk_of_add_provider(np, ctx);
1550 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
projects / firefly-linux-kernel-4.4.55.git / blob