drm/i915: Ensure cache flushes prior to doing CS flips

Synchronising to an object active on the same ring is a no-op, for the
benefit of execbuffer scheduler. However, for CS flips this means that
we can forgo checking whether the last write request of the object is
actually queued and more importantly whether the cache flush for the
write was emitted.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c890e03939fac03058ab60ff8225c8ee09e240ff..3c8801cecd3ff7fd824501acbbf5fe2e13c8241d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11040,6 +11040,12 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                i915_gem_request_assign(&work->flip_queued_req,
                                        obj->last_write_req);
        } else {
+               if (obj->last_write_req) {
+                       ret = i915_gem_check_olr(obj->last_write_req);
+                       if (ret)
+                               goto cleanup_unpin;
+               }
+
                ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
                                                   page_flip_flags);
                if (ret)