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(parent: 2e2f351) | patch
drm/i915: Ensure cache flushes prior to doing CS flips
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 27 Apr 2015 12:41:15 +0000 (13:41 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 20 May 2015 09:25:45 +0000 (11:25 +0200)
commitd94b5030d26b4f45510a092262bc2b542a00bd7c
tree68481d946955c5b7536a3341d4964e42da6de78ctree | snapshot
parent2e2f351dbf29681d54a3a0f1003c5bb9bc832072commit | diff
drm/i915: Ensure cache flushes prior to doing CS flips

Synchronising to an object active on the same ring is a no-op, for the
benefit of execbuffer scheduler. However, for CS flips this means that
we can forgo checking whether the last write request of the object is
actually queued and more importantly whether the cache flush for the
write was emitted.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
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