soc: rockchip: add cpuinfo support

Set system_serial_low/high from eFuse ID.
Serial can read from /proc/cpuinfo.

Change-Id: If412fc5a89a5e5092b510452fc5a126fdd374ac2
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/soc/rockchip/rockchip-cpuinfo.txt b/Documentation/devicetree/bindings/soc/rockchip/rockchip-cpuinfo.txt
new file mode 100644 (file)
index 0000000..2e80be3
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/rockchip/rockchip-cpuinfo.txt
@@ -0,0 +1,16 @@
+Rockchip cpuinfo device tree bindings
+----------------------------------
+
+Required properties:
+- compatible: Should be one of the following.
+ - "rockchip,cpuinfo"
+- nvmem-cells: A phandle to the ID data provided by a nvmem device.
+- nvmem-cell-names: Should be "id"
+
+Example:
+
+cpuinfo {
+       compatible = "rockchip,cpuinfo";
+       nvmem-cells = <&efuse_id>;
+       nvmem-cell-names = "id";
+};

diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig
index 4a34aab187c479685425b5e57f72f023a191c977..ae4cf24a8f70b95ee56f786f176bf6e7ac35e8f1 100644 (file)
--- a/drivers/soc/rockchip/Kconfig
+++ b/drivers/soc/rockchip/Kconfig
@@ -3,6 +3,16 @@ if ARCH_ROCKCHIP || COMPILE_TEST
 #
 # Rockchip Soc drivers
 #
 #
 # Rockchip Soc drivers
 #

+config ROCKCHIP_CPUINFO
+       tristate "Rockchip cpuinfo support"
+       depends on ROCKCHIP_EFUSE && (ARM64 || ARM)
+       help
+         Say y here to enable Rockchip cpuinfo support.
+         Set system_serial_low/high from eFuse ID.
+         Serial can read from /proc/cpuinfo.
+
+         If unsure, say N.
+

 config ROCKCHIP_PM_TEST
        bool "Rockchip pm_test support"
        default n
 config ROCKCHIP_PM_TEST
        bool "Rockchip pm_test support"
        default n

diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile
index 8c322d2ae911cba88c372b7b171840bb816cef03..4c2ee0cf58816c061c5ca92882b4dd94178cbc37 100644 (file)
--- a/drivers/soc/rockchip/Makefile
+++ b/drivers/soc/rockchip/Makefile
@@ -1,6 +1,7 @@
 #
 # Rockchip Soc drivers
 #
 #
 # Rockchip Soc drivers
 #

+obj-$(CONFIG_ROCKCHIP_CPUINFO) += rockchip-cpuinfo.o

 obj-$(CONFIG_ROCKCHIP_PM_TEST) += pm_test.o
 obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o
 obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o
 obj-$(CONFIG_ROCKCHIP_PM_TEST) += pm_test.o
 obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o
 obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o

diff --git a/drivers/soc/rockchip/rockchip-cpuinfo.c b/drivers/soc/rockchip/rockchip-cpuinfo.c
new file mode 100644 (file)
index 0000000..5c8e9f2
--- /dev/null
+++ b/drivers/soc/rockchip/rockchip-cpuinfo.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/crc32.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <asm/system_info.h>
+
+static int rockchip_cpuinfo_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct nvmem_cell *cell;
+       unsigned char *efuse_buf, buf[16];
+       size_t len;
+       int i;
+
+       cell = nvmem_cell_get(dev, "id");
+       if (IS_ERR(cell)) {
+               dev_err(dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
+               if (PTR_ERR(cell) == -EPROBE_DEFER)
+                       return PTR_ERR(cell);
+               return PTR_ERR(cell);
+       }
+       efuse_buf = nvmem_cell_read(cell, &len);
+       nvmem_cell_put(cell);
+
+       if (len != 16) {
+               kfree(efuse_buf);
+               dev_err(dev, "invalid id len: %zu\n", len);
+               return -EINVAL;
+       }
+
+       for (i = 0; i < 8; i++) {
+               buf[i] = efuse_buf[1 + (i << 1)];
+               buf[i + 8] = efuse_buf[i << 1];
+       }
+
+       kfree(efuse_buf);
+
+       system_serial_low = crc32(0, buf, 8);
+       system_serial_high = crc32(system_serial_low, buf + 8, 8);
+
+       dev_info(dev, "Serial\t\t: %08x%08x\n",
+                system_serial_high, system_serial_low);
+
+       return 0;
+}
+
+static const struct of_device_id rockchip_cpuinfo_of_match[] = {
+       { .compatible = "rockchip,cpuinfo", },
+       { },
+};
+MODULE_DEVICE_TABLE(of, rockchip_cpuinfo_of_match);
+
+static struct platform_driver rockchip_cpuinfo_driver = {
+       .probe = rockchip_cpuinfo_probe,
+       .driver = {
+               .name = "rockchip-cpuinfo",
+               .of_match_table = rockchip_cpuinfo_of_match,
+       },
+};
+module_platform_driver(rockchip_cpuinfo_driver);