Signed-off-by: chenjh <chenjh@rock-chips.com>
#include <asm/io.h>
#include "pm.h"
#include <asm/io.h>
#include "pm.h"
/*************************dump reg********************************************/
void rkpm_ddr_reg_offset_dump(void __iomem * base_addr,u32 _offset)
/*************************dump reg********************************************/
void rkpm_ddr_reg_offset_dump(void __iomem * base_addr,u32 _offset)
void rk_sram_suspend(void)
{
RKPM_DDR_FUN(regs_pread);
void rk_sram_suspend(void)
{
RKPM_DDR_FUN(regs_pread);
}
int cpu_suspend(unsigned long arg, int (*fn)(unsigned long));
}
int cpu_suspend(unsigned long arg, int (*fn)(unsigned long));
+#endif /* CONFIG_ARM */
+
static int rkpm_enter(suspend_state_t state)
{
//static u32 test_count=0;
static int rkpm_enter(suspend_state_t state)
{
//static u32 test_count=0;
if(rkpm_chk_jdg_ctrbits(RKPM_CTRBITS_SOC_DLPMD))
{
if(cpu_suspend(0,rk_lpmode_enter)==0)
if(rkpm_chk_jdg_ctrbits(RKPM_CTRBITS_SOC_DLPMD))
{
if(cpu_suspend(0,rk_lpmode_enter)==0)
+#else
+ flush_cache_all();
+ cpu_suspend(1);
+#endif
suspend_set_ops(&rockchip_suspend_ops);
return;
}
suspend_set_ops(&rockchip_suspend_ops);
return;
}
+
+#ifndef CONFIG_ARM
+static int __init rockchip_init_suspend(void)
+{
+ suspend_set_ops(&rockchip_suspend_ops);
+ return 0;
+}
+late_initcall_sync(rockchip_init_suspend);
#endif /* CONFIG_ARM */
static enum rockchip_pm_policy pm_policy;
#endif /* CONFIG_ARM */
static enum rockchip_pm_policy pm_policy;
#address-cells = <2>;
#size-cells = <0>;
#address-cells = <2>;
#size-cells = <0>;
+ idle-states {
+ entry-method = "arm,psci";
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0000000>;
+ entry-latency-us = <10000000>;
+ exit-latency-us = <10000000>;
+ min-residency-us = <25000>;
+ };
+ };
+
little0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
little0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
little1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
};
little1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
little2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
};
little2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
little3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
};
little3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
big0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
big0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
big1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
};
big1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
big2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
};
big2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
big3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
};
big3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
compatible = "arm,psci";
method = "smc";
cpu_on = <0xC4000003>;
compatible = "arm,psci";
method = "smc";
cpu_on = <0xC4000003>;
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
};
gic: interrupt-controller@ffb70000 {
};
gic: interrupt-controller@ffb70000 {
<&clk_gates12 5>,/*aclk_intmem0*/
<&clk_gates12 4>,/*aclk_intmem*/
<&clk_gates13 9>,/*aclk_gic400*/
<&clk_gates12 5>,/*aclk_intmem0*/
<&clk_gates12 4>,/*aclk_intmem*/
<&clk_gates13 9>,/*aclk_gic400*/
+ <&clk_gates12 9>,/*hclk_rom*/
/*PD_ALIVE*/
<&clk_gates22 13>,/*pclk_timer1*/
/*PD_ALIVE*/
<&clk_gates22 13>,/*pclk_timer1*/