arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x0000000>;
  45                                 entry-latency-us = <10000000>;
  46                                 exit-latency-us = <10000000>;
  47                                 min-residency-us = <25000>;
  48                         };
  49                 };
  50
  51                 little0: cpu@100 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x100>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@101 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x101>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@102 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x102>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@103 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x103>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x0>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x1>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@3 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x3>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci";
 142                 method = "smc";
 143                 cpu_on = <0xC4000003>;
 144                 cpu_suspend = <0x84000001>;
 145                 cpu_off = <0x84000002>;
 146         };
 147
 148         gic: interrupt-controller@ffb70000 {
 149                 compatible = "arm,cortex-a15-gic";
 150                 #interrupt-cells = <3>;
 151                 #address-cells = <0>;
 152                 interrupt-controller;
 153                 reg = <0x0 0xffb71000 0 0x1000>,
 154                       <0x0 0xffb72000 0 0x1000>;
 155         };
 156
 157         pmu: syscon@ff730000 {
 158                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 159                 reg = <0x0 0xff730000 0x0 0x1000>;
 160         };
 161
 162         pmugrf: syscon@ff738000 {
 163                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 164                 reg = <0x0 0xff738000 0x0 0x1000>;
 165         };
 166
 167         sgrf: syscon@ff740000 {
 168                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 169                 reg = <0x0 0xff740000 0x0 0x1000>;
 170
 171         };
 172
 173         cru: syscon@ff760000 {
 174                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 175                 reg = <0x0 0xff760000 0x0 0x1000>;
 176         };
 177
 178         grf: syscon@ff770000 {
 179                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 180                 reg = <0x0 0xff770000 0x0 0x1000>;
 181         };
 182
 183         arm-pmu {
 184                 compatible = "arm,armv8-pmuv3";
 185                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 193         };
 194
 195         cpu_axi_bus: cpu_axi_bus {
 196                 compatible = "rockchip,cpu_axi_bus";
 197                 #address-cells = <2>;
 198                 #size-cells = <2>;
 199                 ranges;
 200
 201                 qos {
 202                         #address-cells = <2>;
 203                         #size-cells = <2>;
 204                         ranges;
 205
 206                         dmac {
 207                                 reg = <0x0 0xffa80000 0x0 0x20>;
 208                         };
 209                         crypto {
 210                                 reg = <0x0 0xffa80080 0x0 0x20>;
 211                         };
 212                         bus_cpup {
 213                                 reg = <0x0 0xffa90000 0x0 0x20>;
 214                         };
 215                         cci_r {
 216                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 217                         };
 218                         cci_w {
 219                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 220                         };
 221                         peri {
 222                                 reg = <0x0 0xffab0000 0x0 0x20>;
 223                         };
 224                         iep {
 225                                 reg = <0x0 0xffad0000 0x0 0x20>;
 226                         };
 227                         isp_r0 {
 228                                 reg = <0x0 0xffad0080 0x0 0x20>;
 229                         };
 230                         isp_r1 {
 231                                 reg = <0x0 0xffad0100 0x0 0x20>;
 232                         };
 233                         isp_w0 {
 234                                 reg = <0x0 0xffad0180 0x0 0x20>;
 235                                 rockchip,priority = <2 2>;
 236                         };
 237                         isp_w1 {
 238                                 reg = <0x0 0xffad0200 0x0 0x20>;
 239                                 rockchip,priority = <2 2>;
 240                         };
 241                         vip {
 242                                 reg = <0x0 0xffad0280 0x0 0x20>;
 243                         };
 244                         vop {
 245                                 reg = <0x0 0xffad0300 0x0 0x20>;
 246                                 rockchip,priority = <2 2>;
 247                         };
 248                         rga_r {
 249                                 reg = <0x0 0xffad0380 0x0 0x20>;
 250                         };
 251                         rga_w {
 252                                 reg = <0x0 0xffad0400 0x0 0x20>;
 253                         };
 254                         hevc_r {
 255                                 reg = <0x0 0xffae0000 0x0 0x20>;
 256                         };
 257                         vpu_r {
 258                                 reg = <0x0 0xffae0080 0x0 0x20>;
 259                         };
 260                         vpu_w {
 261                                 reg = <0x0 0xffae0100 0x0 0x20>;
 262                         };
 263                 };
 264
 265                 msch {
 266                         #address-cells = <2>;
 267                         #size-cells = <2>;
 268                         ranges;
 269
 270                         msch {
 271                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 272                                 rockchip,read-latency = <0x34>;
 273                         };
 274                 };
 275         };
 276
 277         timer {
 278                 compatible = "arm,armv8-timer";
 279                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 280                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 281                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 282                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 283                 clock-frequency = <24000000>;
 284         };
 285
 286         timer@ff810000 {
 287                 compatible = "rockchip,timer";
 288                 reg = <0x0 0xff810000 0x0 0x20>;
 289                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 290                 rockchip,broadcast = <1>;
 291         };
 292
 293         sram: sram@ff8c0000 {
 294                 compatible = "mmio-sram";
 295                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 296                 map-exec;
 297         };
 298
 299         watchdog: wdt@ff800000 {
 300                 compatible = "rockchip,watch dog";
 301                 reg = <0x0 0xff800000 0x0 0x100>;
 302                 clocks = <&pclk_alive_pre>;
 303                 clock-names = "pclk_wdt";
 304                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 305                 rockchip,irq = <1>;
 306                 rockchip,timeout = <60>;
 307                 rockchip,atboot = <1>;
 308                 rockchip,debug = <0>;
 309                 status = "disabled";
 310         };
 311
 312         amba {
 313                 #address-cells = <2>;
 314                 #size-cells = <2>;
 315                 compatible = "arm,amba-bus";
 316                 interrupt-parent = <&gic>;
 317                 ranges;
 318
 319                 pdma0: pdma@ff600000 {
 320                         compatible = "arm,pl330", "arm,primecell";
 321                         reg = <0x0 0xff600000 0x0 0x4000>;
 322                         clocks = <&clk_gates12 11>;
 323                         clock-names = "apb_pclk";
 324                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 325                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 326                         #dma-cells = <1>;
 327
 328                 };
 329
 330                 pdma1: pdma@ff250000 {
 331                         compatible = "arm,pl330", "arm,primecell";
 332                         reg = <0x0 0xff250000 0x0 0x4000>;
 333                         clocks = <&clk_gates19 3>;
 334                         clock-names = "apb_pclk";
 335                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 337                         #dma-cells = <1>;
 338                 };
 339         };
 340
 341         reset: reset@ff760300{
 342                 compatible = "rockchip,reset";
 343                 reg = <0x0 0xff760300 0x0 0x38>;
 344                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 345                 #reset-cells = <1>;
 346         };
 347
 348         nandc0: nandc@ff400000 {
 349                 compatible = "rockchip,rk-nandc";
 350                 reg = <0x0 0xff400000 0x0 0x4000>;
 351                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 352                 nandc_id = <0>;
 353                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 354                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 355         };
 356
 357         nandc0reg: nandc0@ff400000 {
 358                 compatible = "rockchip,rk-nandc";
 359                 reg = <0x0 0xff400000 0x0 0x4000>;
 360         };
 361
 362         emmc: rksdmmc@ff0f0000 {
 363                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 364                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 365                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 369                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 370                 rockchip,grf = <&grf>;
 371                 num-slots = <1>;
 372                 fifo-depth = <0x100>;
 373                 bus-width = <8>;
 374         };
 375
 376         sdmmc: rksdmmc@ff0c0000 {
 377                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 378                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 379                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 pinctrl-names = "default", "idle", "udbg";
 383                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 384                 pinctrl-1 = <&sdmmc_gpio>;
 385                 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
 386                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 387                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 388                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 389                 rockchip,grf = <&grf>;
 390                 num-slots = <1>;
 391                 fifo-depth = <0x100>;
 392                 bus-width = <4>;
 393         };
 394
 395         sdio: rksdmmc@ff0d0000 {
 396                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 397                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 398                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 399                 #address-cells = <1>;
 400                 #size-cells = <0>;
 401                 pinctrl-names = "default","idle";
 402                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 403                 pinctrl-1 = <&sdio0_gpio>;
 404                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 405                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 406                 rockchip,grf = <&grf>;
 407                 num-slots = <1>;
 408                 fifo-depth = <0x100>;
 409                 bus-width = <4>;
 410         };
 411
 412         spi0: spi@ff110000 {
 413                 compatible = "rockchip,rockchip-spi";
 414                 reg = <0x0 0xff110000 0x0 0x1000>;
 415                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 420                 rockchip,spi-src-clk = <0>;
 421                 num-cs = <2>;
 422                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 423                 clock-names = "spi", "pclk_spi0";
 424                 //dmas = <&pdma1 11>, <&pdma1 12>;
 425                 //#dma-cells = <2>;
 426                 //dma-names = "tx", "rx";
 427                 status = "disabled";
 428         };
 429
 430         spi1: spi@ff120000 {
 431                 compatible = "rockchip,rockchip-spi";
 432                 reg = <0x0 0xff120000 0x0 0x1000>;
 433                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 438                 rockchip,spi-src-clk = <1>;
 439                 num-cs = <1>;
 440                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 441                 clock-names = "spi", "pclk_spi1";
 442                 //dmas = <&pdma1 13>, <&pdma1 14>;
 443                 //#dma-cells = <2>;
 444                 //dma-names = "tx", "rx";
 445                 status = "disabled";
 446         };
 447
 448         spi2: spi@ff130000 {
 449                 compatible = "rockchip,rockchip-spi";
 450                 reg = <0x0 0xff130000 0x0 0x1000>;
 451                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 452                 #address-cells = <1>;
 453                 #size-cells = <0>;
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 456                 rockchip,spi-src-clk = <2>;
 457                 num-cs = <1>;
 458                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 459                 clock-names = "spi", "pclk_spi2";
 460                 //dmas = <&pdma1 15>, <&pdma1 16>;
 461                 //#dma-cells = <2>;
 462                 //dma-names = "tx", "rx";
 463                 status = "disabled";
 464         };
 465
 466         uart_bt: serial@ff180000 {
 467                 compatible = "rockchip,serial";
 468                 reg = <0x0 0xff180000 0x0 0x100>;
 469                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 470                 clock-frequency = <24000000>;
 471                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 472                 clock-names = "sclk_uart", "pclk_uart";
 473                 reg-shift = <2>;
 474                 reg-io-width = <4>;
 475                 //dmas = <&pdma1 1>, <&pdma1 2>;
 476                 //#dma-cells = <2>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 479                 status = "disabled";
 480         };
 481
 482         uart_bb: serial@ff190000 {
 483                 compatible = "rockchip,serial";
 484                 reg = <0x0 0xff190000 0x0 0x100>;
 485                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 486                 clock-frequency = <24000000>;
 487                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 488                 clock-names = "sclk_uart", "pclk_uart";
 489                 reg-shift = <2>;
 490                 reg-io-width = <4>;
 491                 //dmas = <&pdma1 3>, <&pdma1 4>;
 492                 //#dma-cells = <2>;
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 495                 status = "disabled";
 496         };
 497
 498         uart_dbg: serial@ff690000 {
 499                 compatible = "rockchip,serial";
 500                 reg = <0x0 0xff690000 0x0 0x100>;
 501                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 502                 clock-frequency = <24000000>;
 503                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 504                 clock-names = "sclk_uart", "pclk_uart";
 505                 reg-shift = <2>;
 506                 reg-io-width = <4>;
 507                 //dmas = <&pdma0 4>, <&pdma0 5>;
 508                 //#dma-cells = <2>;
 509                 //pinctrl-names = "default";
 510                 //pinctrl-0 = <&uart2_xfer>;
 511                 status = "disabled";
 512         };
 513
 514         uart_gps: serial@ff1b0000 {
 515                 compatible = "rockchip,serial";
 516                 reg = <0x0 0xff1b0000 0x0 0x100>;
 517                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 518                 clock-frequency = <24000000>;
 519                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 520                 clock-names = "sclk_uart", "pclk_uart";
 521                 current-speed = <115200>;
 522                 reg-shift = <2>;
 523                 reg-io-width = <4>;
 524                 //dmas = <&pdma1 7>, <&pdma1 8>;
 525                 //#dma-cells = <2>;
 526                 pinctrl-names = "default";
 527                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 528                 status = "disabled";
 529         };
 530
 531         uart_exp: serial@ff1c0000 {
 532                 compatible = "rockchip,serial";
 533                 reg = <0x0 0xff1c0000 0x0 0x100>;
 534                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 535                 clock-frequency = <24000000>;
 536                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 537                 clock-names = "sclk_uart", "pclk_uart";
 538                 reg-shift = <2>;
 539                 reg-io-width = <4>;
 540                 //dmas = <&pdma1 9>, <&pdma1 10>;
 541                 //#dma-cells = <2>;
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 544                 status = "disabled";
 545         };
 546
 547         rockchip_clocks_init: clocks-init{
 548                 compatible = "rockchip,clocks-init";
 549                 rockchip,clocks-init-parent =
 550                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 551                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 552                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 553                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 554                 rockchip,clocks-init-rate =
 555                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 556                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 557                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 558                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 559                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 560                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 561                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 562                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 563                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 564                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 565                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 566                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 567                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 568                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 569                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 570                         <&clk_hevc_cabac 300000000>;
 571 /*
 572                 rockchip,clocks-uboot-has-init =
 573                         <&aclk_vio0>;
 574 */
 575         };
 576
 577         rockchip_clocks_enable: clocks-enable {
 578                 compatible = "rockchip,clocks-enable";
 579                 clocks =
 580                 <&pd_vio>,
 581                <&pd_video>,
 582                <&pd_gpu_0>,
 583                <&pd_gpu_1>,
 584
 585                         /*PLL*/
 586                         <&clk_apllb>,
 587                         <&clk_aplll>,
 588                         <&clk_dpll>,
 589                         <&clk_gpll>,
 590                         <&clk_cpll>,
 591
 592                         /*PD_CORE*/
 593                         <&clk_cs>,
 594                         <&clkin_trace>,
 595                         <&aclk_cci>,
 596
 597                         /*PD_BUS*/
 598                         <&aclk_bus>,
 599                         <&hclk_bus>,
 600                         <&pclk_bus>,
 601                         <&clk_gates12 12>,/*aclk_strc_sys*/
 602                         <&clk_gates12 6>,/*aclk_intmem1*/
 603                         <&clk_gates12 5>,/*aclk_intmem0*/
 604                         <&clk_gates12 4>,/*aclk_intmem*/
 605                         <&clk_gates13 9>,/*aclk_gic400*/
 606                         <&clk_gates12 9>,/*hclk_rom*/
 607
 608                         /*PD_ALIVE*/
 609                         <&clk_gates22 13>,/*pclk_timer1*/
 610                         <&clk_gates22 12>,/*pclk_timer0*/
 611                         <&clk_gates22 9>,/*pclk_alive_niu*/
 612                         <&clk_gates22 8>,/*pclk_grf*/
 613
 614                         /*PD_PMU*/
 615                         <&clk_gates23 5>,/*pclk_pmugrf*/
 616                         <&clk_gates23 3>,/*pclk_sgrf*/
 617                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 618                         <&clk_gates23 1>,/*pclk_intmem1*/
 619                         <&clk_gates23 0>,/*pclk_pmu*/
 620
 621                         /*PD_PERI*/
 622                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 623                         <&clk_gates20 8>,/*aclk_peri_niu*/
 624                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 625                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 626                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 627                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 628         };
 629
 630         /* I2C_PMU */
 631         i2c0: i2c@ff650000 {
 632                 compatible = "rockchip,rk30-i2c";
 633                 reg = <0x0 0xff650000 0x0 0x1000>;
 634                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 635                 #address-cells = <1>;
 636                 #size-cells = <0>;
 637                 pinctrl-names = "default", "gpio";
 638                 pinctrl-0 = <&i2c0_xfer>;
 639                 pinctrl-1 = <&i2c0_gpio>;
 640                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 641                 clocks = <&clk_gates12 2>;
 642                 rockchip,check-idle = <1>;
 643                 status = "disabled";
 644         };
 645
 646         /* I2C_AUDIO */
 647         i2c1: i2c@ff660000 {
 648                 compatible = "rockchip,rk30-i2c";
 649                 reg = <0x0 0xff660000 0x0 0x1000>;
 650                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 pinctrl-names = "default", "gpio";
 654                 pinctrl-0 = <&i2c1_xfer>;
 655                 pinctrl-1 = <&i2c1_gpio>;
 656                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 657                 clocks = <&clk_gates12 3>;
 658                 rockchip,check-idle = <1>;
 659                 status = "disabled";
 660         };
 661
 662         /* I2C_SENSOR */
 663         i2c2: i2c@ff140000 {
 664                 compatible = "rockchip,rk30-i2c";
 665                 reg = <0x0 0xff140000 0x0 0x1000>;
 666                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 667                 #address-cells = <1>;
 668                 #size-cells = <0>;
 669                 pinctrl-names = "default", "gpio";
 670                 pinctrl-0 = <&i2c2_xfer>;
 671                 pinctrl-1 = <&i2c2_gpio>;
 672                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 673                 clocks = <&clk_gates19 11>;
 674                 rockchip,check-idle = <1>;
 675                 status = "disabled";
 676         };
 677
 678         /* I2C_CAM */
 679         i2c3: i2c@ff150000 {
 680                 compatible = "rockchip,rk30-i2c";
 681                 reg = <0x0 0xff150000 0x0 0x1000>;
 682                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 pinctrl-names = "default", "gpio";
 686                 pinctrl-0 = <&i2c3_xfer>;
 687                 pinctrl-1 = <&i2c3_gpio>;
 688                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 689                 clocks = <&clk_gates19 12>;
 690                 rockchip,check-idle = <1>;
 691                 status = "disabled";
 692         };
 693
 694         /* I2C_TP */
 695         i2c4: i2c@ff160000 {
 696                 compatible = "rockchip,rk30-i2c";
 697                 reg = <0x0 0xff160000 0x0 0x1000>;
 698                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 pinctrl-names = "default", "gpio";
 702                 pinctrl-0 = <&i2c4_xfer>;
 703                 pinctrl-1 = <&i2c4_gpio>;
 704                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 705                 clocks = <&clk_gates19 13>;
 706                 rockchip,check-idle = <1>;
 707                 status = "disabled";
 708         };
 709
 710         /* I2C_HDMI */
 711         i2c5: i2c@ff170000 {
 712                 compatible = "rockchip,rk30-i2c";
 713                 reg = <0x0 0xff170000 0x0 0x1000>;
 714                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 715                 #address-cells = <1>;
 716                 #size-cells = <0>;
 717                 pinctrl-names = "default", "gpio";
 718                 pinctrl-0 = <&i2c5_xfer>;
 719                 pinctrl-1 = <&i2c5_gpio>;
 720                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 721                 clocks = <&clk_gates19 14>;
 722                 rockchip,check-idle = <1>;
 723                 status = "disabled";
 724         };
 725
 726         fb: fb {
 727                 compatible = "rockchip,rk-fb";
 728                 rockchip,disp-mode = <NO_DUAL>;
 729         };
 730
 731
 732         rk_screen: rk_screen {
 733                 compatible = "rockchip,screen";
 734         };
 735
 736         dsihost0: mipi@ff960000{
 737                 compatible = "rockchip,rk3368-dsi";
 738                 rockchip,prop = <0>;
 739                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 740                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 741                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 743                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 744                 status = "okay";
 745         };
 746
 747         lvds: lvds@ff968000 {
 748                 compatible = "rockchip,rk3368-lvds";
 749                 rockchip,grf = <&grf>;
 750                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 751                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 752                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 753                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 754                 status = "disabled";
 755         };
 756
 757         edp: edp@ff970000 {
 758                 compatible = "rockchip,rk32-edp";
 759                 reg = <0x0 0xff970000 0x0 0x4000>;
 760                 rockchip,grf = <&grf>;
 761                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 762                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 763                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 764                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 765                 reset-names = "edp_24m", "edp_apb";
 766         };
 767
 768         hdmi: hdmi@ff980000 {
 769                 compatible = "rockchip,rk3368-hdmi";
 770                 reg = <0x0 0xff980000 0x0 0x20000>;
 771                 rockchip,grf = <&grf>;
 772                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 773                 pinctrl-names = "default", "gpio";
 774                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 775                 pinctrl-1 = <&i2c5_gpio>;
 776                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 777                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 778                 status = "disabled";
 779         };
 780
 781         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 782                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 783                 reg = <0x0 0xff978000 0x0 0x2000>;
 784                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 785                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 786                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 787                 status = "disabled";
 788         };
 789
 790         lcdc: lcdc@ff930000 {
 791                  compatible = "rockchip,rk3368-lcdc";
 792                  rockchip,grf = <&grf>;
 793                  rockchip,pmugrf = <&pmugrf>;
 794                  rockchip,prop = <PRMRY>;
 795                  rockchip,pwr18 = <0>;
 796                  rockchip,iommu-enabled = <0>;
 797                  reg = <0x0 0xff930000 0x0 0x10000>;
 798                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 799                 /*pinctrl-names = "default", "gpio";
 800                  *pinctrl-0 = <&lcdc_lcdc>;
 801                  *pinctrl-1 = <&lcdc_gpio>;
 802                  */
 803                  status = "disabled";
 804                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 805                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 806         };
 807
 808         adc: adc@ff100000 {
 809                 compatible = "rockchip,saradc";
 810                 reg = <0x0 0xff100000 0x0 0x100>;
 811                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 812                 #io-channel-cells = <1>;
 813                 io-channel-ranges;
 814                 rockchip,adc-vref = <1800>;
 815                 clock-frequency = <1000000>;
 816                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 817                 clock-names = "saradc", "pclk_saradc";
 818                 status = "disabled";
 819         };
 820
 821         rga@ff920000 {
 822                 compatible = "rockchip,rk3368-rga2";
 823                 reg = <0x0 0xff920000 0x0 0x1000>;
 824                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 825                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 826                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 827         };
 828
 829         i2s0: i2s0@ff898000 {
 830                 compatible = "rockchip-i2s";
 831                 reg = <0x0 0xff898000 0x0 0x1000>;
 832                 i2s-id = <0>;
 833                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 834                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 835                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 836                 dmas = <&pdma0 0>, <&pdma0 1>;
 837                 #dma-cells = <2>;
 838                 dma-names = "tx", "rx";
 839                 pinctrl-names = "default", "sleep";
 840                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 841                 pinctrl-1 = <&i2s_gpio>;
 842         };
 843
 844         i2s1: i2s1@ff890000 {
 845                 compatible = "rockchip-i2s";
 846                 reg = <0x0 0xff890000 0x0 0x1000>;
 847                 i2s-id = <1>;
 848                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 849                 clock-names = "i2s_clk", "i2s_hclk";
 850                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 851                 dmas = <&pdma0 6>, <&pdma0 7>;
 852                 #dma-cells = <2>;
 853                 dma-names = "tx", "rx";
 854         };
 855
 856         spdif: spdif@ff880000 {
 857                 compatible = "rockchip-spdif";
 858                 reg = <0x0 0xff880000 0x0 0x1000>;
 859                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 860                 clock-names = "spdif_mclk", "spdif_hclk";
 861                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 862                 dmas = <&pdma0 3>;
 863                 #dma-cells = <1>;
 864                 dma-names = "tx";
 865                 pinctrl-names = "default";
 866                 pinctrl-0 = <&spdif_tx>;
 867         };
 868
 869         pwm0: pwm@ff680000 {
 870                 compatible = "rockchip,rk-pwm";
 871                 reg = <0x0 0xff680000 0x0 0x10>;
 872                 #pwm-cells = <2>;
 873                 pinctrl-names = "default";
 874                 pinctrl-0 = <&pwm0_pin>;
 875                 clocks = <&clk_gates13 6>;
 876                 clock-names = "pclk_pwm";
 877                 status = "disabled";
 878         };
 879
 880         pwm1: pwm@ff680010 {
 881                 compatible = "rockchip,rk-pwm";
 882                 reg = <0x0 0xff680010 0x0 0x10>;
 883                 #pwm-cells = <2>;
 884                 pinctrl-names = "default";
 885                 pinctrl-0 = <&pwm1_pin>;
 886                 clocks = <&clk_gates13 6>;
 887                 clock-names = "pclk_pwm";
 888                 status = "disabled";
 889         };
 890
 891         pwm2: pwm@ff680020 {
 892                 compatible = "rockchip,rk-pwm";
 893                 reg = <0x0 0xff680020 0x0 0x10>;
 894                 #pwm-cells = <2>;
 895                 //pinctrl-names = "default";
 896                 //pinctrl-0 = <&pwm1_pin>;
 897                 clocks = <&clk_gates13 6>;
 898                 clock-names = "pclk_pwm";
 899                 status = "disabled";
 900         };
 901
 902         pwm3: pwm@ff680030 {
 903                 compatible = "rockchip,rk-pwm";
 904                 reg = <0x0 0xff680030 0x0 0x10>;
 905                 #pwm-cells = <2>;
 906                 pinctrl-names = "default";
 907                 pinctrl-0 = <&pwm3_pin>;
 908                 clocks = <&clk_gates13 6>;
 909                 clock-names = "pclk_pwm";
 910                 status = "disabled";
 911         };
 912
 913         remotectl: pwm@ff680030 {
 914                 compatible = "rockchip,remotectl-pwm";
 915                 reg = <0x0 0xff680030 0x0 0x50>;
 916                 #pwm-cells = <2>;
 917                 pinctrl-names = "default";
 918                 pinctrl-0 = <&pwm3_pin>;
 919                 clocks = <&clk_gates13 6>;
 920                 clock-names = "pclk_pwm";
 921                 dmas = <&pdma0 2>;
 922                 #dma-cells = <2>;
 923                 dma-names = "rx";
 924                 remote_pwm_id = <3>;
 925                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 926                 status = "disabled";
 927         };
 928
 929         voppwm: pwm@ff9301a0 {
 930                 compatible = "rockchip,vop-pwm";
 931                 reg = <0x0 0xff9301a0 0x0 0x10>;
 932                 #pwm-cells = <2>;
 933                 pinctrl-names = "default";
 934                 pinctrl-0 = <&vop_pwm_pin>;
 935                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 936                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 937                 status = "disabled";
 938         };
 939
 940         pvtm {
 941                 compatible = "rockchip,rk3368-pvtm";
 942                 rockchip,grf = <&grf>;
 943                 rockchip,pmugrf = <&pmugrf>;
 944                 rockchip,pvtm-clk-out = <1>;
 945         };
 946
 947         cpufreq {
 948                 compatible = "rockchip,rk3368-cpufreq";
 949                 rockchip,grf = <&grf>;
 950         };
 951
 952         dvfs {
 953
 954                 vd_arm: vd_arm {
 955                         regulator_name = "vdd_arm";
 956                         suspend_volt = <1000>; //mV
 957                         pd_core {
 958                                 clk_core_b_dvfs_table: clk_core_b {
 959                                         operating-points = <
 960                                                 /* KHz    uV */
 961                                                 312000 1200000
 962                                                 504000 1200000
 963                                                 816000 1200000
 964                                                 1008000 1200000
 965                                                 >;
 966                                         status = "okay";
 967                                 };
 968                                 clk_core_l_dvfs_table: clk_core_l {
 969                                         operating-points = <
 970                                                 /* KHz    uV */
 971                                                 312000 1200000
 972                                                 504000 1200000
 973                                                 816000 1200000
 974                                                 1008000 1200000
 975                                                 >;
 976                                         status = "okay";
 977                                 };
 978                         };
 979                 };
 980
 981                 vd_logic: vd_logic {
 982                         regulator_name = "vdd_logic";
 983                         suspend_volt = <1000>; //mV
 984                         pd_ddr {
 985                                 clk_ddr_dvfs_table: clk_ddr {
 986                                         operating-points = <
 987                                                 /* KHz    uV */
 988                                                 200000 1200000
 989                                                 300000 1200000
 990                                                 400000 1200000
 991                                                 >;
 992                                         channel = <2>;
 993                                         status = "disabled";
 994                                 };
 995                         };
 996
 997                         pd_gpu {
 998                                 clk_gpu_dvfs_table: clk_gpu {
 999                                         operating-points = <
1000                                                 /* KHz    uV */
1001                                                 200000 1200000
1002                                                 300000 1200000
1003                                                 400000 1200000
1004                                                 >;
1005                                         channel = <1>;
1006                                         status = "okay";
1007                                         regu-mode-table = <
1008                                                 /*freq     mode*/
1009                                                 200000     4
1010                                                 0          3
1011                                         >;
1012                                         regu-mode-en = <0>;
1013                                 };
1014                         };
1015                 };
1016         };
1017
1018         ion {
1019                 compatible = "rockchip,ion";
1020                 #address-cells = <1>;
1021                 #size-cells = <0>;
1022
1023                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1024                         compatible = "rockchip,ion-heap";
1025                         rockchip,ion_heap = <4>;
1026                         reg = <0x00000000 0x08000000>; /* 512MB */
1027                 };
1028                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1029                         compatible = "rockchip,ion-heap";
1030                         rockchip,ion_heap = <0>;
1031                 };
1032         };
1033
1034         vpu: vpu_service {
1035                 compatible = "rockchip,vpu_sub";
1036                 iommu_enabled = <0>;
1037                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1038                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1039                 interrupt-names = "irq_enc", "irq_dec";
1040                 dev_mode = <0>;
1041                 name = "vpu_service";
1042         };
1043
1044         hevc: hevc_service {
1045                 compatible = "rockchip,hevc_sub";
1046                 iommu_enabled = <0>;
1047                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1048                 interrupt-names = "irq_dec";
1049                 dev_mode = <1>;
1050                 name = "hevc_service";
1051         };
1052
1053         vpu_combo: vpu_combo@ff9a0000 {
1054                 compatible = "rockchip,vpu_combo";
1055                 reg = <0x0 0xff9a0000 0x0 0x800>;
1056                 rockchip,grf = <&grf>;
1057                 subcnt = <2>;
1058                 rockchip,sub = <&vpu>, <&hevc>;
1059                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1060                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1061                 mode_bit = <12>;
1062                 mode_ctrl = <0x418>;
1063                 name = "vpu_combo";
1064                 status = "okay";
1065         };
1066
1067         iep: iep@ff900000 {
1068                 compatible = "rockchip,iep";
1069                 iommu_enabled = <0>;
1070                 reg = <0x0 0xff900000 0x0 0x800>;
1071                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1072                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1073                 clock-names = "aclk_iep", "hclk_iep";
1074                 status = "okay";
1075         };
1076
1077         gmac: eth@ff290000 {
1078                 compatible = "rockchip,rk3368-gmac";
1079                 reg = <0x0 0xff290000 0x0 0x10000>;
1080                 rockchip,grf = <&grf>;
1081                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1082                 interrupt-names = "macirq";
1083
1084                 clocks = <&clk_mac>, <&clk_gates7 4>,
1085                          <&clk_gates7 5>, <&clk_gates7 6>,
1086                          <&clk_gates7 7>, <&clk_gates20 13>,
1087                          <&clk_gates20 14>;
1088                 clock-names = "clk_mac", "mac_clk_rx",
1089                               "mac_clk_tx", "clk_mac_ref",
1090                               "clk_mac_refout", "aclk_mac",
1091                               "pclk_mac";
1092
1093                 phy-mode = "rgmii";
1094                 pinctrl-names = "default";
1095                 pinctrl-0 = <&rgmii_pins>;
1096         };
1097
1098         gpu {
1099                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1100                 reg = <0x0 0xffa30000 0x0 0x10000>;
1101                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1102                 interrupt-names = "GPU";
1103         };
1104
1105         iep_mmu {
1106                 dbgname = "iep";
1107                 compatible = "rockchip,iep_mmu";
1108                 reg = <0x0 0xff900800 0x0 0x100>;
1109                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1110                 interrupt-names = "iep_mmu";
1111         };
1112
1113         vip_mmu {
1114                 dbgname = "vip";
1115                 compatible = "rockchip,vip_mmu";
1116                 reg = <0x0 0xff950800 0x0 0x100>;
1117                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1118                 interrupt-names = "vip_mmu";
1119         };
1120
1121         vop_mmu {
1122                 dbgname = "vop";
1123                 compatible = "rockchip,vopb_mmu";
1124                 reg = <0x0 0xff930300 0x0 0x100>;
1125                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1126                 interrupt-names = "vop_mmu";
1127         };
1128
1129         isp_mmu {
1130                 dbgname = "isp_mmu";
1131                 compatible = "rockchip,isp_mmu";
1132                 reg = <0x0 0xff914000 0x0 0x100>,
1133                 <0x0 0xff915000 0x0 0x100>;
1134                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1135                 interrupt-names = "isp_mmu";
1136         };
1137
1138         hdcp_mmu {
1139                 dbgname = "hdcp_mmu";
1140                 compatible = "rockchip,hdcp_mmu";
1141                 reg = <0x0 0xff940000 0x0 0x100>;
1142                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1143                 interrupt-names = "hdcp_mmu";
1144         };
1145
1146         hevc_mmu {
1147                 dbgname = "hevc";
1148                 compatible = "rockchip,hevc_mmu";
1149                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1150                           <0x0 0xff9c0480 0x0 0x40>;
1151                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1152                 interrupt-names = "hevc_mmu";
1153         };
1154
1155         vpu_mmu {
1156                 dbgname = "vpu";
1157                 compatible = "rockchip,vpu_mmu";
1158                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1159                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1160                 interrupt-names = "vpu_mmu";
1161         };
1162
1163         rockchip_suspend {
1164                 rockchip,ctrbits = <
1165                         (0
1166                          |RKPM_CTR_PWR_DMNS
1167                          |RKPM_CTR_GTCLKS
1168                          |RKPM_CTR_PLLS
1169                          |RKPM_CTR_GPIOS
1170                         /*
1171                          |RKPM_CTR_SYSCLK_DIV
1172                          |RKPM_CTR_IDLEAUTO_MD
1173                          |RKPM_CTR_ARMOFF_LPMD
1174                         */
1175                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1176                         )
1177                         >;
1178                 rockchip,pmic-suspend_gpios = <
1179                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1180                         >;
1181                 rockchip,pmic-resume_gpios = <
1182                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1183                         >;
1184         };
1185
1186         isp: isp@ff910000{
1187                 compatible = "rockchip,isp";
1188                 reg = <0x0 0xff910000 0x0 0x10000>;
1189                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1190                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1191                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1192                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1193                 pinctrl-0 = <&cif_clkout>;
1194                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1195                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1196                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1197                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1198                 pinctrl-5 = <&cif_clkout>;
1199                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1200                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1201                 pinctrl-8 = <&isp_flash_trigger>;
1202                 rockchip,isp,mipiphy = <2>;
1203                 rockchip,isp,cifphy = <1>;
1204                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1205                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1206                 rockchip,grf = <&grf>;
1207                 rockchip,cru = <&cru>;
1208                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1209                 rockchip,isp,iommu_enable = <0>;
1210                 status = "okay";
1211         };
1212
1213         cif: cif@ff950000 {
1214                 compatible = "rockchip,cif";
1215                 reg = <0x0 0xff950000 0x0 0x10000>;
1216                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1217                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1218                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1219                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1220                 pinctrl-names = "cif_pin_all";
1221                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1222                 rockchip,grf = <&grf>;
1223                 rockchip,cru = <&cru>;
1224                 status = "okay";
1225         };
1226
1227 /*
1228         thermal-zones {
1229                 #include "rk3368-thermal.dtsi"
1230         };
1231 */
1232
1233         tsadc: tsadc@ff280000 {
1234                 compatible = "rockchip,rk3368-tsadc";
1235                 reg = <0x0 0xff280000 0x0 0x100>;
1236                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1237                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1238                 rockchip,grf = <&grf>;
1239                 rockchip,cru = <&cru>;
1240                 rockchip,pmu = <&pmu>;
1241                 clock-names = "tsadc", "apb_pclk";
1242                 clock-frequency = <32000>;
1243                 resets = <&reset RK3368_SRST_TSADC_P>;
1244                 reset-names = "tsadc-apb";
1245                 //pinctrl-names = "default";
1246                 //pinctrl-0 = <&tsadc_int>;
1247                 #thermal-sensor-cells = <1>;
1248                 hw-shut-temp = <120000>;
1249                 status = "disabled";
1250         };
1251
1252         tsp: tsp@FF8B0000 {
1253                 compatible = "rockchip,rk3368-tsp";
1254                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1255                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1256                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1257                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1258                 interrupt-names = "irq_tsp";
1259                 // pinctrl-names = "default";
1260                 // pinctrl-0 = <&isp_hsadc>;
1261                 status = "okay";
1262         };
1263
1264         crypto: crypto@FF8A0000{
1265                 compatible = "rockchip,rk3368-crypto";
1266                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1267                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1268                 interrupt-names = "irq_crypto";
1269                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1270                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1271                 status = "okay";
1272         };
1273
1274         dwc_control_usb: dwc-control-usb {
1275                 compatible = "rockchip,rk3368-dwc-control-usb";
1276                 rockchip,grf = <&grf>;
1277                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1278                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1279                 interrupt-names = "otg_id", "otg_bvalid",
1280                                   "otg_linestate", "host0_linestate";
1281                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1282                 clock-names = "hclk_usb_peri", "usbphy_480m";
1283                 //resets = <&reset RK3128_RST_USBPOR>;
1284                 //reset-names = "usbphy_por";
1285                 usb_bc{
1286                         compatible = "inno,phy";
1287                         regbase = &dwc_control_usb;
1288                         rk_usb,bvalid     = <0x4bc 23 1>;
1289                         rk_usb,iddig      = <0x4bc 26 1>;
1290                         rk_usb,vdmsrcen   = <0x718 12 1>;
1291                         rk_usb,vdpsrcen   = <0x718 11 1>;
1292                         rk_usb,rdmpden    = <0x718 10 1>;
1293                         rk_usb,idpsrcen   = <0x718  9 1>;
1294                         rk_usb,idmsinken  = <0x718  8 1>;
1295                         rk_usb,idpsinken  = <0x718  7 1>;
1296                         rk_usb,dpattach   = <0x4b8 31 1>;
1297                         rk_usb,cpdet      = <0x4b8 30 1>;
1298                         rk_usb,dcpattach  = <0x4b8 29 1>;
1299                 };
1300         };
1301
1302         usb0: usb@ff580000 {
1303                 compatible = "rockchip,rk3368_usb20_otg";
1304                 reg = <0x0 0xff580000 0x0 0x40000>;
1305                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1306                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1307                 clock-names = "clk_usbphy0", "hclk_otg";
1308                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1309                                 <&reset RK3368_SRST_USBOTGC0>;
1310                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1311                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1312                 rockchip,usb-mode = <0>;
1313         };
1314
1315         usb_ehci: usb@ff500000 {
1316                 compatible = "generic-ehci";
1317                 reg = <0x0 0xff500000 0x0 0x20000>;
1318                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1319                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1320                 clock-names = "clk_usbphy0", "hclk_ehci";
1321                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1322                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1323                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1324         };
1325
1326         usb_ohci: usb@ff520000 {
1327                 compatible = "generic-ohci";
1328                 reg = <0x0 0xff520000 0x0 0x20000>;
1329                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1330                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1331                 clock-names =  "clk_usbphy0", "hclk_ohci";
1332         };
1333
1334         usb_hsic: usb@ff5c0000 {
1335                 compatible = "rockchip,rk3288_rk_hsic_host";
1336                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1337                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1338 /*
1339                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1340                          <&hsicphy_12m>, <&usbphy_480m>,
1341                          <&otgphy1_480m>, <&otgphy2_480m>;
1342                 clock-names = "hsicphy_480m", "hclk_hsic",
1343                               "hsicphy_12m", "usbphy_480m",
1344                               "hsic_usbphy1", "hsic_usbphy2";
1345                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1346                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1347                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1348 */
1349                 status = "disabled";
1350         };
1351
1352         pinctrl: pinctrl {
1353                 compatible = "rockchip,rk3368-pinctrl";
1354                 rockchip,grf = <&grf>;
1355                 rockchip,pmugrf = <&pmugrf>;
1356                 #address-cells = <2>;
1357                 #size-cells = <2>;
1358                 ranges;
1359
1360                 gpio0: gpio0@ff750000 {
1361                         compatible = "rockchip,gpio-bank";
1362                         reg =   <0x0 0xff750000 0x0 0x100>;
1363                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1364                         clocks = <&clk_gates23 4>;
1365
1366                         gpio-controller;
1367                         #gpio-cells = <2>;
1368
1369                         interrupt-controller;
1370                         #interrupt-cells = <2>;
1371                 };
1372
1373                 gpio1: gpio1@ff780000 {
1374                         compatible = "rockchip,gpio-bank";
1375                         reg = <0x0 0xff780000 0x0 0x100>;
1376                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1377                         clocks = <&clk_gates22 1>;
1378
1379                         gpio-controller;
1380                         #gpio-cells = <2>;
1381
1382                         interrupt-controller;
1383                         #interrupt-cells = <2>;
1384                 };
1385
1386                 gpio2: gpio2@ff790000 {
1387                         compatible = "rockchip,gpio-bank";
1388                         reg = <0x0 0xff790000 0x0 0x100>;
1389                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1390                         clocks = <&clk_gates22 2>;
1391
1392                         gpio-controller;
1393                         #gpio-cells = <2>;
1394
1395                         interrupt-controller;
1396                         #interrupt-cells = <2>;
1397                 };
1398
1399                 gpio3: gpio3@ff7a0000 {
1400                         compatible = "rockchip,gpio-bank";
1401                         reg = <0x0 0xff7a0000 0x0 0x100>;
1402                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1403                         clocks = <&clk_gates22 3>;
1404
1405                         gpio-controller;
1406                         #gpio-cells = <2>;
1407
1408                         interrupt-controller;
1409                         #interrupt-cells = <2>;
1410                 };
1411
1412                 pcfg_pull_up: pcfg-pull-up {
1413                         bias-pull-up;
1414                 };
1415
1416                 pcfg_pull_down: pcfg-pull-down {
1417                         bias-pull-down;
1418                 };
1419
1420                 pcfg_pull_none: pcfg-pull-none {
1421                         bias-disable;
1422                 };
1423
1424                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1425                         drive-strength = <8>;
1426                 };
1427
1428                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1429                         drive-strength = <12>;
1430                 };
1431
1432                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1433                         bias-pull-up;
1434                         drive-strength = <8>;
1435                 };
1436
1437                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1438                         drive-strength = <4>;
1439                 };
1440
1441                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1442                         bias-pull-up;
1443                         drive-strength = <4>;
1444                 };
1445
1446                 pcfg_output_high: pcfg-output-high {
1447                         output-high;
1448                 };
1449
1450                 pcfg_output_low: pcfg-output-low {
1451                         output-low;
1452                 };
1453
1454                 i2c0 {
1455                         i2c0_xfer: i2c0-xfer {
1456                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1457                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1458                         };
1459                         i2c0_gpio: i2c0-gpio {
1460                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1461                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1462                         };
1463                 };
1464
1465                 i2c1 {
1466                         i2c1_xfer: i2c1-xfer {
1467                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1468                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1469                         };
1470                         i2c1_gpio: i2c1-gpio {
1471                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1472                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1473                         };
1474                 };
1475
1476                 i2c2 {
1477                         i2c2_xfer: i2c2-xfer {
1478                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1479                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1480                         };
1481                         i2c2_gpio: i2c2-gpio {
1482                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1483                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1484             };
1485                 };
1486
1487                 i2c3 {
1488                         i2c3_xfer: i2c3-xfer {
1489                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1490                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1491                         };
1492                         i2c3_gpio: i2c3-gpio {
1493                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1494                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1495                         };
1496                 };
1497
1498                 i2c4 {
1499                         i2c4_xfer: i2c4-xfer {
1500                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1501                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1502                         };
1503                         i2c4_gpio: i2c4-gpio {
1504                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1505                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1506                         };
1507                 };
1508
1509                 i2c5 {
1510                         i2c5_xfer: i2c5-xfer {
1511                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1512                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1513                         };
1514                         i2c5_gpio: i2c5-gpio {
1515                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1516                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1517                         };
1518                 };
1519
1520                 uart0 {
1521                         uart0_xfer: uart0-xfer {
1522                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1523                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1524                         };
1525
1526                         uart0_cts: uart0-cts {
1527                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1528                         };
1529
1530                         uart0_rts: uart0-rts {
1531                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1532                         };
1533
1534                         uart0_rts_gpio: uart0-rts-gpio {
1535                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 uart1 {
1540                         uart1_xfer: uart1-xfer {
1541                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1542                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1543                         };
1544
1545                         uart1_cts: uart1-cts {
1546                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1547                         };
1548
1549                         uart1_rts: uart1-rts {
1550                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1551                         };
1552                 };
1553
1554                 uart2 {
1555                         uart2_xfer: uart2-xfer {
1556                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1557                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1558                         };
1559                 };
1560
1561                 uart3 {
1562                         uart3_xfer: uart3-xfer {
1563                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1564                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1565                         };
1566
1567                         uart3_cts: uart3-cts {
1568                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1569                         };
1570
1571                         uart3_rts: uart3-rts {
1572                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1573                         };
1574                 };
1575
1576                 uart4 {
1577                         uart4_xfer: uart4-xfer {
1578                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1579                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1580                         };
1581
1582                         uart4_cts: uart4-cts {
1583                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1584                         };
1585
1586                         uart4_rts: uart4-rts {
1587                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1588                         };
1589                 };
1590
1591                 spi0 {
1592                         spi0_clk: spi0-clk {
1593                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1594                         };
1595                         spi0_cs0: spi0-cs0 {
1596                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1597                         };
1598                         spi0_tx: spi0-tx {
1599                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1600                         };
1601                         spi0_rx: spi0-rx {
1602                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1603                         };
1604                         spi0_cs1: spi0-cs1 {
1605                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1606                         };
1607                 };
1608
1609                 spi1 {
1610                         spi1_clk: spi1-clk {
1611                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1612                         };
1613                         spi1_cs0: spi1-cs0 {
1614                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1615                         };
1616                         spi1_rx: spi1-rx {
1617                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1618                         };
1619                         spi1_tx: spi1-tx {
1620                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1621                         };
1622                 };
1623
1624                 spi2 {
1625                         spi2_clk: spi2-clk {
1626                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1627                         };
1628                         spi2_cs0: spi2-cs0 {
1629                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1630                         };
1631                         spi2_rx: spi2-rx {
1632                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1633                         };
1634                         spi2_tx: spi2-tx {
1635                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1636                         };
1637                 };
1638
1639                 i2s {
1640                         i2s_mclk: i2s-mclk {
1641                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1642                         };
1643
1644                         i2s_sclk:i2s-sclk {
1645                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1646                         };
1647
1648                         i2s_lrckrx:i2s-lrckrx {
1649                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651
1652                         i2s_lrcktx:i2s-lrcktx {
1653                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1654                         };
1655
1656                         i2s_sdi:i2s-sdi {
1657                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1658                         };
1659
1660                         i2s_sdo0:i2s-sdo0 {
1661                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1662                         };
1663
1664                         i2s_sdo1:i2s-sdo1 {
1665                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1666                         };
1667
1668                         i2s_sdo2:i2s-sdo2 {
1669                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1670                         };
1671
1672                         i2s_sdo3:i2s-sdo3 {
1673                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1674                         };
1675
1676                         i2s_gpio: i2s-gpio {
1677                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1678                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1679                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1680                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1681                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1682                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1683                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1684                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1685                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1686                         };
1687                 };
1688
1689                 spdif {
1690                         spdif_tx: spdif-tx {
1691                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1692                         };
1693                 };
1694
1695                 sdmmc {
1696                         sdmmc_clk: sdmmc-clk {
1697                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1698                         };
1699
1700                         sdmmc_cmd: sdmmc-cmd {
1701                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1702                         };
1703
1704                         sdmmc_dectn: sdmmc-dectn {
1705                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1706                         };
1707
1708                         sdmmc_bus1: sdmmc-bus1 {
1709                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1710                         };
1711
1712                         sdmmc_bus4: sdmmc-bus4 {
1713                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1714                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1715                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1716                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1717                         };
1718
1719                         sdmmc_gpio: sdmmc-gpio {
1720                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1721                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1722                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1723                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1724                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1725                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1726                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1727                         };
1728                 };
1729
1730                 sdio0 {
1731                         sdio0_bus1: sdio0-bus1 {
1732                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1733                         };
1734
1735                         sdio0_bus4: sdio0-bus4 {
1736                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1737                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1738                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1739                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1740                         };
1741
1742                         sdio0_cmd: sdio0-cmd {
1743                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1744                         };
1745
1746                         sdio0_clk: sdio0-clk {
1747                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1748                         };
1749
1750                         sdio0_dectn: sdio0-dectn {
1751                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1752                         };
1753
1754                         sdio0_wrprt: sdio0-wrprt {
1755                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1756                         };
1757
1758                         sdio0_pwren: sdio0-pwren {
1759                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1760                         };
1761
1762                         sdio0_bkpwr: sdio0-bkpwr {
1763                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1764                         };
1765
1766                         sdio0_int: sdio0-int {
1767                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1768                         };
1769
1770                         sdio0_gpio: sdio0-gpio {
1771                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1772                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1773                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1774                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1775                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1776                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1777                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1778                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1779                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1780                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1781                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1782                         };
1783                 };
1784
1785                 emmc {
1786                         emmc_clk: emmc-clk {
1787                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1788                         };
1789
1790                         emmc_cmd: emmc-cmd {
1791                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1792                         };
1793
1794                         emmc_pwren: emmc-pwren {
1795                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1796                         };
1797
1798                         emmc_rstnout: emmc_rstnout {
1799                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1800                         };
1801
1802                         emmc_bus1: emmc-bus1 {
1803                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1804                         };
1805
1806                         emmc_bus4: emmc-bus4 {
1807                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1808                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1809                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1810                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1811                         };
1812                 };
1813
1814                 pwm0 {
1815                         pwm0_pin: pwm0-pin {
1816                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1817                         };
1818
1819                         vop_pwm_pin:vop-pwm {
1820                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1821                         };
1822                 };
1823
1824                 pwm1 {
1825                         pwm1_pin: pwm1-pin {
1826                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1827                         };
1828                 };
1829
1830                 pwm3 {
1831                         pwm3_pin: pwm3-pin {
1832                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 lcdc {
1837                         lcdc_lcdc: lcdc-lcdc {
1838                                 rockchip,pins =
1839                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1840                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1841                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1842                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1843                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1844                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1845                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1846                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1847                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1848                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1849                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1850                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1851                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1852                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1853                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1854                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1855                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1856                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1857                         };
1858
1859                         lcdc_gpio: lcdc-gpio {
1860                                 rockchip,pins =
1861                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1862                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1863                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1864                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1865                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1866                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1867                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1868                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1869                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1870                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1871                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1872                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1873                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1874                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1875                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1876                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1877                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1878                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1879                         };
1880                 };
1881
1882                 isp {
1883                         cif_clkout: cif-clkout {
1884                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1885                         };
1886
1887                         isp_dvp_d2d9: isp-dvp-d2d9 {
1888                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1889                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1890                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1891                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1892                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1893                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1894                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1895                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1896                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1897                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1898                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1899                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1900                         };
1901
1902                         isp_dvp_d0d1: isp-dvp-d0d1 {
1903                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1904                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1905                         };
1906
1907                         isp_dvp_d10d11:isp_d10d11       {
1908                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1909                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1910                         };
1911
1912                         isp_dvp_d0d7: isp-dvp-d0d7 {
1913                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1914                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1915                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1916                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1917                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1918                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1919                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1920                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1921                         };
1922
1923                         isp_shutter: isp-shutter {
1924                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1925                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1926                         };
1927
1928                         isp_flash_trigger: isp-flash-trigger {
1929                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1930                         };
1931
1932                         isp_prelight: isp-prelight {
1933                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1934                         };
1935
1936                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1937                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1938                         };
1939                 };
1940
1941                 gps {
1942                         gps_mag: gps-mag {
1943                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1944                         };
1945
1946                         gps_sig: gps-sig {
1947                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1948
1949                         };
1950
1951                         gps_rfclk: gps-rfclk {
1952                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1953                         };
1954                 };
1955
1956                 gmac {
1957                         rgmii_pins: rgmii-pins {
1958                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1959                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1960                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1961                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1962                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1963                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1964                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1965                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1966                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1967                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1968                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1969                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1970                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1971                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1972                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1973                         };
1974
1975                         rmii_pins: rmii-pins {
1976                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1977                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1978                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1979                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1980                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1981                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1982                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1983                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1984                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1985                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1986                         };
1987                 };
1988
1989                 tsadc_pin {
1990                         tsadc_int: tsadc-int {
1991                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1992                         };
1993                         tsadc_gpio: tsadc-gpio {
1994                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1995                         };
1996                 };
1997
1998                 hdmi_pin {
1999                         hdmi_cec: hdmi-cec {
2000                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2001                         };
2002                 };
2003
2004                 hdmi_i2c {
2005                         hdmii2c_xfer: hdmii2c-xfer {
2006                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2007                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2008                         };
2009                 };
2010
2011                 cpu_jtag {
2012                         cpu_jtag: cpu-jtag {
2013                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2014                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2015                         };
2016                 };
2017         };
2018
2019         reboot {
2020                 compatible = "rockchip,rk3368-reboot";
2021                 rockchip,cru = <&cru>;
2022                 rockchip,pmugrf = <&pmugrf>;
2023         };
2024 };