ARM64: dts: rk3399: add dmac node
authorSugar Zhang <sugar.zhang@rock-chips.com>
Thu, 14 Jan 2016 09:00:57 +0000 (17:00 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Fri, 15 Jan 2016 09:33:46 +0000 (17:33 +0800)
Change-Id: Ib59775c317f936c54d521d714293a3ab9a546937
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3399.dtsi

index 05764e5d2f4d389547af770c62daabe4be4defe3..2195d1106d8fe0525cf6596f5152b478d31abdb3 100644 (file)
                };
        };
 
                };
        };
 
+       amba {
+               compatible = "arm,amba-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               dmac_bus: dma-controller@ff6d0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x0 0xff6d0000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC_BUS>;
+                       clock-names = "apb_pclk";
+               };
+
+               dmac_peri: dma-controller@ff6e0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x0 0xff6e0000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC_PERI>;
+                       clock-names = "apb_pclk";
+               };
+       };
+
        uart0: serial@ff180000 {
                compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
                reg = <0x0 0xff180000 0x0 0x100>;
        uart0: serial@ff180000 {
                compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
                reg = <0x0 0xff180000 0x0 0x100>;