arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44
  45 / {
  46         compatible = "rockchip,rk3399";
  47         interrupt-parent = <&gic>;
  48         #address-cells = <2>;
  49         #size-cells = <2>;
  50
  51         aliases {
  52                 serial0 = &uart0;
  53                 serial1 = &uart1;
  54                 serial2 = &uart2;
  55                 serial3 = &uart3;
  56         };
  57
  58         psci {
  59                 compatible = "arm,psci";
  60                 method = "smc";
  61         };
  62
  63         cpus {
  64                 #address-cells = <2>;
  65                 #size-cells = <0>;
  66
  67                 cpu-map {
  68                         cluster0 {
  69                                 core0 {
  70                                         cpu = <&cpu_l0>;
  71                                 };
  72                                 core1 {
  73                                         cpu = <&cpu_l1>;
  74                                 };
  75                                 core2 {
  76                                         cpu = <&cpu_l2>;
  77                                 };
  78                                 core3 {
  79                                         cpu = <&cpu_l3>;
  80                                 };
  81                         };
  82
  83                         cluster1 {
  84                                 core0 {
  85                                         cpu = <&cpu_b0>;
  86                                 };
  87                                 core1 {
  88                                         cpu = <&cpu_b1>;
  89                                 };
  90                         };
  91                 };
  92
  93                 idle-states {
  94                         entry-method = "psci";
  95
  96                         cpu_sleep: cpu-sleep-0 {
  97                                 compatible = "arm,idle-state";
  98                         };
  99                 };
 100
 101                 cpu_l0: cpu@0 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         reg = <0x0 0x0>;
 105                         cpu-idle-states = <&cpu_sleep>;
 106                         enable-method = "psci";
 107                 };
 108
 109                 cpu_l1: cpu@1 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x1>;
 113                         cpu-idle-states = <&cpu_sleep>;
 114                         enable-method = "psci";
 115                 };
 116
 117                 cpu_l2: cpu@2 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a53", "arm,armv8";
 120                         reg = <0x0 0x2>;
 121                         cpu-idle-states = <&cpu_sleep>;
 122                         enable-method = "psci";
 123                 };
 124
 125                 cpu_l3: cpu@3 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53", "arm,armv8";
 128                         reg = <0x0 0x3>;
 129                         cpu-idle-states = <&cpu_sleep>;
 130                         enable-method = "psci";
 131                 };
 132
 133                 cpu_b0: cpu@100 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a72", "arm,armv8";
 136                         reg = <0x0 0x100>;
 137                         cpu-idle-states = <&cpu_sleep>;
 138                         enable-method = "psci";
 139                 };
 140
 141                 cpu_b1: cpu@101 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a72", "arm,armv8";
 144                         reg = <0x0 0x101>;
 145                         cpu-idle-states = <&cpu_sleep>;
 146                         enable-method = "psci";
 147                 };
 148         };
 149
 150         pmu {
 151                 compatible = "arm,armv8-pmuv3";
 152                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 153                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 154                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>;
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv8-timer";
 159                 interrupts =
 160                         <GIC_PPI 13
 161                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 162                         <GIC_PPI 14
 163                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 164                         <GIC_PPI 11
 165                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 166                         <GIC_PPI 10
 167                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 168                 clock-frequency = <24000000>;
 169         };
 170
 171         xin24m: xin24m {
 172                 compatible = "fixed-clock";
 173                 #clock-cells = <0>;
 174                 clock-frequency = <24000000>;
 175                 clock-output-names = "xin24m";
 176         };
 177
 178         gic: interrupt-controller@fee00000 {
 179                 compatible = "arm,gic-v3";
 180                 #interrupt-cells = <3>;
 181                 #address-cells = <2>;
 182                 #size-cells = <2>;
 183                 ranges;
 184                 interrupt-controller;
 185
 186                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 187                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 188                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 189                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 190                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 191                 interrupts =
 192                         <GIC_PPI 9
 193                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 194                 its: interrupt-controller@fee20000 {
 195                         compatible = "arm,gic-v3-its";
 196                         msi-controller;
 197                         reg = <0x0 0xfee20000 0x0 0x20000>;
 198                 };
 199         };
 200
 201         amba {
 202                 compatible = "arm,amba-bus";
 203                 #address-cells = <2>;
 204                 #size-cells = <2>;
 205                 ranges;
 206
 207                 dmac_bus: dma-controller@ff6d0000 {
 208                         compatible = "arm,pl330", "arm,primecell";
 209                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 210                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 212                         #dma-cells = <1>;
 213                         clocks = <&cru ACLK_DMAC_BUS>;
 214                         clock-names = "apb_pclk";
 215                 };
 216
 217                 dmac_peri: dma-controller@ff6e0000 {
 218                         compatible = "arm,pl330", "arm,primecell";
 219                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 220                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 222                         #dma-cells = <1>;
 223                         clocks = <&cru ACLK_DMAC_PERI>;
 224                         clock-names = "apb_pclk";
 225                 };
 226         };
 227
 228         uart0: serial@ff180000 {
 229                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 230                 reg = <0x0 0xff180000 0x0 0x100>;
 231                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 232                 clock-names = "baudclk", "apb_pclk";
 233                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 234                 reg-shift = <2>;
 235                 reg-io-width = <4>;
 236                 status = "disabled";
 237         };
 238
 239         uart1: serial@ff190000 {
 240                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 241                 reg = <0x0 0xff190000 0x0 0x100>;
 242                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 243                 clock-names = "baudclk", "apb_pclk";
 244                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 245                 reg-shift = <2>;
 246                 reg-io-width = <4>;
 247                 status = "disabled";
 248         };
 249
 250         uart2: serial@ff1a0000 {
 251                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 252                 reg = <0x0 0xff1a0000 0x0 0x100>;
 253                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 254                 clock-names = "baudclk", "apb_pclk";
 255                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 256                 reg-shift = <2>;
 257                 reg-io-width = <4>;
 258                 status = "disabled";
 259         };
 260
 261         uart3: serial@ff1b0000 {
 262                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 263                 reg = <0x0 0xff1b0000 0x0 0x100>;
 264                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART4>;
 265                 clock-names = "baudclk", "apb_pclk";
 266                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 267                 reg-shift = <2>;
 268                 reg-io-width = <4>;
 269                 status = "disabled";
 270         };
 271
 272         uart4: serial@ff370000 {
 273                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 274                 reg = <0x0 0xff370000 0x0 0x100>;
 275                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 276                 clock-names = "baudclk", "apb_pclk";
 277                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 278                 reg-shift = <2>;
 279                 reg-io-width = <4>;
 280                 status = "disabled";
 281         };
 282
 283         cru_pmu: pmu-clock-controller@ff750000 {
 284                 compatible = "rockchip,rk3399-pmu-cru";
 285                 reg = <0x0 0xff750000 0x0 0x1000>;
 286                 #clock-cells = <1>;
 287                 #reset-cells = <1>;
 288         };
 289
 290         cru: clock-controller@ff760000 {
 291                 compatible = "rockchip,rk3399-cru";
 292                 reg = <0x0 0xff760000 0x0 0x1000>;
 293                 rockchip,grf = <&grf>;
 294                 #clock-cells = <1>;
 295                 #reset-cells = <1>;
 296         };
 297
 298         grf: syscon@ff770000 {
 299                 compatible = "rockchip,rk3399-grf", "syscon";
 300                 reg = <0x0 0xff770000 0x0 0x10000>;
 301         };
 302 };