/*
 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "rockchip,rk3399";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu_l0>;
				};
				core1 {
					cpu = <&cpu_l1>;
				};
				core2 {
					cpu = <&cpu_l2>;
				};
				core3 {
					cpu = <&cpu_l3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu_b0>;
				};
				core1 {
					cpu = <&cpu_b1>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			cpu_sleep: cpu-sleep-0 {
				compatible = "arm,idle-state";
			};
		};

		cpu_l0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x0>;
			cpu-idle-states = <&cpu_sleep>;
			enable-method = "psci";
		};

		cpu_l1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x1>;
			cpu-idle-states = <&cpu_sleep>;
			enable-method = "psci";
		};

		cpu_l2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x2>;
			cpu-idle-states = <&cpu_sleep>;
			enable-method = "psci";
		};

		cpu_l3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x3>;
			cpu-idle-states = <&cpu_sleep>;
			enable-method = "psci";
		};

		cpu_b0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x100>;
			cpu-idle-states = <&cpu_sleep>;
			enable-method = "psci";
		};

		cpu_b1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x101>;
			cpu-idle-states = <&cpu_sleep>;
			enable-method = "psci";
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
		interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
				     <&cpu_l3>, <&cpu_b0>, <&cpu_b1>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts =
			<GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			<GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			<GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			<GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	xin24m: xin24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
	};

	gic: interrupt-controller@fee00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;

		reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
		      <0x0 0xfef00000 0 0xc0000>, /* GICR */
		      <0x0 0xfff00000 0 0x10000>, /* GICC */
		      <0x0 0xfff10000 0 0x10000>, /* GICH */
		      <0x0 0xfff20000 0 0x10000>; /* GICV */
		interrupts =
			<GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		its: interrupt-controller@fee20000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0xfee20000 0x0 0x20000>;
		};
	};

	amba {
		compatible = "arm,amba-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dmac_bus: dma-controller@ff6d0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x0 0xff6d0000 0x0 0x4000>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMAC_BUS>;
			clock-names = "apb_pclk";
		};

		dmac_peri: dma-controller@ff6e0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x0 0xff6e0000 0x0 0x4000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMAC_PERI>;
			clock-names = "apb_pclk";
		};
	};

	uart0: serial@ff180000 {
		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff180000 0x0 0x100>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart1: serial@ff190000 {
		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff190000 0x0 0x100>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart2: serial@ff1a0000 {
		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff1a0000 0x0 0x100>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart3: serial@ff1b0000 {
		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff1b0000 0x0 0x100>;
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart4: serial@ff370000 {
		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff370000 0x0 0x100>;
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	cru_pmu: pmu-clock-controller@ff750000 {
		compatible = "rockchip,rk3399-pmu-cru";
		reg = <0x0 0xff750000 0x0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cru: clock-controller@ff760000 {
		compatible = "rockchip,rk3399-cru";
		reg = <0x0 0xff760000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	grf: syscon@ff770000 {
		compatible = "rockchip,rk3399-grf", "syscon";
		reg = <0x0 0xff770000 0x0 0x10000>;
	};
};