clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
authorXing Zheng <zhengxing@rock-chips.com>
Wed, 27 Jul 2016 02:50:12 +0000 (10:50 +0800)
committerFrank Wang <frank.wang@rock-chips.com>
Wed, 27 Jul 2016 08:52:10 +0000 (16:52 +0800)
Change-Id: Icd566864d3651e7b64ee8209b66e8a326011422f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c
include/dt-bindings/clock/rk3399-cru.h

index 0ee8de6..4e39e42 100644 (file)
@@ -429,9 +429,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(6), 6, GFLAGS),
 
-       GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+       GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(13), 12, GFLAGS),
-       GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+       GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(13), 12, GFLAGS),
        MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
                        RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
index 2290123..a5ff9f9 100644 (file)
 #define SCLK_DPHY_RX0_CFG              165
 #define SCLK_RMII_SRC                  166
 #define SCLK_PCIEPHY_REF100M           167
+#define SCLK_USBPHY0_480M_SRC          168
+#define SCLK_USBPHY1_480M_SRC          169
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181