drm/rockchip: vop: rk3399: add area plane

Change-Id: Ia6f77353363e25423ac29129372bc510565682f8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 7576e88525a921b45ebe3099ef56c23a7b4bc972..1b8ec6637328f197835daeb22f3c85321d337f9f 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -280,12 +280,79 @@ static const struct vop_reg_data rk3399_init_reg_table[] = {
        {RK3399_DSP_CTRL0, 0x00000000},
        {RK3399_WIN0_CTRL0, 0x00000080},
        {RK3399_WIN1_CTRL0, 0x00000080},
        {RK3399_DSP_CTRL0, 0x00000000},
        {RK3399_WIN0_CTRL0, 0x00000080},
        {RK3399_WIN1_CTRL0, 0x00000080},

-       /* TODO: Win2/3 support multiple area function, but we haven't found
-        * a suitable way to use it yet, so let's just use them as other windows
-        * with only area 0 enabled.
+       /*
+        * Bit[0] is win2/3 gate en bit, there is no power consume with this
+        * bit enable. the bit's function similar with area plane enable bit,
+        * So default enable this bit, then We can control win2/3 area plane
+        * with its enable bit.

         */
         */

-       {RK3399_WIN2_CTRL0, 0x00000010},
-       {RK3399_WIN3_CTRL0, 0x00000010},
+       {RK3399_WIN2_CTRL0, 0x00000001},
+       {RK3399_WIN3_CTRL0, 0x00000001},
+};
+
+static const struct vop_win_phy rk3399_win23_data = {
+       .data_formats = formats_win_lite,
+       .nformats = ARRAY_SIZE(formats_win_lite),
+       .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 4),
+       .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 5),
+       .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 20),
+       .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO0, 0x0fff0fff, 0),
+       .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST0, 0x1fff1fff, 0),
+       .yrgb_mst = VOP_REG(RK3399_WIN2_MST0, 0xffffffff, 0),
+       .yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 0),
+       .src_alpha_ctl = VOP_REG(RK3399_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
+       .dst_alpha_ctl = VOP_REG(RK3399_WIN2_DST_ALPHA_CTRL, 0xff, 0),
+};
+
+static const struct vop_win_phy rk3399_area1_data = {
+       .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 8),
+       .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 9),
+       .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 23),
+       .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO1, 0x0fff0fff, 0),
+       .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST1, 0x1fff1fff, 0),
+       .yrgb_mst = VOP_REG(RK3399_WIN2_MST1, 0xffffffff, 0),
+       .yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 16),
+};
+
+static const struct vop_win_phy rk3399_area2_data = {
+       .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 12),
+       .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 13),
+       .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 26),
+       .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO2, 0x0fff0fff, 0),
+       .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST2, 0x1fff1fff, 0),
+       .yrgb_mst = VOP_REG(RK3399_WIN2_MST2, 0xffffffff, 0),
+       .yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 0),
+};
+
+static const struct vop_win_phy rk3399_area3_data = {
+       .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 16),
+       .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 17),
+       .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 29),
+       .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO3, 0x0fff0fff, 0),
+       .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST3, 0x1fff1fff, 0),
+       .yrgb_mst = VOP_REG(RK3399_WIN2_MST3, 0xffffffff, 0),
+       .yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 16),
+};
+
+static const struct vop_win_phy *rk3399_area_data[] = {
+       &rk3399_area1_data,
+       &rk3399_area2_data,
+       &rk3399_area3_data
+};
+
+static const struct vop_win_data rk3399_vop_win_data[] = {
+       { .base = 0x00, .phy = &rk3288_win01_data,
+         .type = DRM_PLANE_TYPE_PRIMARY },
+       { .base = 0x40, .phy = &rk3288_win01_data,
+         .type = DRM_PLANE_TYPE_OVERLAY },
+       { .base = 0x00, .phy = &rk3399_win23_data,
+         .type = DRM_PLANE_TYPE_OVERLAY,
+         .area = rk3399_area_data,
+         .area_size = ARRAY_SIZE(rk3399_area_data), },
+       { .base = 0x50, .phy = &rk3399_win23_data,
+         .type = DRM_PLANE_TYPE_CURSOR,
+         .area = rk3399_area_data,
+         .area_size = ARRAY_SIZE(rk3399_area_data), },

 };
 
 static const struct vop_data rk3399_vop_big = {
 };
 
 static const struct vop_data rk3399_vop_big = {


@@ -296,8 +363,8 @@ static const struct vop_data rk3399_vop_big = {
        /*
         * rk3399 vop big windows register layout is same as rk3288.
         */
        /*
         * rk3399 vop big windows register layout is same as rk3288.
         */

-       .win = rk3288_vop_win_data,
-       .win_size = ARRAY_SIZE(rk3288_vop_win_data),
+       .win = rk3399_vop_win_data,
+       .win_size = ARRAY_SIZE(rk3399_vop_win_data),

 };
 
 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 };
 
 static const struct vop_win_data rk3399_vop_lit_win_data[] = {