drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG(off, _mask, s) \
  24                 {.offset = off, \
  25                  .mask = _mask, \
  26                  .shift = s, \
  27                  .write_mask = false,}
  28
  29 #define VOP_REG_MASK(off, _mask, s) \
  30                 {.offset = off, \
  31                  .mask = _mask, \
  32                  .shift = s, \
  33                  .write_mask = true,}
  34
  35 static const uint32_t formats_win_full[] = {
  36         DRM_FORMAT_XRGB8888,
  37         DRM_FORMAT_ARGB8888,
  38         DRM_FORMAT_XBGR8888,
  39         DRM_FORMAT_ABGR8888,
  40         DRM_FORMAT_RGB888,
  41         DRM_FORMAT_BGR888,
  42         DRM_FORMAT_RGB565,
  43         DRM_FORMAT_BGR565,
  44         DRM_FORMAT_NV12,
  45         DRM_FORMAT_NV16,
  46         DRM_FORMAT_NV24,
  47 };
  48
  49 static const uint32_t formats_win_lite[] = {
  50         DRM_FORMAT_XRGB8888,
  51         DRM_FORMAT_ARGB8888,
  52         DRM_FORMAT_XBGR8888,
  53         DRM_FORMAT_ABGR8888,
  54         DRM_FORMAT_RGB888,
  55         DRM_FORMAT_BGR888,
  56         DRM_FORMAT_RGB565,
  57         DRM_FORMAT_BGR565,
  58 };
  59
  60 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  61         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  62         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  63         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  64         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  65         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  66         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  67         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  68         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  69         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  70         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  71         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  72         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  73         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  74         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  75         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  76         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  77         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  78         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  79         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  80         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  81         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  82 };
  83
  84 static const struct vop_scl_regs rk3288_win_full_scl = {
  85         .ext = &rk3288_win_full_scl_ext,
  86         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  87         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
  88         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
  89         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
  90 };
  91
  92 static const struct vop_win_phy rk3288_win01_data = {
  93         .scl = &rk3288_win_full_scl,
  94         .data_formats = formats_win_full,
  95         .nformats = ARRAY_SIZE(formats_win_full),
  96         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
  97         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
  98         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
  99         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 100         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 101         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 102         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 103         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 104         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 105         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 106         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 107         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
 108 };
 109
 110 static const struct vop_win_phy rk3288_win23_data = {
 111         .data_formats = formats_win_lite,
 112         .nformats = ARRAY_SIZE(formats_win_lite),
 113         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 114         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 115         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 116         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 117         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 118         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 119         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 120         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 121         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 122 };
 123
 124 static const struct vop_win_phy rk3288_area1_data = {
 125         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 126         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 127         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 128         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 129         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 130 };
 131
 132 static const struct vop_win_phy rk3288_area2_data = {
 133         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 134         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 135         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 136         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 137         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 138 };
 139
 140 static const struct vop_win_phy rk3288_area3_data = {
 141         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 142         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 143         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 144         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 145         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 146 };
 147
 148 static const struct vop_win_phy *rk3288_area_data[] = {
 149         &rk3288_area1_data,
 150         &rk3288_area2_data,
 151         &rk3288_area3_data
 152 };
 153
 154 static const struct vop_ctrl rk3288_ctrl_data = {
 155         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 156         .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 157         .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
 158         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 159         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 160         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 161         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 162         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 163         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 164         .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
 165         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 166         .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
 167         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 168         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 169         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 170         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 171         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 172         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 173         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 174 };
 175
 176 static const struct vop_reg_data rk3288_init_reg_table[] = {
 177         {RK3288_SYS_CTRL, 0x00c00000},
 178         {RK3288_DSP_CTRL0, 0x00000000},
 179         {RK3288_WIN0_CTRL0, 0x00000080},
 180         {RK3288_WIN1_CTRL0, 0x00000080},
 181         /*
 182          * Bit[0] is win2/3 gate en bit, there is no power consume with this
 183          * bit enable. the bit's function similar with area plane enable bit,
 184          * So default enable this bit, then We can control win2/3 area plane
 185          * with its enable bit.
 186          */
 187         {RK3288_WIN2_CTRL0, 0x00000001},
 188         {RK3288_WIN3_CTRL0, 0x00000001},
 189 };
 190
 191 /*
 192  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 193  * special support to get alpha blending working.  For now, just use overlay
 194  * window 3 for the drm cursor.
 195  *
 196  */
 197 static const struct vop_win_data rk3288_vop_win_data[] = {
 198         { .base = 0x00, .phy = &rk3288_win01_data,
 199           .type = DRM_PLANE_TYPE_PRIMARY },
 200         { .base = 0x40, .phy = &rk3288_win01_data,
 201           .type = DRM_PLANE_TYPE_OVERLAY },
 202         { .base = 0x00, .phy = &rk3288_win23_data,
 203           .type = DRM_PLANE_TYPE_OVERLAY,
 204           .area = rk3288_area_data,
 205           .area_size = ARRAY_SIZE(rk3288_area_data), },
 206         { .base = 0x50, .phy = &rk3288_win23_data,
 207           .type = DRM_PLANE_TYPE_CURSOR,
 208           .area = rk3288_area_data,
 209           .area_size = ARRAY_SIZE(rk3288_area_data), },
 210 };
 211
 212 static const int rk3288_vop_intrs[] = {
 213         DSP_HOLD_VALID_INTR,
 214         FS_INTR,
 215         LINE_FLAG_INTR,
 216         BUS_ERROR_INTR,
 217 };
 218
 219 static const struct vop_intr rk3288_vop_intr = {
 220         .intrs = rk3288_vop_intrs,
 221         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 222         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 223         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 224         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 225 };
 226
 227 static const struct vop_data rk3288_vop = {
 228         .init_table = rk3288_init_reg_table,
 229         .table_size = ARRAY_SIZE(rk3288_init_reg_table),
 230         .intr = &rk3288_vop_intr,
 231         .ctrl = &rk3288_ctrl_data,
 232         .win = rk3288_vop_win_data,
 233         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 234 };
 235
 236 static const struct vop_ctrl rk3399_ctrl_data = {
 237         .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
 238         .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
 239         .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
 240         .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
 241         .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
 242         .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
 243         .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
 244         .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
 245         .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
 246         .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
 247         .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
 248         .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
 249         .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
 250         .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
 251         .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 252         .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
 253         .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 254         .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
 255         .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 256         .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 257         .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
 258 };
 259
 260 static const int rk3399_vop_intrs[] = {
 261         FS_INTR,
 262         0, 0,
 263         LINE_FLAG_INTR,
 264         0,
 265         BUS_ERROR_INTR,
 266         0, 0, 0, 0, 0, 0, 0,
 267         DSP_HOLD_VALID_INTR,
 268 };
 269
 270 static const struct vop_intr rk3399_vop_intr = {
 271         .intrs = rk3399_vop_intrs,
 272         .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
 273         .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
 274         .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
 275         .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
 276 };
 277
 278 static const struct vop_reg_data rk3399_init_reg_table[] = {
 279         {RK3399_SYS_CTRL, 0x2000f800},
 280         {RK3399_DSP_CTRL0, 0x00000000},
 281         {RK3399_WIN0_CTRL0, 0x00000080},
 282         {RK3399_WIN1_CTRL0, 0x00000080},
 283         /* TODO: Win2/3 support multiple area function, but we haven't found
 284          * a suitable way to use it yet, so let's just use them as other windows
 285          * with only area 0 enabled.
 286          */
 287         {RK3399_WIN2_CTRL0, 0x00000010},
 288         {RK3399_WIN3_CTRL0, 0x00000010},
 289 };
 290
 291 static const struct vop_data rk3399_vop_big = {
 292         .init_table = rk3399_init_reg_table,
 293         .table_size = ARRAY_SIZE(rk3399_init_reg_table),
 294         .intr = &rk3399_vop_intr,
 295         .ctrl = &rk3399_ctrl_data,
 296         /*
 297          * rk3399 vop big windows register layout is same as rk3288.
 298          */
 299         .win = rk3288_vop_win_data,
 300         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 301 };
 302
 303 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 304         { .base = 0x00, .phy = &rk3288_win01_data,
 305           .type = DRM_PLANE_TYPE_PRIMARY },
 306         { .base = 0x00, .phy = &rk3288_win23_data,
 307           .type = DRM_PLANE_TYPE_CURSOR},
 308 };
 309
 310
 311 static const struct vop_data rk3399_vop_lit = {
 312         .init_table = rk3399_init_reg_table,
 313         .table_size = ARRAY_SIZE(rk3399_init_reg_table),
 314         .intr = &rk3399_vop_intr,
 315         .ctrl = &rk3399_ctrl_data,
 316         /*
 317          * rk3399 vop lit windows register layout is same as rk3288,
 318          * but cut off the win1 and win3 windows.
 319          */
 320         .win = rk3399_vop_lit_win_data,
 321         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 322 };
 323
 324 static const struct vop_scl_regs rk3066_win_scl = {
 325         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 326         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 327         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 328         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 329 };
 330
 331 static const struct vop_win_phy rk3036_win0_data = {
 332         .scl = &rk3066_win_scl,
 333         .data_formats = formats_win_full,
 334         .nformats = ARRAY_SIZE(formats_win_full),
 335         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 336         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 337         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 338         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 339         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 340         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 341         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 342         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 343         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 344 };
 345
 346 static const struct vop_win_phy rk3036_win1_data = {
 347         .data_formats = formats_win_lite,
 348         .nformats = ARRAY_SIZE(formats_win_lite),
 349         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 350         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 351         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 352         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 353         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 354         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 355         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 356         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 357 };
 358
 359 static const struct vop_win_data rk3036_vop_win_data[] = {
 360         { .base = 0x00, .phy = &rk3036_win0_data,
 361           .type = DRM_PLANE_TYPE_PRIMARY },
 362         { .base = 0x00, .phy = &rk3036_win1_data,
 363           .type = DRM_PLANE_TYPE_CURSOR },
 364 };
 365
 366 static const int rk3036_vop_intrs[] = {
 367         DSP_HOLD_VALID_INTR,
 368         FS_INTR,
 369         LINE_FLAG_INTR,
 370         BUS_ERROR_INTR,
 371 };
 372
 373 static const struct vop_intr rk3036_intr = {
 374         .intrs = rk3036_vop_intrs,
 375         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 376         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 377         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 378         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 379 };
 380
 381 static const struct vop_ctrl rk3036_ctrl_data = {
 382         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 383         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 384         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 385         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 386         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 387         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 388         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 389         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 390 };
 391
 392 static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
 393         {RK3036_DSP_CTRL1, 0x00000000},
 394 };
 395
 396 static const struct vop_data rk3036_vop = {
 397         .init_table = rk3036_vop_init_reg_table,
 398         .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
 399         .ctrl = &rk3036_ctrl_data,
 400         .intr = &rk3036_intr,
 401         .win = rk3036_vop_win_data,
 402         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 403 };
 404
 405 static const struct of_device_id vop_driver_dt_match[] = {
 406         { .compatible = "rockchip,rk3288-vop",
 407           .data = &rk3288_vop },
 408         { .compatible = "rockchip,rk3036-vop",
 409           .data = &rk3036_vop },
 410         { .compatible = "rockchip,rk3399-vop-big",
 411           .data = &rk3399_vop_big },
 412         { .compatible = "rockchip,rk3399-vop-lit",
 413           .data = &rk3399_vop_lit },
 414         {},
 415 };
 416 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 417
 418 static int vop_probe(struct platform_device *pdev)
 419 {
 420         struct device *dev = &pdev->dev;
 421
 422         if (!dev->of_node) {
 423                 dev_err(dev, "can't find vop devices\n");
 424                 return -ENODEV;
 425         }
 426
 427         return component_add(dev, &vop_component_ops);
 428 }
 429
 430 static int vop_remove(struct platform_device *pdev)
 431 {
 432         component_del(&pdev->dev, &vop_component_ops);
 433
 434         return 0;
 435 }
 436
 437 struct platform_driver vop_platform_driver = {
 438         .probe = vop_probe,
 439         .remove = vop_remove,
 440         .driver = {
 441                 .name = "rockchip-vop",
 442                 .owner = THIS_MODULE,
 443                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 444         },
 445 };
 446
 447 module_platform_driver(vop_platform_driver);
 448
 449 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 450 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 451 MODULE_LICENSE("GPL v2");