arm64: dts: rockchip: rk3368: xin32k use the fixed clk
authorElaine Zhang <zhangqing@rock-chips.com>
Tue, 21 Mar 2017 07:09:17 +0000 (15:09 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Tue, 21 Mar 2017 08:09:43 +0000 (16:09 +0800)
If xin32k use the rk808_clkout1, rk808 init is too late,
xin32k enable count and prepare count is not match with it's child clk.

Change-Id: I314776c5024fdf3373619968582497e0e2d5666f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
arch/arm64/boot/dts/rockchip/rk3368-p9.dts
arch/arm64/boot/dts/rockchip/rk3368-sheep.dts
arch/arm64/boot/dts/rockchip/rk3368.dtsi

index 46cdddfcea6c43ad30518d359babe7e094b943ac..a66179ad0ffb8953629d9df5ec0ceabfa7e1cdcb 100644 (file)
                vcc10-supply = <&vcc_sys>;
                vcc11-supply = <&vcc_sys>;
                vcc12-supply = <&vcc_io>;
-               clock-output-names = "xin32k", "rk808-clkout2";
+               clock-output-names = "rk808-clkout1", "rk808-clkout2";
                #clock-cells = <1>;
 
                regulators {
index d7ee5dd6f217689930444a24ac45fed78aa96569..855a579c870c374af05384484d952905580b7de6 100644 (file)
                compatible = "rockchip,rk818";
                status = "okay";
                reg = <0x1c>;
-               clock-output-names = "xin32k", "wifibt_32kin";
+               clock-output-names = "rk808-clkout1", "wifibt_32kin";
                interrupt-parent = <&gpio0>;
                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
                pinctrl-names = "default";
index 0b8134ffe42af1d4dd14da734fe9df8941a16e97..c9f7391783411ca63ea537b43a8fd410bf62e09d 100644 (file)
                reg = <0x1c>;
                status = "okay";
 
-               clock-output-names = "xin32k", "wifibt_32kin";
+               clock-output-names = "rk808-clkout1", "wifibt_32kin";
                interrupt-parent = <&gpio0>;
                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
                pinctrl-names = "default";
index 4845d82b80e36d4bc31190391db50a157c34c7ed..1c3eae584871268ab43332b2cb0565f3967dba1c 100644 (file)
                #clock-cells = <0>;
        };
 
+       xin32k: xin32k {
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+               clock-output-names = "xin32k";
+               #clock-cells = <0>;
+       };
+
        sdmmc: rksdmmc@ff0c0000 {
                compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff0c0000 0x0 0x4000>;