arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135
 136                         #cooling-cells = <2>; /* min followed by max */
 137                 };
 138
 139                 cpu_l1: cpu@1 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x1>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         operating-points-v2 = <&cluster0_opp>;
 147                 };
 148
 149                 cpu_l2: cpu@2 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a53", "arm,armv8";
 152                         reg = <0x0 0x2>;
 153                         cpu-idle-states = <&cpu_sleep>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         operating-points-v2 = <&cluster0_opp>;
 157                 };
 158
 159                 cpu_l3: cpu@3 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a53", "arm,armv8";
 162                         reg = <0x0 0x3>;
 163                         cpu-idle-states = <&cpu_sleep>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKL>;
 166                         operating-points-v2 = <&cluster0_opp>;
 167                 };
 168
 169                 cpu_b0: cpu@100 {
 170                         device_type = "cpu";
 171                         compatible = "arm,cortex-a53", "arm,armv8";
 172                         reg = <0x0 0x100>;
 173                         cpu-idle-states = <&cpu_sleep>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         operating-points-v2 = <&cluster1_opp>;
 177
 178                         #cooling-cells = <2>; /* min followed by max */
 179                 };
 180
 181                 cpu_b1: cpu@101 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a53", "arm,armv8";
 184                         reg = <0x0 0x101>;
 185                         cpu-idle-states = <&cpu_sleep>;
 186                         enable-method = "psci";
 187                         clocks = <&cru ARMCLKB>;
 188                         operating-points-v2 = <&cluster1_opp>;
 189                 };
 190
 191                 cpu_b2: cpu@102 {
 192                         device_type = "cpu";
 193                         compatible = "arm,cortex-a53", "arm,armv8";
 194                         reg = <0x0 0x102>;
 195                         cpu-idle-states = <&cpu_sleep>;
 196                         enable-method = "psci";
 197                         clocks = <&cru ARMCLKB>;
 198                         operating-points-v2 = <&cluster1_opp>;
 199                 };
 200
 201                 cpu_b3: cpu@103 {
 202                         device_type = "cpu";
 203                         compatible = "arm,cortex-a53", "arm,armv8";
 204                         reg = <0x0 0x103>;
 205                         cpu-idle-states = <&cpu_sleep>;
 206                         enable-method = "psci";
 207                         clocks = <&cru ARMCLKB>;
 208                         operating-points-v2 = <&cluster1_opp>;
 209                 };
 210         };
 211
 212         cluster0_opp: opp_table0 {
 213                 compatible = "operating-points-v2";
 214                 opp-shared;
 215
 216                 opp@216000000 {
 217                         opp-hz = /bits/ 64 <216000000>;
 218                         opp-microvolt = <950000 950000 1350000>;
 219                         clock-latency-ns = <40000>;
 220                         opp-suspend;
 221                 };
 222                 opp@408000000 {
 223                         opp-hz = /bits/ 64 <408000000>;
 224                         opp-microvolt = <950000 950000 1350000>;
 225                         clock-latency-ns = <40000>;
 226                 };
 227                 opp@600000000 {
 228                         opp-hz = /bits/ 64 <600000000>;
 229                         opp-microvolt = <950000 950000 1350000>;
 230                         clock-latency-ns = <40000>;
 231                 };
 232                 opp@816000000 {
 233                         opp-hz = /bits/ 64 <816000000>;
 234                         opp-microvolt = <1025000 1025000 1350000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@1008000000 {
 238                         opp-hz = /bits/ 64 <1008000000>;
 239                         opp-microvolt = <1125000 1125000 1350000>;
 240                         clock-latency-ns = <40000>;
 241                 };
 242                 opp@1200000000 {
 243                         opp-hz = /bits/ 64 <1200000000>;
 244                         opp-microvolt = <1225000 1225000 1350000>;
 245                         clock-latency-ns = <40000>;
 246                 };
 247         };
 248
 249         cluster1_opp: opp_table1 {
 250                 compatible = "operating-points-v2";
 251                 opp-shared;
 252
 253                 opp@216000000 {
 254                         opp-hz = /bits/ 64 <216000000>;
 255                         opp-microvolt = <950000 950000 1350000>;
 256                         clock-latency-ns = <40000>;
 257                         opp-suspend;
 258                 };
 259                 opp@408000000 {
 260                         opp-hz = /bits/ 64 <408000000>;
 261                         opp-microvolt = <950000 950000 1350000>;
 262                         clock-latency-ns = <40000>;
 263                 };
 264                 opp@600000000 {
 265                         opp-hz = /bits/ 64 <600000000>;
 266                         opp-microvolt = <950000 950000 1350000>;
 267                         clock-latency-ns = <40000>;
 268                 };
 269                 opp@816000000 {
 270                         opp-hz = /bits/ 64 <816000000>;
 271                         opp-microvolt = <975000 975000 1350000>;
 272                         clock-latency-ns = <40000>;
 273                 };
 274                 opp@1008000000 {
 275                         opp-hz = /bits/ 64 <1008000000>;
 276                         opp-microvolt = <1050000 1050000 1350000>;
 277                         clock-latency-ns = <40000>;
 278                 };
 279                 opp@1200000000 {
 280                         opp-hz = /bits/ 64 <1200000000>;
 281                         opp-microvolt = <1150000 1150000 1350000>;
 282                         clock-latency-ns = <40000>;
 283                 };
 284                 opp@1296000000 {
 285                         opp-hz = /bits/ 64 <1296000000>;
 286                         opp-microvolt = <1225000 1225000 1350000>;
 287                         clock-latency-ns = <40000>;
 288                 };
 289                 opp@1416000000 {
 290                         opp-hz = /bits/ 64 <1416000000>;
 291                         opp-microvolt = <1300000 1300000 1350000>;
 292                         clock-latency-ns = <40000>;
 293                 };
 294                 opp@1512000000 {
 295                         opp-hz = /bits/ 64 <1512000000>;
 296                         opp-microvolt = <1350000 1350000 1350000>;
 297                         clock-latency-ns = <40000>;
 298                 };
 299         };
 300
 301         cpu_avs: cpu-avs {
 302                 cluster0-avs {
 303                         cluster-id = <0>;
 304                         min-volt = <950000>; /* uV */
 305                         min-freq = <216000>; /* KHz */
 306                         leakage-adjust-volt = <
 307                         /*  mA        mA         uV */
 308                             0         254        0
 309                         >;
 310                         nvmem-cells = <&cpu_leakage>;
 311                         nvmem-cell-names = "cpu_leakage";
 312                 };
 313                 cluster1-avs {
 314                         cluster-id = <1>;
 315                         min-volt = <950000>; /* uV */
 316                         min-freq = <216000>; /* KHz */
 317                         leakage-adjust-volt = <
 318                         /*  mA        mA         uV */
 319                             0         254        0
 320                         >;
 321                         nvmem-cells = <&cpu_leakage>;
 322                         nvmem-cell-names = "cpu_leakage";
 323                 };
 324         };
 325
 326         arm-pmu {
 327                 compatible = "arm,armv8-pmuv3";
 328                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 336                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 337                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 338                                      <&cpu_b2>, <&cpu_b3>;
 339         };
 340
 341         amba {
 342                 compatible = "arm,amba-bus";
 343                 #address-cells = <2>;
 344                 #size-cells = <2>;
 345                 ranges;
 346
 347                 dmac_peri: dma-controller@ff250000 {
 348                         compatible = "arm,pl330", "arm,primecell";
 349                         reg = <0x0 0xff250000 0x0 0x4000>;
 350                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 352                         #dma-cells = <1>;
 353                         clocks = <&cru ACLK_DMAC_PERI>;
 354                         clock-names = "apb_pclk";
 355                         arm,pl330-broken-no-flushp;
 356                         peripherals-req-type-burst;
 357                 };
 358
 359                 dmac_bus: dma-controller@ff600000 {
 360                         compatible = "arm,pl330", "arm,primecell";
 361                         reg = <0x0 0xff600000 0x0 0x4000>;
 362                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 364                         #dma-cells = <1>;
 365                         clocks = <&cru ACLK_DMAC_BUS>;
 366                         clock-names = "apb_pclk";
 367                         arm,pl330-broken-no-flushp;
 368                         peripherals-req-type-burst;
 369                 };
 370         };
 371
 372         psci {
 373                 compatible = "arm,psci-0.2";
 374                 method = "smc";
 375         };
 376
 377         timer {
 378                 compatible = "arm,armv8-timer";
 379                 interrupts = <GIC_PPI 13
 380                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 381                              <GIC_PPI 14
 382                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 383                              <GIC_PPI 11
 384                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 385                              <GIC_PPI 10
 386                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 387         };
 388
 389         xin24m: oscillator {
 390                 compatible = "fixed-clock";
 391                 clock-frequency = <24000000>;
 392                 clock-output-names = "xin24m";
 393                 #clock-cells = <0>;
 394         };
 395
 396         xin32k: xin32k {
 397                 compatible = "fixed-clock";
 398                 clock-frequency = <32768>;
 399                 clock-output-names = "xin32k";
 400                 #clock-cells = <0>;
 401         };
 402
 403         sdmmc: rksdmmc@ff0c0000 {
 404                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 405                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 406                 clock-freq-min-max = <400000 150000000>;
 407                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 408                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 409                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 410                 fifo-depth = <0x100>;
 411                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 412                 status = "disabled";
 413         };
 414
 415         sdio0: dwmmc@ff0d0000 {
 416                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 417                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 418                 clock-freq-min-max = <400000 150000000>;
 419                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 420                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 421                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 422                 fifo-depth = <0x100>;
 423                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 424                 status = "disabled";
 425         };
 426
 427         emmc: rksdmmc@ff0f0000 {
 428                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 429                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 430                 clock-freq-min-max = <400000 150000000>;
 431                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 432                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 433                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 434                 fifo-depth = <0x100>;
 435                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 436                 status = "disabled";
 437         };
 438
 439         saradc: saradc@ff100000 {
 440                 compatible = "rockchip,saradc";
 441                 reg = <0x0 0xff100000 0x0 0x100>;
 442                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 443                 #io-channel-cells = <1>;
 444                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 445                 clock-names = "saradc", "apb_pclk";
 446                 resets = <&cru SRST_SARADC>;
 447                 reset-names = "saradc-apb";
 448                 status = "disabled";
 449         };
 450
 451         spi0: spi@ff110000 {
 452                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 453                 reg = <0x0 0xff110000 0x0 0x1000>;
 454                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 455                 clock-names = "spiclk", "apb_pclk";
 456                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 status = "disabled";
 462         };
 463
 464         spi1: spi@ff120000 {
 465                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 466                 reg = <0x0 0xff120000 0x0 0x1000>;
 467                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 468                 clock-names = "spiclk", "apb_pclk";
 469                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 status = "disabled";
 475         };
 476
 477         spi2: spi@ff130000 {
 478                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 479                 reg = <0x0 0xff130000 0x0 0x1000>;
 480                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 481                 clock-names = "spiclk", "apb_pclk";
 482                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 status = "disabled";
 488         };
 489
 490         i2c0: i2c@ff650000 {
 491                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 492                 reg = <0x0 0xff650000 0x0 0x1000>;
 493                 clocks = <&cru PCLK_I2C0>;
 494                 clock-names = "i2c";
 495                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 496                 pinctrl-names = "default";
 497                 pinctrl-0 = <&i2c0_xfer>;
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 status = "disabled";
 501         };
 502
 503         i2c2: i2c@ff140000 {
 504                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 505                 reg = <0x0 0xff140000 0x0 0x1000>;
 506                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 clock-names = "i2c";
 510                 clocks = <&cru PCLK_I2C2>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&i2c2_xfer>;
 513                 status = "disabled";
 514         };
 515
 516         i2c3: i2c@ff150000 {
 517                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 518                 reg = <0x0 0xff150000 0x0 0x1000>;
 519                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 clock-names = "i2c";
 523                 clocks = <&cru PCLK_I2C3>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2c3_xfer>;
 526                 status = "disabled";
 527         };
 528
 529         i2c4: i2c@ff160000 {
 530                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 531                 reg = <0x0 0xff160000 0x0 0x1000>;
 532                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 clock-names = "i2c";
 536                 clocks = <&cru PCLK_I2C4>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c4_xfer>;
 539                 status = "disabled";
 540         };
 541
 542         i2c5: i2c@ff170000 {
 543                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 544                 reg = <0x0 0xff170000 0x0 0x1000>;
 545                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 clock-names = "i2c";
 549                 clocks = <&cru PCLK_I2C5>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c5_xfer>;
 552                 status = "disabled";
 553         };
 554
 555         uart0: serial@ff180000 {
 556                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 557                 reg = <0x0 0xff180000 0x0 0x100>;
 558                 clock-frequency = <24000000>;
 559                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 560                 clock-names = "baudclk", "apb_pclk";
 561                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 562                 reg-shift = <2>;
 563                 reg-io-width = <4>;
 564                 status = "disabled";
 565         };
 566
 567         uart1: serial@ff190000 {
 568                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 569                 reg = <0x0 0xff190000 0x0 0x100>;
 570                 clock-frequency = <24000000>;
 571                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 572                 clock-names = "baudclk", "apb_pclk";
 573                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 574                 reg-shift = <2>;
 575                 reg-io-width = <4>;
 576                 status = "disabled";
 577         };
 578
 579         uart3: serial@ff1b0000 {
 580                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 581                 reg = <0x0 0xff1b0000 0x0 0x100>;
 582                 clock-frequency = <24000000>;
 583                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 584                 clock-names = "baudclk", "apb_pclk";
 585                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 586                 reg-shift = <2>;
 587                 reg-io-width = <4>;
 588                 status = "disabled";
 589         };
 590
 591         uart4: serial@ff1c0000 {
 592                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 593                 reg = <0x0 0xff1c0000 0x0 0x100>;
 594                 clock-frequency = <24000000>;
 595                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 596                 clock-names = "baudclk", "apb_pclk";
 597                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 598                 reg-shift = <2>;
 599                 reg-io-width = <4>;
 600                 status = "disabled";
 601         };
 602
 603         thermal-zones {
 604                 cpu {
 605                         polling-delay-passive = <100>; /* milliseconds */
 606                         polling-delay = <5000>; /* milliseconds */
 607
 608                         thermal-sensors = <&tsadc 0>;
 609
 610                         trips {
 611                                 cpu_alert0: cpu_alert0 {
 612                                         temperature = <75000>; /* millicelsius */
 613                                         hysteresis = <2000>; /* millicelsius */
 614                                         type = "passive";
 615                                 };
 616                                 cpu_alert1: cpu_alert1 {
 617                                         temperature = <80000>; /* millicelsius */
 618                                         hysteresis = <2000>; /* millicelsius */
 619                                         type = "passive";
 620                                 };
 621                                 cpu_crit: cpu_crit {
 622                                         temperature = <95000>; /* millicelsius */
 623                                         hysteresis = <2000>; /* millicelsius */
 624                                         type = "critical";
 625                                 };
 626                         };
 627
 628                         cooling-maps {
 629                                 map0 {
 630                                         trip = <&cpu_alert0>;
 631                                         cooling-device =
 632                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 633                                 };
 634                                 map1 {
 635                                         trip = <&cpu_alert1>;
 636                                         cooling-device =
 637                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 638                                 };
 639                         };
 640                 };
 641
 642                 gpu {
 643                         polling-delay-passive = <100>; /* milliseconds */
 644                         polling-delay = <5000>; /* milliseconds */
 645
 646                         thermal-sensors = <&tsadc 1>;
 647
 648                         trips {
 649                                 gpu_alert0: gpu_alert0 {
 650                                         temperature = <80000>; /* millicelsius */
 651                                         hysteresis = <2000>; /* millicelsius */
 652                                         type = "passive";
 653                                 };
 654                                 gpu_crit: gpu_crit {
 655                                         temperature = <115000>; /* millicelsius */
 656                                         hysteresis = <2000>; /* millicelsius */
 657                                         type = "critical";
 658                                 };
 659                         };
 660
 661                         cooling-maps {
 662                                 map0 {
 663                                         trip = <&gpu_alert0>;
 664                                         cooling-device =
 665                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 666                                 };
 667                         };
 668                 };
 669         };
 670
 671         tsadc: tsadc@ff280000 {
 672                 compatible = "rockchip,rk3368-tsadc-legacy";
 673                 reg = <0x0 0xff280000 0x0 0x100>;
 674                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 675                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 676                 clock-names = "tsadc", "apb_pclk";
 677                 clock-frequency = <32768>;
 678                 resets = <&cru SRST_TSADC>;
 679                 reset-names = "tsadc-apb";
 680                 nvmem-cells = <&temp_adjust>;
 681                 nvmem-cell-names = "temp_adjust";
 682                 #thermal-sensor-cells = <1>;
 683                 hw-shut-temp = <95000>;
 684                 status = "disabled";
 685         };
 686
 687         gmac: ethernet@ff290000 {
 688                 compatible = "rockchip,rk3368-gmac";
 689                 reg = <0x0 0xff290000 0x0 0x10000>;
 690                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 691                 interrupt-names = "macirq";
 692                 rockchip,grf = <&grf>;
 693                 clocks = <&cru SCLK_MAC>,
 694                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 695                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 696                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 697                 clock-names = "stmmaceth",
 698                         "mac_clk_rx", "mac_clk_tx",
 699                         "clk_mac_ref", "clk_mac_refout",
 700                         "aclk_mac", "pclk_mac";
 701                 status = "disabled";
 702         };
 703
 704         nandc0: nandc@ff400000 {
 705                 compatible = "rockchip,rk-nandc";
 706                 reg = <0x0 0xff400000 0x0 0x4000>;
 707                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 708                 nandc_id = <0>;
 709                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 710                 clock-names = "clk_nandc", "hclk_nandc";
 711                 status = "disabled";
 712         };
 713
 714         usb_host0_ehci: usb@ff500000 {
 715                 compatible = "generic-ehci";
 716                 reg = <0x0 0xff500000 0x0 0x20000>;
 717                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 718                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 719                 clock-names = "usbhost", "utmi";
 720                 phys = <&u2phy_host>;
 721                 phy-names = "usb";
 722                 status = "disabled";
 723         };
 724
 725         usb_host0_ohci: usb@ff520000 {
 726                 compatible = "generic-ohci";
 727                 reg = <0x0 0xff520000 0x0 0x20000>;
 728                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 730                 clock-names = "usbhost", "utmi";
 731                 phys = <&u2phy_host>;
 732                 phy-names = "usb";
 733                 status = "disabled";
 734         };
 735
 736         usb_otg: usb@ff580000 {
 737                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 738                                 "snps,dwc2";
 739                 reg = <0x0 0xff580000 0x0 0x40000>;
 740                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&cru HCLK_OTG0>;
 742                 clock-names = "otg";
 743                 dr_mode = "otg";
 744                 g-np-tx-fifo-size = <16>;
 745                 g-rx-fifo-size = <275>;
 746                 g-tx-fifo-size = <256 128 128 64 64 32>;
 747                 g-use-dma;
 748                 status = "disabled";
 749         };
 750
 751         ddrpctl: syscon@ff610000 {
 752                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 753                 reg = <0x0 0xff610000 0x0 0x400>;
 754         };
 755
 756         i2c1: i2c@ff660000 {
 757                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 758                 reg = <0x0 0xff660000 0x0 0x1000>;
 759                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 760                 #address-cells = <1>;
 761                 #size-cells = <0>;
 762                 clock-names = "i2c";
 763                 clocks = <&cru PCLK_I2C1>;
 764                 pinctrl-names = "default";
 765                 pinctrl-0 = <&i2c1_xfer>;
 766                 status = "disabled";
 767         };
 768
 769         pwm0: pwm@ff680000 {
 770                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 771                 reg = <0x0 0xff680000 0x0 0x10>;
 772                 #pwm-cells = <3>;
 773                 pinctrl-names = "default";
 774                 pinctrl-0 = <&pwm0_pin>;
 775                 clocks = <&cru PCLK_PWM1>;
 776                 clock-names = "pwm";
 777                 status = "disabled";
 778         };
 779
 780         pwm1: pwm@ff680010 {
 781                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 782                 reg = <0x0 0xff680010 0x0 0x10>;
 783                 #pwm-cells = <3>;
 784                 pinctrl-names = "default";
 785                 pinctrl-0 = <&pwm1_pin>;
 786                 clocks = <&cru PCLK_PWM1>;
 787                 clock-names = "pwm";
 788                 status = "disabled";
 789         };
 790
 791         pwm2: pwm@ff680020 {
 792                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 793                 reg = <0x0 0xff680020 0x0 0x10>;
 794                 #pwm-cells = <3>;
 795                 clocks = <&cru PCLK_PWM1>;
 796                 clock-names = "pwm";
 797                 status = "disabled";
 798         };
 799
 800         pwm3: pwm@ff680030 {
 801                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 802                 reg = <0x0 0xff680030 0x0 0x10>;
 803                 #pwm-cells = <3>;
 804                 pinctrl-names = "default";
 805                 pinctrl-0 = <&pwm3_pin>;
 806                 clocks = <&cru PCLK_PWM1>;
 807                 clock-names = "pwm";
 808                 status = "disabled";
 809         };
 810
 811         uart2: serial@ff690000 {
 812                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 813                 reg = <0x0 0xff690000 0x0 0x100>;
 814                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 815                 clock-names = "baudclk", "apb_pclk";
 816                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 817                 pinctrl-names = "default";
 818                 pinctrl-0 = <&uart2_xfer>;
 819                 reg-shift = <2>;
 820                 reg-io-width = <4>;
 821                 status = "disabled";
 822         };
 823
 824         mbox: mbox@ff6b0000 {
 825                 compatible = "rockchip,rk3368-mailbox";
 826                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 827                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 828                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 829                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 830                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 831                 clocks = <&cru PCLK_MAILBOX>;
 832                 clock-names = "pclk_mailbox";
 833                 #mbox-cells = <1>;
 834                 status = "disabled";
 835         };
 836
 837         mailbox: mailbox@ff6b0000 {
 838                 compatible = "rockchip,rk3368-mbox-legacy";
 839                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 840                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 841                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 842                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 843                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 844                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 845                 clocks = <&cru PCLK_MAILBOX>;
 846                 clock-names = "pclk_mailbox";
 847                 #mbox-cells = <1>;
 848                 status = "disabled";
 849         };
 850
 851         mailbox_scpi: mailbox-scpi {
 852                 compatible = "rockchip,rk3368-scpi-legacy";
 853                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 854                 chan-nums = <3>;
 855                 status = "disabled";
 856         };
 857
 858         qos_iep: qos@ffad0000 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffad0000 0x0 0x20>;
 861         };
 862
 863         qos_isp_r0: qos@ffad0080 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffad0080 0x0 0x20>;
 866         };
 867
 868         qos_isp_r1: qos@ffad0100 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffad0100 0x0 0x20>;
 871         };
 872
 873         qos_isp_w0: qos@ffad0180 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffad0180 0x0 0x20>;
 876         };
 877
 878         qos_isp_w1: qos@ffad0200 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffad0200 0x0 0x20>;
 881         };
 882
 883         qos_vip: qos@ffad0280 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffad0280 0x0 0x20>;
 886         };
 887
 888         qos_vop: qos@ffad0300 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffad0300 0x0 0x20>;
 891         };
 892
 893         qos_rga_r: qos@ffad0380 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffad0380 0x0 0x20>;
 896         };
 897
 898         qos_rga_w: qos@ffad0400 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffad0400 0x0 0x20>;
 901         };
 902
 903         qos_hevc_r: qos@ffae0000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffae0000 0x0 0x20>;
 906         };
 907
 908         qos_vpu_r: qos@ffae0100 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffae0100 0x0 0x20>;
 911         };
 912
 913         qos_vpu_w: qos@ffae0180 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffae0180 0x0 0x20>;
 916         };
 917
 918         qos_gpu: qos@ffaf0000 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffaf0000 0x0 0x20>;
 921         };
 922
 923         pmu: power-management@ff730000 {
 924                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 925                 reg = <0x0 0xff730000 0x0 0x1000>;
 926
 927                 power: power-controller {
 928                         compatible = "rockchip,rk3368-power-controller";
 929                         #power-domain-cells = <1>;
 930                         #address-cells = <1>;
 931                         #size-cells = <0>;
 932
 933                         /*
 934                          * Note: Although SCLK_* are the working clocks
 935                          * of device without including on the NOC, needed for
 936                          * synchronous reset.
 937                          *
 938                          * The clocks on the which NOC:
 939                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 940                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 941                          * ACLK_RGA is on ACLK_RGA_NIU.
 942                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 943                          *
 944                          * Which clock are device clocks:
 945                          *      clocks          devices
 946                          *      *_IEP           IEP:Image Enhancement Processor
 947                          *      *_ISP           ISP:Image Signal Processing
 948                          *      *_VIP           VIP:Video Input Processor
 949                          *      *_VOP*          VOP:Visual Output Processor
 950                          *      *_RGA           RGA
 951                          *      *_EDP*          EDP
 952                          *      *_DPHY*         LVDS
 953                          *      *_HDMI          HDMI
 954                          *      *_MIPI_*        MIPI
 955                          */
 956                         pd_vio {
 957                                 reg = <RK3368_PD_VIO>;
 958                                 clocks = <&cru ACLK_IEP>,
 959                                          <&cru ACLK_ISP>,
 960                                          <&cru ACLK_VIP>,
 961                                          <&cru ACLK_RGA>,
 962                                          <&cru ACLK_VOP>,
 963                                          <&cru ACLK_VOP_IEP>,
 964                                          <&cru DCLK_VOP>,
 965                                          <&cru HCLK_IEP>,
 966                                          <&cru HCLK_ISP>,
 967                                          <&cru HCLK_RGA>,
 968                                          <&cru HCLK_VIP>,
 969                                          <&cru HCLK_VOP>,
 970                                          <&cru HCLK_VIO_HDCPMMU>,
 971                                          <&cru PCLK_EDP_CTRL>,
 972                                          <&cru PCLK_HDMI_CTRL>,
 973                                          <&cru PCLK_HDCP>,
 974                                          <&cru PCLK_ISP>,
 975                                          <&cru PCLK_VIP>,
 976                                          <&cru PCLK_DPHYRX>,
 977                                          <&cru PCLK_DPHYTX0>,
 978                                          <&cru PCLK_MIPI_CSI>,
 979                                          <&cru PCLK_MIPI_DSI0>,
 980                                          <&cru SCLK_VOP0_PWM>,
 981                                          <&cru SCLK_EDP_24M>,
 982                                          <&cru SCLK_EDP>,
 983                                          <&cru SCLK_HDCP>,
 984                                          <&cru SCLK_ISP>,
 985                                          <&cru SCLK_RGA>,
 986                                          <&cru SCLK_HDMI_CEC>,
 987                                          <&cru SCLK_HDMI_HDCP>;
 988                                 pm_qos = <&qos_iep>,
 989                                          <&qos_isp_r0>,
 990                                          <&qos_isp_r1>,
 991                                          <&qos_isp_w0>,
 992                                          <&qos_isp_w1>,
 993                                          <&qos_vip>,
 994                                          <&qos_vop>,
 995                                          <&qos_rga_r>,
 996                                          <&qos_rga_w>;
 997                         };
 998                         /*
 999                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1000                          * (video endecoder & decoder) clocks that on the
1001                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1002                          */
1003                         pd_video {
1004                                 reg = <RK3368_PD_VIDEO>;
1005                                 clocks = <&cru ACLK_VIDEO>,
1006                                          <&cru HCLK_VIDEO>,
1007                                          <&cru SCLK_HEVC_CABAC>,
1008                                          <&cru SCLK_HEVC_CORE>;
1009                                 pm_qos = <&qos_hevc_r>,
1010                                          <&qos_vpu_r>,
1011                                          <&qos_vpu_w>;
1012                         };
1013                         /*
1014                          * Note: ACLK_GPU is the GPU clock,
1015                          * and on the ACLK_GPU_NIU (NOC).
1016                          */
1017                         pd_gpu_1 {
1018                                 reg = <RK3368_PD_GPU_1>;
1019                                 clocks = <&cru ACLK_GPU_CFG>,
1020                                          <&cru ACLK_GPU_MEM>,
1021                                          <&cru SCLK_GPU_CORE>;
1022                                 pm_qos = <&qos_gpu>;
1023                         };
1024                 };
1025         };
1026
1027         pmugrf: syscon@ff738000 {
1028                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1029                 reg = <0x0 0xff738000 0x0 0x1000>;
1030
1031                 pmu_io_domains: io-domains {
1032                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1033                         status = "disabled";
1034                 };
1035
1036                 reboot-mode {
1037                         compatible = "syscon-reboot-mode";
1038                         offset = <0x200>;
1039                         mode-normal = <BOOT_NORMAL>;
1040                         mode-recovery = <BOOT_RECOVERY>;
1041                         mode-bootloader = <BOOT_FASTBOOT>;
1042                         mode-loader = <BOOT_BL_DOWNLOAD>;
1043                 };
1044         };
1045
1046         cru: clock-controller@ff760000 {
1047                 compatible = "rockchip,rk3368-cru";
1048                 reg = <0x0 0xff760000 0x0 0x1000>;
1049                 rockchip,grf = <&grf>;
1050                 #clock-cells = <1>;
1051                 #reset-cells = <1>;
1052                 assigned-clocks =
1053                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1054                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1055                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1056                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1057                 assigned-clock-rates =
1058                         <576000000>, <400000000>,
1059                         <300000000>, <300000000>,
1060                         <150000000>, <150000000>,
1061                         <75000000>, <75000000>;
1062         };
1063
1064         grf: syscon@ff770000 {
1065                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1066                 reg = <0x0 0xff770000 0x0 0x1000>;
1067                 #address-cells = <1>;
1068                 #size-cells = <1>;
1069
1070                 io_domains: io-domains {
1071                         compatible = "rockchip,rk3368-io-voltage-domain";
1072                         status = "disabled";
1073                 };
1074
1075                 u2phy: usb2-phy@700 {
1076                         compatible = "rockchip,rk3368-usb2phy";
1077                         reg = <0x700 0x2c>;
1078                         clocks = <&cru SCLK_OTGPHY0>;
1079                         clock-names = "phyclk";
1080                         #clock-cells = <0>;
1081                         clock-output-names = "usbotg_out";
1082                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1083                         assigned-clock-parents = <&u2phy>;
1084                         status = "disabled";
1085
1086                         u2phy_host: host-port {
1087                                 #phy-cells = <0>;
1088                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1089                                 interrupt-names = "linestate";
1090                                 status = "disabled";
1091                         };
1092                 };
1093         };
1094
1095         wdt: watchdog@ff800000 {
1096                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1097                 reg = <0x0 0xff800000 0x0 0x100>;
1098                 clocks = <&cru PCLK_WDT>;
1099                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1100                 status = "disabled";
1101         };
1102
1103         timer@ff810000 {
1104                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1105                 reg = <0x0 0xff810000 0x0 0x20>;
1106                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1107         };
1108
1109         i2s_2ch: i2s-2ch@ff890000 {
1110                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1111                 reg = <0x0 0xff890000 0x0 0x1000>;
1112                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1113                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1114                 dma-names = "tx", "rx";
1115                 clock-names = "i2s_clk", "i2s_hclk";
1116                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1117                 status = "disabled";
1118         };
1119
1120         i2s_8ch: i2s-8ch@ff898000 {
1121                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1122                 reg = <0x0 0xff898000 0x0 0x1000>;
1123                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1124                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1125                 dma-names = "tx", "rx";
1126                 clock-names = "i2s_clk", "i2s_hclk";
1127                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1128                 pinctrl-names = "default";
1129                 pinctrl-0 = <&i2s_8ch_bus>;
1130                 status = "disabled";
1131         };
1132
1133         isp_mmu: iommu@ff914000 {
1134                 compatible = "rockchip,iommu";
1135                 reg = <0x0 0xff914000 0x0 0x100>,
1136                       <0x0 0xff915000 0x0 0x100>;
1137                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1138                 interrupt-names = "isp_mmu";
1139                 #iommu-cells = <0>;
1140                 status = "disabled";
1141         };
1142
1143         vop: vop@ff930000 {
1144                 compatible = "rockchip,rk3368-vop";
1145                 reg = <0x0 0xff930000 0x0 0x2fc>;
1146                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1147                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1148                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1149                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1150                 assigned-clock-rates = <400000000>, <200000000>;
1151                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1152                 reset-names = "axi", "ahb", "dclk";
1153                 power-domains = <&power RK3368_PD_VIO>;
1154                 iommus = <&vop_mmu>;
1155                 status = "disabled";
1156
1157                 vop_out: port {
1158                         #address-cells = <1>;
1159                         #size-cells = <0>;
1160
1161                         vop_out_mipi: endpoint@0 {
1162                                 reg = <0>;
1163                                 remote-endpoint = <&mipi_in_vop>;
1164                         };
1165                 };
1166         };
1167
1168         display_subsystem: display-subsystem {
1169                 compatible = "rockchip,display-subsystem";
1170                 ports = <&vop_out>;
1171                 status = "disabled";
1172         };
1173
1174         vop_mmu: iommu@ff930300 {
1175                 compatible = "rockchip,iommu";
1176                 reg = <0x0 0xff930300 0x0 0x100>;
1177                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1178                 interrupt-names = "vop_mmu";
1179                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1180                 clock-names = "aclk", "hclk";
1181                 power-domains = <&power RK3368_PD_VIO>;
1182                 #iommu-cells = <0>;
1183                 status = "disabled";
1184         };
1185
1186         mipi_dsi_host: mipi-dsi-host@ff960000 {
1187                 compatible = "rockchip,rk3368-mipi-dsi";
1188                 reg = <0x0 0xff960000 0x0 0x4000>;
1189                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1190                 clocks = <&cru PCLK_MIPI_DSI0>;
1191                 clock-names = "pclk";
1192                 phys = <&mipi_dphy>;
1193                 phy-names = "mipi_dphy";
1194                 rockchip,grf = <&grf>;
1195                 power-domains = <&power RK3368_PD_VIO>;
1196                 #address-cells = <1>;
1197                 #size-cells = <0>;
1198                 status = "disabled";
1199
1200                 ports@1 {
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203                         reg = <1>;
1204
1205                         mipi_in: port {
1206                                 #address-cells = <1>;
1207                                 #size-cells = <0>;
1208
1209                                 mipi_in_vop: endpoint@0 {
1210                                         reg = <0>;
1211                                         remote-endpoint = <&vop_out_mipi>;
1212                                 };
1213                         };
1214                 };
1215         };
1216
1217         mipi_dphy: mipi-dphy@ff968000 {
1218                 compatible = "rockchip,rk3368-mipi-dphy";
1219                 reg = <0x0 0xff968000 0x0 0x4000>;
1220                 #phy-cells = <0>;
1221                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1222                 clock-names = "ref", "pclk";
1223                 status = "disabled";
1224         };
1225
1226         hevc_mmu: iommu@ff9a0440 {
1227                 compatible = "rockchip,iommu";
1228                 reg = <0x0 0xff9a0440 0x0 0x100>,
1229                       <0x0 0xff9a0480 0x0 0x100>;
1230                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1231                 interrupt-names = "hevc_mmu";
1232                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1233                 clock-names = "aclk", "hclk";
1234                 power-domains = <&power RK3368_PD_VIDEO>;
1235                 #iommu-cells = <0>;
1236                 status = "disabled";
1237         };
1238
1239         vpu_mmu: iommu@ff9a0800 {
1240                 compatible = "rockchip,iommu";
1241                 reg = <0x0 0xff9a0800 0x0 0x100>;
1242                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1243                 interrupt-names = "vpu_mmu";
1244                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1245                 clock-names = "aclk", "hclk";
1246                 power-domains = <&power RK3368_PD_VIDEO>;
1247                 #iommu-cells = <0>;
1248                 status = "disabled";
1249         };
1250
1251         gic: interrupt-controller@ffb71000 {
1252                 compatible = "arm,gic-400";
1253                 interrupt-controller;
1254                 #interrupt-cells = <3>;
1255                 #address-cells = <0>;
1256
1257                 reg = <0x0 0xffb71000 0x0 0x1000>,
1258                       <0x0 0xffb72000 0x0 0x2000>,
1259                       <0x0 0xffb74000 0x0 0x2000>,
1260                       <0x0 0xffb76000 0x0 0x2000>;
1261                 interrupts = <GIC_PPI 9
1262                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1263         };
1264
1265         gpu: rogue-g6110@ffa30000 {
1266                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1267                 reg = <0x0 0xffa30000 0x0 0x10000>;
1268                 clocks =
1269                         <&cru SCLK_GPU_CORE>,
1270                         <&cru ACLK_GPU_MEM>,
1271                         <&cru ACLK_GPU_CFG>;
1272                 clock-names =
1273                         "sclk_gpu_core",
1274                         "aclk_gpu_mem",
1275                         "aclk_gpu_cfg";
1276                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1277                 interrupt-names = "rogue-g6110-irq";
1278                 power-domains = <&power RK3368_PD_GPU_1>;
1279                 operating-points-v2 = <&gpu_opp_table>;
1280         };
1281
1282         gpu_opp_table: gpu_opp_table {
1283                 compatible = "operating-points-v2";
1284                 opp-shared;
1285
1286                 opp@200000000 {
1287                         opp-hz = /bits/ 64 <200000000>;
1288                         opp-microvolt = <1100000>;
1289                 };
1290                 opp@288000000 {
1291                         opp-hz = /bits/ 64 <288000000>;
1292                         opp-microvolt = <1100000>;
1293                 };
1294                 opp@400000000 {
1295                         opp-hz = /bits/ 64 <400000000>;
1296                         opp-microvolt = <1100000>;
1297                 };
1298                 opp@576000000 {
1299                         opp-hz = /bits/ 64 <576000000>;
1300                         opp-microvolt = <1200000>;
1301                 };
1302         };
1303
1304         efuse: efuse@ffb00000 {
1305                 compatible = "rockchip,rk3368-efuse";
1306                 reg = <0x0 0xffb00000 0x0 0x20>;
1307                 #address-cells = <1>;
1308                 #size-cells = <1>;
1309                 clocks = <&cru PCLK_EFUSE256>;
1310                 clock-names = "pclk_efuse";
1311
1312                 /* Data cells */
1313                 cpu_leakage: cpu-leakage@17 {
1314                         reg = <0x17 0x1>;
1315                 };
1316                 temp_adjust: temp-adjust@1f {
1317                         reg = <0x1f 0x1>;
1318                 };
1319         };
1320
1321         pinctrl: pinctrl {
1322                 compatible = "rockchip,rk3368-pinctrl";
1323                 rockchip,grf = <&grf>;
1324                 rockchip,pmu = <&pmugrf>;
1325                 #address-cells = <0x2>;
1326                 #size-cells = <0x2>;
1327                 ranges;
1328
1329                 gpio0: gpio0@ff750000 {
1330                         compatible = "rockchip,gpio-bank";
1331                         reg = <0x0 0xff750000 0x0 0x100>;
1332                         clocks = <&cru PCLK_GPIO0>;
1333                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1334
1335                         gpio-controller;
1336                         #gpio-cells = <0x2>;
1337
1338                         interrupt-controller;
1339                         #interrupt-cells = <0x2>;
1340                 };
1341
1342                 gpio1: gpio1@ff780000 {
1343                         compatible = "rockchip,gpio-bank";
1344                         reg = <0x0 0xff780000 0x0 0x100>;
1345                         clocks = <&cru PCLK_GPIO1>;
1346                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1347
1348                         gpio-controller;
1349                         #gpio-cells = <0x2>;
1350
1351                         interrupt-controller;
1352                         #interrupt-cells = <0x2>;
1353                 };
1354
1355                 gpio2: gpio2@ff790000 {
1356                         compatible = "rockchip,gpio-bank";
1357                         reg = <0x0 0xff790000 0x0 0x100>;
1358                         clocks = <&cru PCLK_GPIO2>;
1359                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1360
1361                         gpio-controller;
1362                         #gpio-cells = <0x2>;
1363
1364                         interrupt-controller;
1365                         #interrupt-cells = <0x2>;
1366                 };
1367
1368                 gpio3: gpio3@ff7a0000 {
1369                         compatible = "rockchip,gpio-bank";
1370                         reg = <0x0 0xff7a0000 0x0 0x100>;
1371                         clocks = <&cru PCLK_GPIO3>;
1372                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1373
1374                         gpio-controller;
1375                         #gpio-cells = <0x2>;
1376
1377                         interrupt-controller;
1378                         #interrupt-cells = <0x2>;
1379                 };
1380
1381                 pcfg_pull_up: pcfg-pull-up {
1382                         bias-pull-up;
1383                 };
1384
1385                 pcfg_pull_down: pcfg-pull-down {
1386                         bias-pull-down;
1387                 };
1388
1389                 pcfg_pull_none: pcfg-pull-none {
1390                         bias-disable;
1391                 };
1392
1393                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1394                         bias-disable;
1395                         drive-strength = <12>;
1396                 };
1397
1398                 emmc {
1399                         emmc_clk: emmc-clk {
1400                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1401                         };
1402
1403                         emmc_cmd: emmc-cmd {
1404                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1405                         };
1406
1407                         emmc_pwr: emmc-pwr {
1408                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1409                         };
1410
1411                         emmc_bus1: emmc-bus1 {
1412                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1413                         };
1414
1415                         emmc_bus4: emmc-bus4 {
1416                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1417                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1418                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1419                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1420                         };
1421
1422                         emmc_bus8: emmc-bus8 {
1423                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1424                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1425                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1426                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1427                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1428                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1429                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1430                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1431                         };
1432                 };
1433
1434                 gmac {
1435                         rgmii_pins: rgmii-pins {
1436                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1437                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1438                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1439                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1440                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1441                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1442                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1443                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1444                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1445                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1446                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1447                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1448                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1449                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1450                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1451                         };
1452
1453                         rmii_pins: rmii-pins {
1454                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1455                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1456                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1457                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1458                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1459                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1460                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1461                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1462                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1463                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 i2c0 {
1468                         i2c0_xfer: i2c0-xfer {
1469                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1470                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1471                         };
1472                 };
1473
1474                 i2c1 {
1475                         i2c1_xfer: i2c1-xfer {
1476                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1477                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1478                         };
1479                 };
1480
1481                 i2c2 {
1482                         i2c2_xfer: i2c2-xfer {
1483                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1484                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1485                         };
1486                 };
1487
1488                 i2c3 {
1489                         i2c3_xfer: i2c3-xfer {
1490                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1491                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1492                         };
1493                 };
1494
1495                 i2c4 {
1496                         i2c4_xfer: i2c4-xfer {
1497                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1498                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1499                         };
1500                 };
1501
1502                 i2c5 {
1503                         i2c5_xfer: i2c5-xfer {
1504                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1505                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1506                         };
1507                 };
1508
1509                 i2s {
1510                         i2s_8ch_bus: i2s-8ch-bus {
1511                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1512                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1513                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1514                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1515                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1516                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1517                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1518                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1519                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1520                         };
1521                 };
1522
1523                 pwm0 {
1524                         pwm0_pin: pwm0-pin {
1525                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1526                         };
1527
1528                         vop_pwm_pin: vop-pwm {
1529                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1530                         };
1531                 };
1532
1533                 pwm1 {
1534                         pwm1_pin: pwm1-pin {
1535                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 pwm3 {
1540                         pwm3_pin: pwm3-pin {
1541                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1542                         };
1543                 };
1544
1545                 sdio0 {
1546                         sdio0_bus1: sdio0-bus1 {
1547                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1548                         };
1549
1550                         sdio0_bus4: sdio0-bus4 {
1551                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1552                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1553                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1554                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1555                         };
1556
1557                         sdio0_cmd: sdio0-cmd {
1558                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1559                         };
1560
1561                         sdio0_clk: sdio0-clk {
1562                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564
1565                         sdio0_cd: sdio0-cd {
1566                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1567                         };
1568
1569                         sdio0_wp: sdio0-wp {
1570                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1571                         };
1572
1573                         sdio0_pwr: sdio0-pwr {
1574                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1575                         };
1576
1577                         sdio0_bkpwr: sdio0-bkpwr {
1578                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1579                         };
1580
1581                         sdio0_int: sdio0-int {
1582                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1583                         };
1584                 };
1585
1586                 sdmmc {
1587                         sdmmc_clk: sdmmc-clk {
1588                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1589                         };
1590
1591                         sdmmc_cmd: sdmmc-cmd {
1592                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1593                         };
1594
1595                         sdmmc_cd: sdmmc-cd {
1596                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1597                         };
1598
1599                         sdmmc_bus1: sdmmc-bus1 {
1600                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1601                         };
1602
1603                         sdmmc_bus4: sdmmc-bus4 {
1604                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1605                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1606                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1607                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1608                         };
1609                 };
1610
1611                 spi0 {
1612                         spi0_clk: spi0-clk {
1613                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1614                         };
1615                         spi0_cs0: spi0-cs0 {
1616                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1617                         };
1618                         spi0_cs1: spi0-cs1 {
1619                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1620                         };
1621                         spi0_tx: spi0-tx {
1622                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1623                         };
1624                         spi0_rx: spi0-rx {
1625                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1626                         };
1627                 };
1628
1629                 spi1 {
1630                         spi1_clk: spi1-clk {
1631                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1632                         };
1633                         spi1_cs0: spi1-cs0 {
1634                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1635                         };
1636                         spi1_cs1: spi1-cs1 {
1637                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1638                         };
1639                         spi1_rx: spi1-rx {
1640                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1641                         };
1642                         spi1_tx: spi1-tx {
1643                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1644                         };
1645                 };
1646
1647                 spi2 {
1648                         spi2_clk: spi2-clk {
1649                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1650                         };
1651                         spi2_cs0: spi2-cs0 {
1652                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1653                         };
1654                         spi2_rx: spi2-rx {
1655                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1656                         };
1657                         spi2_tx: spi2-tx {
1658                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1659                         };
1660                 };
1661
1662                 uart0 {
1663                         uart0_xfer: uart0-xfer {
1664                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1665                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1666                         };
1667
1668                         uart0_cts: uart0-cts {
1669                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1670                         };
1671
1672                         uart0_rts: uart0-rts {
1673                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1674                         };
1675                 };
1676
1677                 uart1 {
1678                         uart1_xfer: uart1-xfer {
1679                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1680                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1681                         };
1682
1683                         uart1_cts: uart1-cts {
1684                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1685                         };
1686
1687                         uart1_rts: uart1-rts {
1688                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1689                         };
1690                 };
1691
1692                 uart2 {
1693                         uart2_xfer: uart2-xfer {
1694                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1695                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1696                         };
1697                         /* no rts / cts for uart2 */
1698                 };
1699
1700                 uart3 {
1701                         uart3_xfer: uart3-xfer {
1702                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1703                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1704                         };
1705
1706                         uart3_cts: uart3-cts {
1707                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1708                         };
1709
1710                         uart3_rts: uart3-rts {
1711                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1712                         };
1713                 };
1714
1715                 uart4 {
1716                         uart4_xfer: uart4-xfer {
1717                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1718                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1719                         };
1720
1721                         uart4_cts: uart4-cts {
1722                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1723                         };
1724
1725                         uart4_rts: uart4-rts {
1726                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1727                         };
1728                 };
1729         };
1730 };