clk: rockchip: rk3288: fix up the clk register for hclk_vio
authorElaine Zhang <zhangqing@rock-chips.com>
Tue, 11 Apr 2017 03:11:56 +0000 (11:11 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Tue, 11 Apr 2017 08:39:41 +0000 (16:39 +0800)
Change-Id: If07e27b1f88974fa0dcb2c8f719df6ba3c35dbcd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3288.c

index 2fd36be..1bbbc95 100644 (file)
@@ -411,12 +411,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
                RK3288_CLKGATE_CON(9), 1, GFLAGS),
 
-       COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(3), 0, GFLAGS),
-       DIV(0, "hclk_vio", "aclk_vio0", 0,
-                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
-       COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+       COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3288_CLKGATE_CON(3), 2, GFLAGS),
 
@@ -947,5 +945,20 @@ static void __init rk3288_clk_init(struct device_node *np)
        register_syscore_ops(&rk3288_clk_syscore_ops);
 
        rockchip_clk_of_add_provider(np, ctx);
+
+       if (of_machine_is_compatible("rockchip,rk3288w")) {
+               clk = clk_register_divider(NULL, "hclk_vio", "aclk_vio1", 0,
+                               ctx->reg_base + RK3288_CLKSEL_CON(28), 8, 5,
+                               DFLAGS, &ctx->lock);
+       } else {
+               clk = clk_register_divider(NULL, "hclk_vio", "aclk_vio0", 0,
+                               ctx->reg_base + RK3288_CLKSEL_CON(28), 8, 5,
+                               DFLAGS, &ctx->lock);
+       }
+       if (IS_ERR(clk))
+               pr_warn("%s: could not register clock hclk_vio: %ld\n",
+                       __func__, PTR_ERR(clk));
+       else
+               rockchip_clk_add_lookup(ctx, clk, HCLK_VIO);
 }
 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);