There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit
45970584ead0a5dfe27a6edef198ede536ad37ba (FROMLIST: drm: bridge:
analogix/dp: add some rk3288 special registers setting).
The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.
Change-Id: I8cb806d23144697225f626aaa2af19e6379dfe51
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
#define HSYNC_POLARITY_CFG (0x1 << 0)
/* ANALOGIX_DP_PLL_REG_1 */
-#define REF_CLK_24M (0x1 << 1)
-#define REF_CLK_27M (0x0 << 1)
+#define REF_CLK_24M (0x1 << 0)
+#define REF_CLK_27M (0x0 << 0)
/* ANALOGIX_DP_LANE_MAP */
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)