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drm: bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
authorYakir Yang <ykk@rock-chips.com>
Mon, 28 Mar 2016 02:48:19 +0000 (10:48 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Tue, 29 Mar 2016 12:15:46 +0000 (20:15 +0800)
commit455be1a2af76dbc2a3d3d808bf0d88a26c2a98ad
tree1cc7431e9f7b2bb2d68ec19ca2b7359fea27870ftree | snapshot
parent7a8bd6a860e186a7e42e19bbfc8cf124c355db11commit | diff
drm: bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit 45970584ead0a5dfe27a6edef198ede536ad37ba (FROMLIST: drm: bridge:
analogix/dp: add some rk3288 special registers setting).

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Change-Id: I8cb806d23144697225f626aaa2af19e6379dfe51
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h diff | blob | history
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