rk3368: clk: cpll: make cpll low jitter.

This modify is for cpll low jitter.
Make the signal of clk_gmac better.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rk3368-clocks.dtsi b/arch/arm64/boot/dts/rk3368-clocks.dtsi
index 39bda43e4acc14bf9f7593e9eb1155edfff017c8..1ef9c5c389c21c372857190ea21d9b25d6282d1e 100644 (file)
--- a/arch/arm64/boot/dts/rk3368-clocks.dtsi
+++ b/arch/arm64/boot/dts/rk3368-clocks.dtsi
@@ -330,7 +330,7 @@
                                        status-reg = <0x0480 3>;
                                        clocks = <&xin24m>;
                                        clock-output-names = "clk_cpll";
-                                       rockchip,pll-type = <CLK_PLL_3188PLUS>;
+                                       rockchip,pll-type = <CLK_PLL_3368_LOW_JITTER>;
                                        #clock-cells = <0>;
                                        #clock-init-cells = <1>;
                                };

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 210254b320c772a0f9b2e8b34da31e391106d262..325eb2c9167d1d795dc7f4a72053cf75acebb9c2 100755 (executable)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -332,6 +332,7 @@ static const struct apll_clk_set rk3368_aplll_table[] = {
 static const struct pll_clk_set rk3368_pll_table_low_jitter[] = {
        /*                             _khz, nr,  nf, no, nb */
        _RK3188PLUS_PLL_SET_CLKS_NB(1188000,  1,  99,  2,  1),
+       _RK3188PLUS_PLL_SET_CLKS_NB(400000,  1,  100,  6,  1),
        _RK3188PLUS_PLL_SET_CLKS(         0,  0,   0,  0),
 };