Documentation: rockchip-emmc-phy: add ctrl-base support

This patch adds ctrl-base which points to the digital block
to setup phy pll enabling.

Change-Id: I922dd7574229fda6b2ee51ca6ed1d7852ef87d30
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
index a962fafc62bacb84620d0463d9c650b5f612d3ca..73eda56201907988f3cdc44fd4cd3afd4e28b16a 100644 (file)
--- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
@@ -8,6 +8,7 @@ Required properties:
  - #phy-cells: must be 0
  - reg-offset: PHY configure reg address offset in "general
    register files"
  - #phy-cells: must be 0
  - reg-offset: PHY configure reg address offset in "general
    register files"

+ - ctrl-base: controller digital block's physical address.

 
 Optional Properties:
  - freq-sel: must match the freq of emmc clock, only support the
 
 Optional Properties:
  - freq-sel: must match the freq of emmc clock, only support the


@@ -22,5 +23,6 @@ emmcphy: phy {
        compatible = "rockchip,rk3399-emmc-phy";
        rockchip,grf = <&grf>;
        reg-offset = <0xf780>;
        compatible = "rockchip,rk3399-emmc-phy";
        rockchip,grf = <&grf>;
        reg-offset = <0xf780>;

+       ctrl-base = <0xfe330000>;

        #phy-cells = <0>;
 };
        #phy-cells = <0>;
 };