2 -----------------------
5 - compatible: rockchip,rk3399-emmc-phy
6 - rockchip,grf : phandle to the syscon managing the "general
8 - #phy-cells: must be 0
9 - reg-offset: PHY configure reg address offset in "general
11 - ctrl-base: controller digital block's physical address.
14 - freq-sel: must match the freq of emmc clock, only support the
15 following frequency: 50000000, 100000000, 150000000, 200000000.
16 If not assigned any freq, default use 200000000Hz.
17 - dr-sel: select the drive strength of phy IO.
18 - opdelay: select the output delay count number for clk IO and data IO
23 compatible = "rockchip,rk3399-emmc-phy";
24 rockchip,grf = <&grf>;
25 reg-offset = <0xf780>;
26 ctrl-base = <0xfe330000>;