- cdn_dp_fb: dp-fb@fec00000 {
- status = "disabled";
- compatible = "rockchip,rk3399-cdn-dp-fb";
- reg = <0x0 0xfec00000 0x0 0x100000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
- <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
- clock-names = "core-clk", "pclk", "spdif", "grf";
- assigned-clocks = <&cru SCLK_DP_CORE>;
- assigned-clock-rates = <100000000>;
- power-domains = <&power RK3399_PD_HDCP>;
- phys = <&tcphy0_dp>, <&tcphy1_dp>;
- resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
- <&cru SRST_P_UPHY0_APB>;
- reset-names = "spdif", "dptx", "apb";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- #sound-dai-cells = <1>;
- };
-
- cdn_dp_sound: cdn-dp-sound {
- status = "disabled";
- compatible = "simple-audio-card";
- simple-audio-card,name = "rockchip,cdn-dp-fb";
- simple-audio-card,widgets = "Headphone", "Out Jack",
- "Line", "In Jack";
-
- simple-audio-card,dai-link@0 {
- format = "i2s";
- mclk-fs = <256>;
-
- cpu {
- sound-dai = <&i2s2>;
- };
-
- codec {
- sound-dai = <&cdn_dp_fb 0>;
- };
- };
- };
-
- vpu: vpu_service@ff650000 {
- compatible = "rockchip,vpu_service";
- rockchip,grf = <&grf>;
- iommu_enabled = <1>;
- reg = <0x0 0xff650000 0x0 0x800>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "irq_dec", "irq_enc";
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VCODEC>;
- name = "vpu_service";
- dev_mode = <0>;
- };
-
- vpu_mmu: vpu_mmu {
- dbgname = "vpu";
- compatible = "rockchip,vpu_mmu";
- reg = <0x0 0xff650800 0x0 0x40>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vpu_mmu";
- };
-
- rkvdec: rkvdec@ff660000 {
- compatible = "rockchip,rkvdec";
- rockchip,grf = <&grf>;
- iommu_enabled = <1>;
- reg = <0x0 0xff660000 0x0 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "irq_dec";
- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
- resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VDU>;
- dev_mode = <2>;
- name = "rkvdec";
- };
-
- vdec_mmu: vdec_mmu {
- dbgname = "vdec";
- compatible = "rockchip,vdec_mmu";
- reg = <0x0 0xff660480 0x0 0x40>,
- <0x0 0xff6604c0 0x0 0x40>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdec_mmu";
- };
-
- iep: iep@ff670000 {
- compatible = "rockchip,iep";
- iommu_enabled = <1>;
- reg = <0x0 0xff670000 0x0 0x800>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
- clock-names = "aclk_iep", "hclk_iep";
- power-domains = <&power RK3399_PD_IEP>;
- version = <2>;
- };
-
- iep_mmu: iep-mmu {
- dbgname = "iep";
- compatible = "rockchip,iep_mmu";
- reg = <0x0 0xff670800 0x0 0x40>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "iep_mmu";
- };
-