2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
46 compatible = "rockchip,android", "rockchip,rk3399";
54 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
57 ramoops_mem: ramoops_mem {
58 reg = <0x0 0x110000 0x0 0xf0000>;
59 reg-names = "ramoops_mem";
63 compatible = "ramoops";
64 record-size = <0x0 0x20000>;
65 console-size = <0x0 0x80000>;
66 ftrace-size = <0x0 0x00000>;
67 pmsg-size = <0x0 0x50000>;
68 memory-region = <&ramoops_mem>;
71 fiq_debugger: fiq-debugger {
72 compatible = "rockchip,fiq-debugger";
73 rockchip,serial-id = <2>;
74 rockchip,signal-irq = <182>;
75 rockchip,wake-irq = <0>;
76 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
77 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
78 pinctrl-names = "default";
79 pinctrl-0 = <&uart2c_xfer>;
87 /* global autoconfigured region for contiguous allocations */
89 compatible = "shared-dma-pool";
91 size = <0x0 0x8000000>;
94 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
95 rockchip_logo: rockchip-logo@00000000 {
96 compatible = "rockchip,fb-logo";
97 reg = <0x0 0x0 0x0 0x0>;
102 compatible = "rockchip,ion";
103 #address-cells = <1>;
107 reg = <0x00000000 0x02000000>;
114 rk_key: rockchip-key {
115 compatible = "rockchip,key";
118 io-channels = <&saradc 1>;
123 rockchip,adc_value = <1>;
128 label = "volume down";
129 rockchip,adc_value = <170>;
133 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
142 rockchip,adc_value = <746>;
148 rockchip,adc_value = <355>;
154 rockchip,adc_value = <560>;
160 rockchip,adc_value = <450>;
164 cdn_dp_fb: dp-fb@fec00000 {
166 compatible = "rockchip,rk3399-cdn-dp-fb";
167 reg = <0x0 0xfec00000 0x0 0x100000>;
168 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
170 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
171 clock-names = "core-clk", "pclk", "spdif", "grf";
172 assigned-clocks = <&cru SCLK_DP_CORE>;
173 assigned-clock-rates = <100000000>;
174 power-domains = <&power RK3399_PD_HDCP>;
175 phys = <&tcphy0_dp>, <&tcphy1_dp>;
176 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
177 <&cru SRST_P_UPHY0_APB>;
178 reset-names = "spdif", "dptx", "apb";
179 rockchip,grf = <&grf>;
180 #address-cells = <1>;
182 #sound-dai-cells = <1>;
185 cdn_dp_sound: cdn-dp-sound {
187 compatible = "simple-audio-card";
188 simple-audio-card,name = "rockchip,cdn-dp-fb";
189 simple-audio-card,widgets = "Headphone", "Out Jack",
192 simple-audio-card,dai-link@0 {
201 sound-dai = <&cdn_dp_fb 0>;
206 vpu: vpu_service@ff650000 {
207 compatible = "rockchip,vpu_service";
208 rockchip,grf = <&grf>;
210 reg = <0x0 0xff650000 0x0 0x800>;
211 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
212 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
213 interrupt-names = "irq_dec", "irq_enc";
214 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
215 clock-names = "aclk_vcodec", "hclk_vcodec";
216 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
217 reset-names = "video_h", "video_a";
218 power-domains = <&power RK3399_PD_VCODEC>;
219 name = "vpu_service";
225 compatible = "rockchip,vpu_mmu";
226 reg = <0x0 0xff650800 0x0 0x40>;
227 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
228 interrupt-names = "vpu_mmu";
231 rkvdec: rkvdec@ff660000 {
232 compatible = "rockchip,rkvdec";
233 rockchip,grf = <&grf>;
235 reg = <0x0 0xff660000 0x0 0x400>;
236 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
237 interrupt-names = "irq_dec";
238 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
239 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
240 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
241 reset-names = "video_h", "video_a";
242 power-domains = <&power RK3399_PD_VDU>;
249 compatible = "rockchip,vdec_mmu";
250 reg = <0x0 0xff660480 0x0 0x40>,
251 <0x0 0xff6604c0 0x0 0x40>;
252 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
253 interrupt-names = "vdec_mmu";
257 compatible = "rockchip,iep";
259 reg = <0x0 0xff670000 0x0 0x800>;
260 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
261 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
262 clock-names = "aclk_iep", "hclk_iep";
263 power-domains = <&power RK3399_PD_IEP>;
269 compatible = "rockchip,iep_mmu";
270 reg = <0x0 0xff670800 0x0 0x40>;
271 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
272 interrupt-names = "iep_mmu";
276 compatible = "rockchip,rga2";
278 reg = <0x0 0xff680000 0x0 0x1000>;
279 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
280 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
281 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
282 power-domains = <&power RK3399_PD_RGA>;
288 compatible = "rockchip,rk-fb";
289 rockchip,disp-mode = <DUAL>;
290 rockchip,uboot-logo-on = <1>;
291 memory-region = <&rockchip_logo>;
296 compatible = "rockchip,screen";
299 vopb_rk_fb: vop-rk-fb@ff900000 {
301 compatible = "rockchip,rk3399-lcdc";
302 rockchip,prop = <PRMRY>;
303 reg = <0x0 0xff900000 0x0 0x3efc>;
304 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
305 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
306 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
307 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
308 reset-names = "axi", "ahb", "dclk";
309 rockchip,grf = <&grf>;
310 rockchip,pwr18 = <0>;
311 rockchip,iommu-enabled = <1>;
312 power-domains = <&power RK3399_PD_VOPB>;
316 vopb_mmu_rk_fb: vopb-mmu {
319 compatible = "rockchip,vopb_mmu";
320 reg = <0x0 0xff903f00 0x0 0x100>;
321 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
322 interrupt-names = "vopb_mmu";
325 vopl_rk_fb: vop-rk-fb@ff8f0000 {
327 compatible = "rockchip,rk3399-lcdc";
328 rockchip,prop = <EXTEND>;
329 reg = <0x0 0xff8f0000 0x0 0x3efc>;
330 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
331 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
332 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
333 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
334 reset-names = "axi", "ahb", "dclk";
335 rockchip,grf = <&grf>;
336 rockchip,pwr18 = <0>;
337 rockchip,iommu-enabled = <1>;
338 power-domains = <&power RK3399_PD_VOPL>;
342 vopl_mmu_rk_fb: vopl-mmu {
345 compatible = "rockchip,vopl_mmu";
346 reg = <0x0 0xff8f3f00 0x0 0x100>;
347 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
348 interrupt-names = "vopl_mmu";
352 compatible = "rockchip,rk3399-isp", "rockchip,isp";
353 reg = <0x0 0xff910000 0x0 0x10000>;
354 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
356 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
357 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
358 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
359 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
360 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
362 "clk_cif_out", "clk_cif_pll",
363 "pclk_dphytxrx", "pclk_dphy_ref",
364 "aclk_isp0_noc", "aclk_isp0_wrapper",
365 "hclk_isp0_noc", "hclk_isp0_wrapper",
366 "clk_isp0", "pclk_dphyrx";
368 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
369 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
370 "isp_flash_as_trigger_out";
371 pinctrl-0 = <&cif_clkout>;
372 pinctrl-1 = <&isp_dvp_d0d7>;
373 pinctrl-2 = <&cif_clkout>;
374 pinctrl-3 = <&isp_prelight>;
375 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
376 pinctrl-5 = <&isp_flash_trigger>;
377 rockchip,isp,mipiphy = <2>;
378 rockchip,isp,cifphy = <1>;
379 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
380 rockchip,grf = <&grf>;
381 rockchip,cru = <&cru>;
382 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
383 rockchip,isp,iommu-enable = <1>;
384 power-domains = <&power RK3399_PD_ISP0>;
390 compatible = "rockchip,isp0_mmu";
391 reg = <0x0 0xff914000 0x0 0x100>,
392 <0x0 0xff915000 0x0 0x100>;
393 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
394 interrupt-names = "isp0_mmu";
398 compatible = "rockchip,rk3399-isp", "rockchip,isp";
399 reg = <0x0 0xff920000 0x0 0x10000>;
400 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
402 <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
403 <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
404 <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
405 <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
406 <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
407 <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
408 <&cru SCLK_MIPIDPHY_CFG>;
410 "aclk_isp1_noc", "aclk_isp1_wrapper",
411 "hclk_isp1_noc", "hclk_isp1_wrapper",
412 "clk_isp1", "clk_cif_out",
413 "clk_cif_pll", "pclk_dphytxrx",
414 "pclk_dphy_ref", "pclk_isp1",
415 "pclk_dphyrx", "pclk_mipi_dsi",
418 "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
419 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
420 "isp_flash_as_trigger_out";
421 pinctrl-0 = <&cif_clkout>;
422 pinctrl-1 = <&isp_dvp_d0d7>;
423 pinctrl-2 = <&cif_clkout>;
424 pinctrl-3 = <&isp_prelight>;
425 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
426 pinctrl-5 = <&isp_flash_trigger>;
427 rockchip,isp,mipiphy = <2>;
428 rockchip,isp,cifphy = <1>;
429 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
430 rockchip,grf = <&grf>;
431 rockchip,cru = <&cru>;
432 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
433 rockchip,isp,iommu-enable = <1>;
434 power-domains = <&power RK3399_PD_ISP1>;
440 compatible = "rockchip,isp1_mmu";
441 reg = <0x0 0xff924000 0x0 0x100>,
442 <0x0 0xff925000 0x0 0x100>;
443 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
444 interrupt-names = "isp1_mmu";
447 hdmi_rk_fb: hdmi-rk-fb@ff940000 {
449 compatible = "rockchip,rk3399-hdmi";
450 reg = <0x0 0xff940000 0x0 0x20000>;
451 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
452 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
453 clocks = <&cru PCLK_HDMI_CTRL>,
455 <&cru SCLK_HDMI_CEC>,
457 <&cru SCLK_HDMI_SFR>;
458 clock-names = "pclk_hdmi",
463 resets = <&cru SRST_HDMI_CTRL>;
464 reset-names = "hdmi";
465 pinctrl-names = "default", "gpio";
466 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
467 pinctrl-1 = <&i2c3_gpio>;
468 rockchip,grf = <&grf>;
469 power-domains = <&power RK3399_PD_HDCP>;
472 mipi0_rk_fb: mipi-rk-fb@ff960000 {
473 compatible = "rockchip,rk3399-dsi";
475 rockchip,grf = <&grf>;
476 reg = <0x0 0xff960000 0x0 0x8000>;
477 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
478 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
479 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
480 power-domains = <&power RK3399_PD_VIO>;
484 mipi1_rk_fb: mipi-rk-fb@ff968000 {
485 compatible = "rockchip,rk3399-dsi";
487 rockchip,grf = <&grf>;
488 reg = <0x0 0xff968000 0x0 0x8000>;
489 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
490 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
491 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
492 power-domains = <&power RK3399_PD_VIO>;
496 edp_rk_fb: edp-rk-fb@ff970000 {
497 compatible = "rockchip,rk3399-edp-fb";
498 reg = <0x0 0xff970000 0x0 0x8000>;
499 rockchip,grf = <&grf>;
500 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
501 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
502 clock-names = "clk_edp", "pclk_edp", "clk_grf";
503 resets = <&cru SRST_P_EDP_CTRL>;
504 reset-names = "edp_apb";
506 power-domains = <&power RK3399_PD_EDP>;
512 cif_clkout: cif-clkout {
515 <2 11 RK_FUNC_3 &pcfg_pull_none>;
518 isp_dvp_d0d7: isp-dvp-d0d7 {
521 <2 0 RK_FUNC_3 &pcfg_pull_none>,
523 <2 1 RK_FUNC_3 &pcfg_pull_none>,
525 <2 2 RK_FUNC_3 &pcfg_pull_none>,
527 <2 3 RK_FUNC_3 &pcfg_pull_none>,
529 <2 4 RK_FUNC_3 &pcfg_pull_none>,
531 <2 5 RK_FUNC_3 &pcfg_pull_none>,
533 <2 6 RK_FUNC_3 &pcfg_pull_none>,
535 <2 7 RK_FUNC_3 &pcfg_pull_none>,
537 <2 8 RK_FUNC_3 &pcfg_pull_none>,
539 <2 9 RK_FUNC_3 &pcfg_pull_none>,
541 <2 10 RK_FUNC_3 &pcfg_pull_none>;
544 isp_shutter: isp-shutter {
547 <1 1 RK_FUNC_1 &pcfg_pull_none>,
549 <1 0 RK_FUNC_1 &pcfg_pull_none>;
552 isp_flash_trigger: isp-flash-trigger {
554 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
557 isp_prelight: isp-prelight {
559 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
562 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
564 rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;