1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
73 extern int pcd_init(struct platform_device *_dev);
74 extern int otg20_hcd_init(struct platform_device *_dev);
75 extern int host20_hcd_init(struct platform_device *_dev);
76 extern int pcd_remove(struct platform_device *_dev);
77 extern void hcd_remove(struct platform_device *_dev);
78 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
81 #ifdef CONFIG_RK_USB_UART
82 static u32 usb_to_uart_status;
84 /*-------------------------------------------------------------------------*/
85 /* Encapsulate the module parameter settings */
87 struct dwc_otg_driver_module_params {
91 int32_t dma_desc_enable;
92 int32_t dma_burst_size;
94 int32_t host_support_fs_ls_low_power;
95 int32_t host_ls_low_power_phy_clk;
96 int32_t enable_dynamic_fifo;
97 int32_t data_fifo_size;
98 int32_t dev_rx_fifo_size;
99 int32_t dev_nperio_tx_fifo_size;
100 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
101 int32_t host_rx_fifo_size;
102 int32_t host_nperio_tx_fifo_size;
103 int32_t host_perio_tx_fifo_size;
104 int32_t max_transfer_size;
105 int32_t max_packet_count;
106 int32_t host_channels;
107 int32_t dev_endpoints;
109 int32_t phy_utmi_width;
110 int32_t phy_ulpi_ddr;
111 int32_t phy_ulpi_ext_vbus;
115 int32_t en_multiple_tx_fifo;
116 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
118 uint32_t tx_thr_length;
119 uint32_t rx_thr_length;
124 int32_t baseline_besl;
127 int32_t ahb_thr_ratio;
137 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
139 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
141 .dma_desc_enable = 0,
142 .dma_burst_size = -1,
144 .host_support_fs_ls_low_power = -1,
145 .host_ls_low_power_phy_clk = -1,
146 .enable_dynamic_fifo = 1,
147 .data_fifo_size = -1,
148 .dev_rx_fifo_size = 0x120,
149 .dev_nperio_tx_fifo_size = 0x10,
150 .dev_perio_tx_fifo_size = {
151 /* dev_perio_tx_fifo_size_1 */
169 .host_rx_fifo_size = -1,
170 .host_nperio_tx_fifo_size = -1,
171 .host_perio_tx_fifo_size = -1,
172 .max_transfer_size = -1,
173 .max_packet_count = -1,
177 .phy_utmi_width = -1,
179 .phy_ulpi_ext_vbus = -1,
183 .en_multiple_tx_fifo = -1,
184 .dev_tx_fifo_size = {
185 /* dev_tx_fifo_size */
223 #ifdef CONFIG_USB20_HOST
224 static struct dwc_otg_driver_module_params dwc_host_module_params = {
226 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
228 .dma_desc_enable = 0,
229 .dma_burst_size = -1,
231 .host_support_fs_ls_low_power = -1,
232 .host_ls_low_power_phy_clk = -1,
233 .enable_dynamic_fifo = -1,
234 .data_fifo_size = -1,
235 .dev_rx_fifo_size = -1,
236 .dev_nperio_tx_fifo_size = -1,
237 .dev_perio_tx_fifo_size = {
238 /* dev_perio_tx_fifo_size_1 */
256 .host_rx_fifo_size = -1,
257 .host_nperio_tx_fifo_size = -1,
258 .host_perio_tx_fifo_size = -1,
259 .max_transfer_size = -1,
260 .max_packet_count = -1,
264 .phy_utmi_width = -1,
266 .phy_ulpi_ext_vbus = -1,
270 .en_multiple_tx_fifo = -1,
271 .dev_tx_fifo_size = {
272 /* dev_tx_fifo_size */
312 * This function shows the Driver Version.
314 static ssize_t version_show(struct device_driver *dev, char *buf)
316 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
320 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
323 * Global Debug Level Mask.
325 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
328 * This function shows the driver Debug Level.
330 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
332 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
336 * This function stores the driver Debug Level.
338 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
341 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
345 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
348 extern void hcd_start(dwc_otg_core_if_t *core_if);
349 extern struct usb_hub *g_dwc_otg_root_hub20;
350 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
352 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
354 dwc_otg_device_t *otg_dev = core_if->otg_dev;
355 dctl_data_t dctl = {.d32 = 0 };
358 if (core_if->op_state == A_HOST) {
359 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
362 core_if->op_state = A_HOST;
364 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
365 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
366 dctl.b.sftdiscon = 1;
367 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
369 local_irq_save(flags);
370 cil_pcd_stop(core_if);
372 * Initialize the Core for Host mode.
375 dwc_otg_core_init(core_if);
376 dwc_otg_enable_global_interrupts(core_if);
377 cil_hcd_start(core_if);
378 local_irq_restore(flags);
381 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
383 dwc_otg_device_t *otg_dev = core_if->otg_dev;
386 local_irq_save(flags);
388 if (core_if->op_state == B_PERIPHERAL) {
389 local_irq_restore(flags);
391 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
394 core_if->op_state = B_PERIPHERAL;
395 cil_hcd_stop(core_if);
396 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
397 otg_dev->pcd->phy_suspend = 1;
398 otg_dev->pcd->vbus_status = 0;
399 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
401 /* Reset the Controller */
402 dwc_otg_core_reset(core_if);
404 dwc_otg_core_init(core_if);
405 dwc_otg_disable_global_interrupts(core_if);
406 cil_pcd_start(core_if);
408 local_irq_restore(flags);
411 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
413 dwc_otg_device_t *otg_dev = g_otgdev;
414 dwc_otg_core_if_t *core_if = otg_dev->core_if;
416 return sprintf(buf, "%d\n", core_if->usb_mode);
419 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
422 int new_mode = simple_strtoul(buf, NULL, 16);
423 dwc_otg_device_t *otg_dev = g_otgdev;
424 dwc_otg_core_if_t *core_if;
425 struct dwc_otg_platform_data *pldata;
430 core_if = otg_dev->core_if;
431 pldata = otg_dev->pldata;
433 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
435 if (core_if->usb_mode == new_mode) {
439 if (pldata->phy_status == USB_PHY_SUSPEND) {
440 pldata->clock_enable(pldata, 1);
441 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
445 case USB_MODE_FORCE_HOST:
446 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
448 core_if->usb_mode = new_mode;
449 dwc_otg_force_host(core_if);
450 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
451 core_if->usb_mode = new_mode;
452 if (dwc_otg_is_host_mode(core_if))
453 dwc_otg_set_force_mode(core_if, new_mode);
455 dwc_otg_force_host(core_if);
459 case USB_MODE_FORCE_DEVICE:
460 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
461 core_if->usb_mode = new_mode;
462 dwc_otg_force_device(core_if);
463 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
464 core_if->usb_mode = new_mode;
465 if (dwc_otg_is_device_mode(core_if))
466 dwc_otg_set_force_mode(core_if, new_mode);
468 dwc_otg_force_device(core_if);
472 case USB_MODE_NORMAL:
473 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
474 core_if->usb_mode = new_mode;
475 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
476 dwc_otg_set_force_mode(core_if, new_mode);
478 if (dwc_otg_is_host_mode(core_if)) {
479 dwc_otg_force_host(core_if);
481 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
483 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
484 core_if->usb_mode = new_mode;
485 dwc_otg_set_force_mode(core_if, new_mode);
487 if (dwc_otg_is_device_mode(core_if)) {
488 dwc_otg_force_device(core_if);
499 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
500 force_usb_mode_store);
502 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
505 dwc_otg_device_t *otg_dev = g_otgdev;
506 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
507 return sprintf(_buf, "%d\n", _pcd->conn_en);
511 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
512 const char *_buf, size_t _count)
514 int enable = simple_strtoul(_buf, NULL, 10);
515 dwc_otg_device_t *otg_dev = g_otgdev;
516 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
517 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
519 _pcd->conn_en = enable;
523 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
524 dwc_otg_conn_en_store);
526 /* used for product vbus power control, SDK not need.
527 * If dwc_otg is host mode, enable vbus power.
528 * If dwc_otg is device mode, disable vbus power.
529 * return 1 - host mode, 0 - device mode.
531 int dwc_otg_usb_state(void)
533 dwc_otg_device_t *otg_dev = g_otgdev;
536 /* op_state is A_HOST */
537 if (1 == otg_dev->core_if->op_state)
539 /* op_state is B_PERIPHERAL */
540 else if (4 == otg_dev->core_if->op_state)
545 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
549 EXPORT_SYMBOL(dwc_otg_usb_state);
551 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
553 dwc_otg_device_t *otg_dev = g_otgdev;
556 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
558 return sprintf(_buf, "%d\n", 0);
561 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
563 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
565 dwc_otg_device_t *otg_dev = g_otgdev;
566 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
567 return sprintf(_buf, "%d\n", _pcd->vbus_status);
570 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
573 * This function is called during module intialization
574 * to pass module parameters to the DWC_OTG CORE.
576 static int set_parameters(dwc_otg_core_if_t *core_if,
577 struct dwc_otg_driver_module_params module_params)
582 if (module_params.otg_cap != -1) {
584 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
586 if (module_params.dma_enable != -1) {
588 dwc_otg_set_param_dma_enable(core_if,
589 module_params.dma_enable);
591 if (module_params.dma_desc_enable != -1) {
593 dwc_otg_set_param_dma_desc_enable(core_if,
594 module_params.dma_desc_enable);
596 if (module_params.opt != -1) {
597 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
599 if (module_params.dma_burst_size != -1) {
601 dwc_otg_set_param_dma_burst_size(core_if,
602 module_params.dma_burst_size);
604 if (module_params.host_support_fs_ls_low_power != -1) {
606 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
607 module_params.host_support_fs_ls_low_power);
609 if (module_params.enable_dynamic_fifo != -1) {
611 dwc_otg_set_param_enable_dynamic_fifo(core_if,
612 module_params.enable_dynamic_fifo);
614 if (module_params.data_fifo_size != -1) {
616 dwc_otg_set_param_data_fifo_size(core_if,
617 module_params.data_fifo_size);
619 if (module_params.dev_rx_fifo_size != -1) {
621 dwc_otg_set_param_dev_rx_fifo_size(core_if,
622 module_params.dev_rx_fifo_size);
624 if (module_params.dev_nperio_tx_fifo_size != -1) {
626 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
627 module_params.dev_nperio_tx_fifo_size);
629 if (module_params.host_rx_fifo_size != -1) {
631 dwc_otg_set_param_host_rx_fifo_size(core_if,
635 if (module_params.host_nperio_tx_fifo_size != -1) {
637 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
638 module_params.host_nperio_tx_fifo_size);
640 if (module_params.host_perio_tx_fifo_size != -1) {
642 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
643 module_params.host_perio_tx_fifo_size);
645 if (module_params.max_transfer_size != -1) {
647 dwc_otg_set_param_max_transfer_size(core_if,
648 module_params.max_transfer_size);
650 if (module_params.max_packet_count != -1) {
652 dwc_otg_set_param_max_packet_count(core_if,
653 module_params.max_packet_count);
655 if (module_params.host_channels != -1) {
657 dwc_otg_set_param_host_channels(core_if,
658 module_params.host_channels);
660 if (module_params.dev_endpoints != -1) {
662 dwc_otg_set_param_dev_endpoints(core_if,
663 module_params.dev_endpoints);
665 if (module_params.phy_type != -1) {
667 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
669 if (module_params.speed != -1) {
670 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
672 if (module_params.host_ls_low_power_phy_clk != -1) {
674 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
675 module_params.host_ls_low_power_phy_clk);
677 if (module_params.phy_ulpi_ddr != -1) {
679 dwc_otg_set_param_phy_ulpi_ddr(core_if,
680 module_params.phy_ulpi_ddr);
682 if (module_params.phy_ulpi_ext_vbus != -1) {
684 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
685 module_params.phy_ulpi_ext_vbus);
687 if (module_params.phy_utmi_width != -1) {
689 dwc_otg_set_param_phy_utmi_width(core_if,
690 module_params.phy_utmi_width);
692 if (module_params.ulpi_fs_ls != -1) {
694 dwc_otg_set_param_ulpi_fs_ls(core_if,
695 module_params.ulpi_fs_ls);
697 if (module_params.ts_dline != -1) {
699 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
701 if (module_params.i2c_enable != -1) {
703 dwc_otg_set_param_i2c_enable(core_if,
704 module_params.i2c_enable);
706 if (module_params.en_multiple_tx_fifo != -1) {
708 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
709 module_params.en_multiple_tx_fifo);
711 for (i = 0; i < 15; i++) {
712 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
714 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
715 module_params.dev_perio_tx_fifo_size
720 for (i = 0; i < 15; i++) {
721 if (module_params.dev_tx_fifo_size[i] != -1) {
722 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
723 module_params.dev_tx_fifo_size
727 if (module_params.thr_ctl != -1) {
729 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
731 if (module_params.mpi_enable != -1) {
733 dwc_otg_set_param_mpi_enable(core_if,
734 module_params.mpi_enable);
736 if (module_params.pti_enable != -1) {
738 dwc_otg_set_param_pti_enable(core_if,
739 module_params.pti_enable);
741 if (module_params.lpm_enable != -1) {
743 dwc_otg_set_param_lpm_enable(core_if,
744 module_params.lpm_enable);
746 if (module_params.besl_enable != -1) {
748 dwc_otg_set_param_besl_enable(core_if,
749 module_params.besl_enable);
751 if (module_params.baseline_besl != -1) {
753 dwc_otg_set_param_baseline_besl(core_if,
754 module_params.baseline_besl);
756 if (module_params.deep_besl != -1) {
758 dwc_otg_set_param_deep_besl(core_if,
759 module_params.deep_besl);
761 if (module_params.ic_usb_cap != -1) {
763 dwc_otg_set_param_ic_usb_cap(core_if,
764 module_params.ic_usb_cap);
766 if (module_params.tx_thr_length != -1) {
768 dwc_otg_set_param_tx_thr_length(core_if,
772 if (module_params.rx_thr_length != -1) {
774 dwc_otg_set_param_rx_thr_length(core_if,
775 module_params.rx_thr_length);
777 if (module_params.ahb_thr_ratio != -1) {
779 dwc_otg_set_param_ahb_thr_ratio(core_if,
783 if (module_params.power_down != -1) {
785 dwc_otg_set_param_power_down(core_if,
786 module_params.power_down);
788 if (module_params.reload_ctl != -1) {
790 dwc_otg_set_param_reload_ctl(core_if,
791 module_params.reload_ctl);
794 if (module_params.dev_out_nak != -1) {
796 dwc_otg_set_param_dev_out_nak(core_if,
797 module_params.dev_out_nak);
800 if (module_params.cont_on_bna != -1) {
802 dwc_otg_set_param_cont_on_bna(core_if,
803 module_params.cont_on_bna);
806 if (module_params.ahb_single != -1) {
808 dwc_otg_set_param_ahb_single(core_if,
809 module_params.ahb_single);
812 if (module_params.otg_ver != -1) {
814 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
816 if (module_params.adp_enable != -1) {
818 dwc_otg_set_param_adp_enable(core_if,
819 module_params.adp_enable);
825 * This function is the top level interrupt handler for the Common
826 * (Device and host modes) interrupts.
828 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
830 int32_t retval = IRQ_NONE;
832 retval = dwc_otg_handle_common_intr(dev);
834 /* S3C2410X_CLEAR_EINTPEND(); */
836 return IRQ_RETVAL(retval);
839 #ifdef CONFIG_USB20_HOST
841 * This function is called when a lm_device is unregistered with the
842 * dwc_otg_driver. This happens, for example, when the rmmod command is
843 * executed. The device may or may not be electrically present. If it is
844 * present, the driver stops device processing. Any resources used on behalf
845 * of this device are freed.
849 static int host20_driver_remove(struct platform_device *_dev)
852 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
853 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
856 /* Memory allocation for the dwc_otg_device failed. */
857 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
860 #ifndef DWC_DEVICE_ONLY
864 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
869 #ifndef DWC_HOST_ONLY
873 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
881 if (otg_dev->common_irq_installed) {
882 /* free_irq(_dev->irq, otg_dev); */
883 free_irq(platform_get_irq(_dev, 0), otg_dev);
885 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
890 if (otg_dev->core_if) {
891 dwc_otg_cil_remove(otg_dev->core_if);
893 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
898 * Remove the device attributes
900 dwc_otg_attr_remove(_dev);
905 if (otg_dev->os_dep.base) {
906 iounmap(otg_dev->os_dep.base);
911 * Clear the drvdata pointer.
914 dwc_set_device_platform_data(_dev, 0);
919 static const struct of_device_id usb20_host_of_match[] = {
922 .compatible = "rockchip,rk3188_usb20_host",
923 .data = &usb20host_pdata_rk3188,
926 .compatible = "rockchip,rk3288_usb20_host",
927 .data = &usb20host_pdata_rk3288,
930 .compatible = "rockchip,rk3036_usb20_host",
931 .data = &usb20host_pdata_rk3036,
934 .compatible = "rockchip,rk3126_usb20_host",
935 .data = &usb20host_pdata_rk3126,
941 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
944 * This function is called when an lm_device is bound to a
945 * dwc_otg_driver. It creates the driver components required to
946 * control the device (CIL, HCD, and PCD) and it initializes the
947 * device. The driver components are stored in a dwc_otg_device
948 * structure. A reference to the dwc_otg_device is saved in the
949 * lm_device. This allows the driver to access the dwc_otg_device
950 * structure on subsequent calls to driver methods for this device.
952 * @param _dev Bus device
954 static int host20_driver_probe(struct platform_device *_dev)
958 struct resource *res_base;
959 dwc_otg_device_t *dwc_otg_device;
960 struct device *dev = &_dev->dev;
961 struct device_node *node = _dev->dev.of_node;
962 struct dwc_otg_platform_data *pldata;
963 const struct of_device_id *match =
964 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
966 if (match && match->data) {
967 pldata = (void *)match->data;
970 dev_err(dev, "usb20otg match failed\n");
975 dev_err(dev, "device node not found\n");
982 if (pldata->clock_init) {
983 pldata->clock_init(pldata);
984 pldata->clock_enable(pldata, 1);
987 if (pldata->phy_suspend)
988 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
990 if (pldata->soft_reset)
991 pldata->soft_reset(pldata, RST_POR);
993 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
995 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
997 if (!dwc_otg_device) {
998 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1003 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1004 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1007 * Map the DWC_otg Core memory into virtual address space.
1010 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1012 if (!dwc_otg_device->os_dep.base) {
1013 dev_err(&_dev->dev, "ioremap() failed\n");
1014 DWC_FREE(dwc_otg_device);
1018 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1020 /* Set device flags indicating whether the HCD supports DMA. */
1021 if (!_dev->dev.dma_mask)
1022 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1023 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1028 * Initialize driver data to point to the global DWC_otg
1032 dwc_set_device_platform_data(_dev, dwc_otg_device);
1033 pldata->privdata = dwc_otg_device;
1034 dwc_otg_device->pldata = (void *)pldata;
1036 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1038 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1040 if (!dwc_otg_device->core_if) {
1041 dev_err(&_dev->dev, "CIL initialization failed!\n");
1046 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1049 * Attempt to ensure this device is really a DWC_otg Controller.
1050 * Read and verify the SNPSID register contents. The value should be
1051 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1052 * as in "OTG version 2.XX" or "OTG version 3.XX".
1055 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1057 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1059 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1060 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1066 * Validate parameter values.
1068 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1074 * Create Device Attributes in sysfs
1076 dwc_otg_attr_create(_dev);
1079 * Disable the global interrupt until all the interrupt
1080 * handlers are installed.
1082 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1085 * Install the interrupt handler for the common interrupts before
1086 * enabling common interrupts in core_init below.
1088 irq = platform_get_irq(_dev, 0);
1089 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1090 retval = request_irq(irq, dwc_otg_common_irq,
1091 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1093 DWC_ERROR("request of irq%d failed\n", irq);
1097 dwc_otg_device->common_irq_installed = 1;
1101 * Initialize the DWC_otg core.
1102 * In order to reduce the time of initialization,
1103 * we do core soft reset after connection detected.
1105 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1108 * Initialize the HCD
1110 retval = host20_hcd_init(_dev);
1112 DWC_ERROR("hcd_init failed\n");
1113 dwc_otg_device->hcd = NULL;
1117 clk_set_rate(pldata->phyclk_480m, 480000000);
1119 * Enable the global interrupt after all the interrupt
1120 * handlers are installed if there is no ADP support else
1121 * perform initial actions required for Internal ADP logic.
1123 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1124 if (pldata->phy_status == USB_PHY_ENABLED) {
1125 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1127 pldata->clock_enable(pldata, 0);
1129 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1131 dwc_otg_adp_start(dwc_otg_device->core_if,
1132 dwc_otg_is_host_mode(dwc_otg_device->
1138 host20_driver_remove(_dev);
1140 if (pldata->clock_enable)
1141 pldata->clock_enable(pldata, 0);
1147 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1153 static int dwc_otg_driver_resume(struct platform_device *_dev)
1158 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1160 struct device *dev = &_dev->dev;
1161 dwc_otg_device_t *otg_dev = dev->platform_data;
1162 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1163 struct dwc_otg_platform_data *pldata = otg_dev->pldata;
1164 dctl_data_t dctl = {.d32 = 0 };
1165 dwc_otg_pcd_t *pcd = core_if->otg_dev->pcd;
1167 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1168 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1170 if (dwc_otg_is_host_mode(core_if)) {
1171 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1172 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1174 cancel_delayed_work_sync(&pcd->check_vbus_work);
1175 /* soft disconnect */
1177 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1178 dctl.b.sftdiscon = 1;
1179 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1182 /* Clear any pending interrupts */
1183 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1185 if (pldata->dwc_otg_uart_mode != NULL)
1186 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1187 if (pldata->phy_suspend != NULL)
1188 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1193 * This structure defines the methods to be called by a bus driver
1194 * during the lifecycle of a device on that bus. Both drivers and
1195 * devices are registered with a bus driver. The bus driver matches
1196 * devices to drivers based on information in the device and driver
1199 * The probe function is called when the bus driver matches a device
1200 * to this driver. The remove function is called when a device is
1201 * unregistered with the bus driver.
1203 #ifdef CONFIG_USB20_HOST
1204 static struct platform_driver dwc_host_driver = {
1206 .name = (char *)dwc_host20_driver_name,
1207 .of_match_table = of_match_ptr(usb20_host_of_match),
1209 .probe = host20_driver_probe,
1210 .remove = host20_driver_remove,
1211 .suspend = dwc_otg_driver_suspend,
1212 .resume = dwc_otg_driver_resume,
1216 #ifdef CONFIG_USB20_OTG
1218 * This function is called when a lm_device is unregistered with the
1219 * dwc_otg_driver. This happens, for example, when the rmmod command is
1220 * executed. The device may or may not be electrically present. If it is
1221 * present, the driver stops device processing. Any resources used on behalf
1222 * of this device are freed.
1226 static int otg20_driver_remove(struct platform_device *_dev)
1229 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1230 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1233 /* Memory allocation for the dwc_otg_device failed. */
1234 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1237 #ifndef DWC_DEVICE_ONLY
1241 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1246 #ifndef DWC_HOST_ONLY
1250 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1257 if (otg_dev->common_irq_installed) {
1258 /* free_irq(_dev->irq, otg_dev); */
1259 free_irq(platform_get_irq(_dev, 0), otg_dev);
1261 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1266 if (otg_dev->core_if) {
1267 dwc_otg_cil_remove(otg_dev->core_if);
1269 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1274 * Remove the device attributes
1276 dwc_otg_attr_remove(_dev);
1279 * Return the memory.
1281 if (otg_dev->os_dep.base)
1282 iounmap(otg_dev->os_dep.base);
1286 * Clear the drvdata pointer.
1289 dwc_set_device_platform_data(_dev, 0);
1294 static const struct of_device_id usb20_otg_of_match[] = {
1297 .compatible = "rockchip,rk3188_usb20_otg",
1298 .data = &usb20otg_pdata_rk3188,
1301 .compatible = "rockchip,rk3288_usb20_otg",
1302 .data = &usb20otg_pdata_rk3288,
1305 .compatible = "rockchip,rk3036_usb20_otg",
1306 .data = &usb20otg_pdata_rk3036,
1309 .compatible = "rockchip,rk3126_usb20_otg",
1310 .data = &usb20otg_pdata_rk3126,
1315 .compatible = "rockchip,rk3368-usb",
1316 .data = &usb20otg_pdata_rk3368,
1322 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1325 * This function is called when an lm_device is bound to a
1326 * dwc_otg_driver. It creates the driver components required to
1327 * control the device (CIL, HCD, and PCD) and it initializes the
1328 * device. The driver components are stored in a dwc_otg_device
1329 * structure. A reference to the dwc_otg_device is saved in the
1330 * lm_device. This allows the driver to access the dwc_otg_device
1331 * structure on subsequent calls to driver methods for this device.
1333 * @param _dev Bus device
1335 static int otg20_driver_probe(struct platform_device *_dev)
1340 struct resource *res_base;
1341 dwc_otg_device_t *dwc_otg_device;
1342 struct device *dev = &_dev->dev;
1343 struct device_node *node = _dev->dev.of_node;
1344 struct dwc_otg_platform_data *pldata;
1345 const struct of_device_id *match =
1346 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1348 if (match && match->data) {
1349 pldata = (void *)match->data;
1352 dev_err(dev, "usb20otg match failed\n");
1357 dev_err(dev, "device node not found\n");
1361 if (pldata->hw_init)
1364 if (pldata->clock_init) {
1365 pldata->clock_init(pldata);
1366 pldata->clock_enable(pldata, 1);
1369 if (pldata->phy_suspend)
1370 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1372 if (pldata->dwc_otg_uart_mode)
1373 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1375 /* do reset later, because reset need about
1376 * 100ms to ensure otg id state change.
1379 if(pldata->soft_reset)
1380 pldata->soft_reset();
1384 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1386 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1388 if (!dwc_otg_device) {
1389 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1394 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1395 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1398 * Map the DWC_otg Core memory into virtual address space.
1401 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1403 if (!dwc_otg_device->os_dep.base) {
1404 dev_err(&_dev->dev, "ioremap() failed\n");
1405 DWC_FREE(dwc_otg_device);
1409 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1411 /* Set device flags indicating whether the HCD supports DMA. */
1412 if (!_dev->dev.dma_mask)
1413 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1414 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1419 * Initialize driver data to point to the global DWC_otg
1423 g_otgdev = dwc_otg_device;
1424 dwc_otg_dev = (struct device *)&_dev->dev;
1425 pldata->privdata = dwc_otg_device;
1426 dwc_otg_device->pldata = pldata;
1428 dwc_set_device_platform_data(_dev, dwc_otg_device);
1430 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1432 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1433 if (!dwc_otg_device->core_if) {
1434 dev_err(&_dev->dev, "CIL initialization failed!\n");
1439 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1441 * Attempt to ensure this device is really a DWC_otg Controller.
1442 * Read and verify the SNPSID register contents. The value should be
1443 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1444 * as in "OTG version 2.XX" or "OTG version 3.XX".
1447 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1449 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1451 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1452 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1458 * Validate parameter values.
1460 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1466 * Create Device Attributes in sysfs
1468 dwc_otg_attr_create(_dev);
1471 * Disable the global interrupt until all the interrupt
1472 * handlers are installed.
1474 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1477 * Install the interrupt handler for the common interrupts before
1478 * enabling common interrupts in core_init below.
1480 irq = platform_get_irq(_dev, 0);
1481 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1482 retval = request_irq(irq, dwc_otg_common_irq,
1483 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1485 DWC_ERROR("request of irq%d failed\n", irq);
1489 dwc_otg_device->common_irq_installed = 1;
1493 * Initialize the DWC_otg core.
1494 * In order to reduce the time of initialization,
1495 * we do core soft reset after connection detected.
1497 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1500 * 0 - USB_MODE_NORMAL
1501 * 1 - USB_MODE_FORCE_HOST
1502 * 2 - USB_MODE_FORCE_DEVICE
1504 of_property_read_u32(node, "rockchip,usb-mode", &val);
1505 dwc_otg_device->core_if->usb_mode = val;
1507 #ifndef DWC_HOST_ONLY
1509 * Initialize the PCD
1511 retval = pcd_init(_dev);
1513 DWC_ERROR("pcd_init failed\n");
1514 dwc_otg_device->pcd = NULL;
1518 #ifndef DWC_DEVICE_ONLY
1520 * Initialize the HCD
1522 retval = otg20_hcd_init(_dev);
1524 DWC_ERROR("hcd_init failed\n");
1525 dwc_otg_device->hcd = NULL;
1530 * Enable the global interrupt after all the interrupt
1531 * handlers are installed if there is no ADP support else
1532 * perform initial actions required for Internal ADP logic.
1534 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1535 if (dwc_otg_device->core_if->usb_mode == USB_MODE_NORMAL &&
1536 pldata->phy_status == USB_PHY_ENABLED) {
1537 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1539 pldata->clock_enable(pldata, 0);
1541 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1543 dwc_otg_adp_start(dwc_otg_device->core_if,
1544 dwc_otg_is_host_mode(dwc_otg_device->
1550 otg20_driver_remove(_dev);
1553 if (pldata->clock_enable)
1554 pldata->clock_enable(pldata, 0);
1560 static int dwc_otg_pm_suspend(struct device *dev)
1562 dwc_otg_device_t *dwc_otg_device;
1563 struct dwc_otg_platform_data *pdata_otg;
1565 dwc_otg_device = dev_get_platdata(dev);
1567 dev_dbg(dev, "dwc_otg PM suspend\n");
1569 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1572 pdata_otg = dwc_otg_device->pldata;
1573 pdata_otg->phy_suspend(pdata_otg, USB_PHY_SUSPEND);
1578 static int dwc_otg_pm_resume(struct device *dev)
1580 dwc_otg_device_t *dwc_otg_device;
1581 struct dwc_otg_platform_data *pdata_otg;
1583 dwc_otg_device = dev_get_platdata(dev);
1585 dev_dbg(dev, "dwc_otg PM resume\n");
1587 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1590 pdata_otg = dwc_otg_device->pldata;
1591 pdata_otg->phy_suspend(pdata_otg, USB_PHY_ENABLED);
1596 #define dwc_otg_pm_suspend NULL
1597 #define dwc_otg_pm_resume NULL
1600 static const struct dev_pm_ops dwc_otg_dev_pm_ops = {
1601 .suspend = dwc_otg_pm_suspend,
1602 .resume = dwc_otg_pm_resume,
1605 static struct platform_driver dwc_otg_driver = {
1607 .name = (char *)dwc_otg20_driver_name,
1608 .of_match_table = of_match_ptr(usb20_otg_of_match),
1610 .pm = &dwc_otg_dev_pm_ops,
1613 .probe = otg20_driver_probe,
1614 .remove = otg20_driver_remove,
1615 .suspend = dwc_otg_driver_suspend,
1616 .resume = dwc_otg_driver_resume,
1617 .shutdown = dwc_otg_driver_shutdown,
1621 void rk_usb_power_up(void)
1623 struct dwc_otg_platform_data *pldata_otg;
1624 #ifdef CONFIG_USB20_HOST
1625 struct dwc_otg_platform_data *pldata_host;
1627 #ifdef CONFIG_USB_EHCI_RK
1628 struct rkehci_platform_data *pldata_ehci;
1631 if (is_rk3288_usb()) {
1632 #ifdef CONFIG_RK_USB_UART
1633 /* enable USB bypass UART function */
1634 writel_relaxed(0x00c00000 | usb_to_uart_status,
1635 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1638 /* unset siddq,the analog blocks are powered up */
1639 #ifdef CONFIG_USB20_OTG
1640 pldata_otg = &usb20otg_pdata_rk3288;
1642 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1643 writel_relaxed((0x01 << 13) << 16,
1645 RK3288_GRF_UOC0_CON0);
1648 #ifdef CONFIG_USB20_HOST
1649 pldata_host = &usb20host_pdata_rk3288;
1651 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1652 writel_relaxed((0x01 << 13) << 16,
1654 RK3288_GRF_UOC2_CON0);
1657 #ifdef CONFIG_USB_EHCI_RK
1658 pldata_ehci = &rkehci_pdata_rk3288;
1660 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1661 writel_relaxed((0x01 << 13) << 16,
1663 RK3288_GRF_UOC1_CON0);
1668 dwc_otg_device_t *otg_dev = g_otgdev;
1673 pldata_otg = otg_dev->pldata;
1674 if (pldata_otg && pldata_otg->phy_power_down)
1675 pldata_otg->phy_power_down(PHY_POWER_UP);
1679 void rk_usb_power_down(void)
1681 struct dwc_otg_platform_data *pldata_otg;
1682 #ifdef CONFIG_USB20_HOST
1683 struct dwc_otg_platform_data *pldata_host;
1685 #ifdef CONFIG_USB_EHCI_RK
1686 struct rkehci_platform_data *pldata_ehci;
1689 if (is_rk3288_usb()) {
1690 #ifdef CONFIG_RK_USB_UART
1691 /* disable USB bypass UART function */
1692 usb_to_uart_status =
1693 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1694 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1696 /* set siddq,the analog blocks are powered down
1698 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1699 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1700 * and TESTBURNIN are set to 1'b0.
1701 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1702 #ifdef CONFIG_USB20_OTG
1703 pldata_otg = &usb20otg_pdata_rk3288;
1705 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1706 writel_relaxed((0x01 << 13) |
1707 ((0x01 << 13) << 16),
1709 RK3288_GRF_UOC0_CON0);
1712 #ifdef CONFIG_USB20_HOST
1713 pldata_host = &usb20host_pdata_rk3288;
1715 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1716 writel_relaxed((0x01 << 13) |
1717 ((0x01 << 13) << 16),
1719 RK3288_GRF_UOC2_CON0);
1722 #ifdef CONFIG_USB_EHCI_RK
1723 pldata_ehci = &rkehci_pdata_rk3288;
1725 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1726 writel_relaxed((0x01 << 13) |
1727 ((0x01 << 13) << 16),
1729 RK3288_GRF_UOC1_CON0);
1733 dwc_otg_device_t *otg_dev = g_otgdev;
1738 pldata_otg = otg_dev->pldata;
1739 if (pldata_otg && pldata_otg->phy_power_down)
1740 pldata_otg->phy_power_down(PHY_POWER_DOWN);
1744 EXPORT_SYMBOL(rk_usb_power_up);
1745 EXPORT_SYMBOL(rk_usb_power_down);
1747 * This function is called when the dwc_otg_driver is installed with the
1748 * insmod command. It registers the dwc_otg_driver structure with the
1749 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1750 * to be called. In addition, the bus driver will automatically expose
1751 * attributes defined for the device and driver in the special sysfs file
1756 static int __init dwc_otg_driver_init(void)
1761 #ifdef CONFIG_USB20_OTG
1762 /* register otg20 */
1763 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1764 DWC_DRIVER_VERSION);
1766 retval = platform_driver_register(&dwc_otg_driver);
1768 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1773 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1775 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1777 driver_create_file(&dwc_otg_driver.driver,
1778 &driver_attr_dwc_otg_conn_en);
1780 driver_create_file(&dwc_otg_driver.driver,
1781 &driver_attr_vbus_status);
1783 driver_create_file(&dwc_otg_driver.driver,
1784 &driver_attr_force_usb_mode);
1786 driver_create_file(&dwc_otg_driver.driver,
1787 &driver_attr_op_state);
1791 /* register host20 */
1792 #ifdef CONFIG_USB20_HOST
1793 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1794 DWC_DRIVER_VERSION);
1796 retval = platform_driver_register(&dwc_host_driver);
1798 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1803 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1805 driver_create_file(&dwc_host_driver.driver,
1806 &driver_attr_debuglevel);
1811 module_init(dwc_otg_driver_init);
1814 * This function is called when the driver is removed from the kernel
1815 * with the rmmod command. The driver unregisters itself with its bus
1819 static void __exit dwc_otg_driver_cleanup(void)
1821 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1823 #ifdef CONFIG_USB20_HOST
1825 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1826 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1827 platform_driver_unregister(&dwc_host_driver);
1828 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1831 #ifdef CONFIG_USB20_OTG
1833 driver_remove_file(&dwc_otg_driver.driver,
1834 &driver_attr_dwc_otg_conn_en);
1835 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1836 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1837 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1838 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1839 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1840 platform_driver_unregister(&dwc_otg_driver);
1841 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1845 module_exit(dwc_otg_driver_cleanup);
1847 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1848 MODULE_AUTHOR("Synopsys Inc.");
1849 MODULE_LICENSE("GPL");
1851 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1852 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1853 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1854 MODULE_PARM_DESC(opt, "OPT Mode");
1855 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1856 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1858 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1860 MODULE_PARM_DESC(dma_desc_enable,
1861 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1863 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1865 MODULE_PARM_DESC(dma_burst_size,
1866 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1867 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1868 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1869 module_param_named(host_support_fs_ls_low_power,
1870 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1872 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1873 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1874 module_param_named(host_ls_low_power_phy_clk,
1875 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1876 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1877 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1878 module_param_named(enable_dynamic_fifo,
1879 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1880 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1881 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1883 MODULE_PARM_DESC(data_fifo_size,
1884 "Total number of words in the data FIFO memory 32-32768");
1885 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1887 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1888 module_param_named(dev_nperio_tx_fifo_size,
1889 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1890 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1891 "Number of words in the non-periodic Tx FIFO 16-32768");
1892 module_param_named(dev_perio_tx_fifo_size_1,
1893 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1894 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1895 "Number of words in the periodic Tx FIFO 4-768");
1896 module_param_named(dev_perio_tx_fifo_size_2,
1897 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1898 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1899 "Number of words in the periodic Tx FIFO 4-768");
1900 module_param_named(dev_perio_tx_fifo_size_3,
1901 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1902 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1903 "Number of words in the periodic Tx FIFO 4-768");
1904 module_param_named(dev_perio_tx_fifo_size_4,
1905 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1906 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1907 "Number of words in the periodic Tx FIFO 4-768");
1908 module_param_named(dev_perio_tx_fifo_size_5,
1909 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1910 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1911 "Number of words in the periodic Tx FIFO 4-768");
1912 module_param_named(dev_perio_tx_fifo_size_6,
1913 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1914 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1915 "Number of words in the periodic Tx FIFO 4-768");
1916 module_param_named(dev_perio_tx_fifo_size_7,
1917 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1918 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1919 "Number of words in the periodic Tx FIFO 4-768");
1920 module_param_named(dev_perio_tx_fifo_size_8,
1921 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1922 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1923 "Number of words in the periodic Tx FIFO 4-768");
1924 module_param_named(dev_perio_tx_fifo_size_9,
1925 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1926 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1927 "Number of words in the periodic Tx FIFO 4-768");
1928 module_param_named(dev_perio_tx_fifo_size_10,
1929 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1930 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1931 "Number of words in the periodic Tx FIFO 4-768");
1932 module_param_named(dev_perio_tx_fifo_size_11,
1933 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1934 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1935 "Number of words in the periodic Tx FIFO 4-768");
1936 module_param_named(dev_perio_tx_fifo_size_12,
1937 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1938 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1939 "Number of words in the periodic Tx FIFO 4-768");
1940 module_param_named(dev_perio_tx_fifo_size_13,
1941 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1942 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1943 "Number of words in the periodic Tx FIFO 4-768");
1944 module_param_named(dev_perio_tx_fifo_size_14,
1945 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1946 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1947 "Number of words in the periodic Tx FIFO 4-768");
1948 module_param_named(dev_perio_tx_fifo_size_15,
1949 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1950 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1951 "Number of words in the periodic Tx FIFO 4-768");
1952 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1954 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1955 module_param_named(host_nperio_tx_fifo_size,
1956 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1957 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1958 "Number of words in the non-periodic Tx FIFO 16-32768");
1959 module_param_named(host_perio_tx_fifo_size,
1960 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1961 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1962 "Number of words in the host periodic Tx FIFO 16-32768");
1963 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1965 /** @todo Set the max to 512K, modify checks */
1966 MODULE_PARM_DESC(max_transfer_size,
1967 "The maximum transfer size supported in bytes 2047-65535");
1968 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1970 MODULE_PARM_DESC(max_packet_count,
1971 "The maximum number of packets in a transfer 15-511");
1972 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1974 MODULE_PARM_DESC(host_channels,
1975 "The number of host channel registers to use 1-16");
1976 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1978 MODULE_PARM_DESC(dev_endpoints,
1979 "The number of endpoints in addition to EP0 available for device mode 1-15");
1980 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1981 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1982 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1984 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1985 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1986 MODULE_PARM_DESC(phy_ulpi_ddr,
1987 "ULPI at double or single data rate 0=Single 1=Double");
1988 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1990 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1991 "ULPI PHY using internal or external vbus 0=Internal");
1992 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1993 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1994 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1995 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1996 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1997 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1998 module_param_named(debug, g_dbg_lvl, int, 0444);
1999 MODULE_PARM_DESC(debug, "");
2001 module_param_named(en_multiple_tx_fifo,
2002 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
2003 MODULE_PARM_DESC(en_multiple_tx_fifo,
2004 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
2005 module_param_named(dev_tx_fifo_size_1,
2006 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
2007 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
2008 module_param_named(dev_tx_fifo_size_2,
2009 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
2010 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
2011 module_param_named(dev_tx_fifo_size_3,
2012 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
2013 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
2014 module_param_named(dev_tx_fifo_size_4,
2015 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
2016 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
2017 module_param_named(dev_tx_fifo_size_5,
2018 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
2019 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2020 module_param_named(dev_tx_fifo_size_6,
2021 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2022 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2023 module_param_named(dev_tx_fifo_size_7,
2024 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2025 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2026 module_param_named(dev_tx_fifo_size_8,
2027 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2028 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2029 module_param_named(dev_tx_fifo_size_9,
2030 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2031 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2032 module_param_named(dev_tx_fifo_size_10,
2033 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2034 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2035 module_param_named(dev_tx_fifo_size_11,
2036 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2037 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2038 module_param_named(dev_tx_fifo_size_12,
2039 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2040 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2041 module_param_named(dev_tx_fifo_size_13,
2042 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2043 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2044 module_param_named(dev_tx_fifo_size_14,
2045 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2046 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2047 module_param_named(dev_tx_fifo_size_15,
2048 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2049 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2051 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2052 MODULE_PARM_DESC(thr_ctl,
2053 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2054 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2056 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2057 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2059 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2061 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2062 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2063 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2064 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2066 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2067 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2068 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2070 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2071 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2072 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2074 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2075 MODULE_PARM_DESC(ic_usb_cap,
2076 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2077 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2079 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2080 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2081 MODULE_PARM_DESC(power_down, "Power Down Mode");
2082 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2083 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2084 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2085 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2086 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2087 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2088 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2089 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2090 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2091 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2092 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2093 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2095 /** @page "Module Parameters"
2097 * The following parameters may be specified when starting the module.
2098 * These parameters define how the DWC_otg controller should be
2099 * configured. Parameter values are passed to the CIL initialization
2100 * function dwc_otg_cil_init
2102 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2106 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2110 <td>Specifies the OTG capabilities. The driver will automatically detect the
2111 value for this parameter if none is specified.
2112 - 0: HNP and SRP capable (default, if available)
2113 - 1: SRP Only capable
2114 - 2: No HNP/SRP capable
2119 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2120 The driver will automatically detect the value for this parameter if none is
2123 - 1: DMA (default, if available)
2127 <td>dma_burst_size</td>
2128 <td>The DMA Burst size (applicable only for External DMA Mode).
2129 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2134 <td>Specifies the maximum speed of operation in host and device mode. The
2135 actual speed depends on the speed of the attached device and the value of
2137 - 0: High Speed (default)
2142 <td>host_support_fs_ls_low_power</td>
2143 <td>Specifies whether low power mode is supported when attached to a Full
2144 Speed or Low Speed device in host mode.
2145 - 0: Don't support low power mode (default)
2146 - 1: Support low power mode
2150 <td>host_ls_low_power_phy_clk</td>
2151 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2152 Speed device in host mode. This parameter is applicable only if
2153 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2154 - 0: 48 MHz (default)
2159 <td>enable_dynamic_fifo</td>
2160 <td> Specifies whether FIFOs may be resized by the driver software.
2161 - 0: Use cC FIFO size parameters
2162 - 1: Allow dynamic FIFO sizing (default)
2166 <td>data_fifo_size</td>
2167 <td>Total number of 4-byte words in the data FIFO memory. This memory
2168 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2169 - Values: 32 to 32768 (default 8192)
2171 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2175 <td>dev_rx_fifo_size</td>
2176 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2177 FIFO sizing is enabled.
2178 - Values: 16 to 32768 (default 1064)
2182 <td>dev_nperio_tx_fifo_size</td>
2183 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2184 dynamic FIFO sizing is enabled.
2185 - Values: 16 to 32768 (default 1024)
2189 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2190 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2191 when dynamic FIFO sizing is enabled.
2192 - Values: 4 to 768 (default 256)
2196 <td>host_rx_fifo_size</td>
2197 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2199 - Values: 16 to 32768 (default 1024)
2203 <td>host_nperio_tx_fifo_size</td>
2204 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2205 dynamic FIFO sizing is enabled in the core.
2206 - Values: 16 to 32768 (default 1024)
2210 <td>host_perio_tx_fifo_size</td>
2211 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2213 - Values: 16 to 32768 (default 1024)
2217 <td>max_transfer_size</td>
2218 <td>The maximum transfer size supported in bytes.
2219 - Values: 2047 to 65,535 (default 65,535)
2223 <td>max_packet_count</td>
2224 <td>The maximum number of packets in a transfer.
2225 - Values: 15 to 511 (default 511)
2229 <td>host_channels</td>
2230 <td>The number of host channel registers to use.
2231 - Values: 1 to 16 (default 12)
2233 Note: The FPGA configuration supports a maximum of 12 host channels.
2237 <td>dev_endpoints</td>
2238 <td>The number of endpoints in addition to EP0 available for device mode
2240 - Values: 1 to 15 (default 6 IN and OUT)
2242 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2248 <td>Specifies the type of PHY interface to use. By default, the driver will
2249 automatically detect the phy_type.
2251 - 1: UTMI+ (default, if available)
2256 <td>phy_utmi_width</td>
2257 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2258 phy_type of UTMI+. Also, this parameter is applicable only if the
2259 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2260 core has been configured to work at either data path width.
2261 - Values: 8 or 16 bits (default 16)
2265 <td>phy_ulpi_ddr</td>
2266 <td>Specifies whether the ULPI operates at double or single data rate. This
2267 parameter is only applicable if phy_type is ULPI.
2268 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2269 - 1: double data rate ULPI interface with 4 bit wide data bus
2274 <td>Specifies whether to use the I2C interface for full speed PHY. This
2275 parameter is only applicable if PHY_TYPE is FS.
2276 - 0: Disabled (default)
2282 <td>Specifies whether to use ULPI FS/LS mode only.
2283 - 0: Disabled (default)
2289 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2290 - 0: Disabled (default)
2295 <td>en_multiple_tx_fifo</td>
2296 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2297 The driver will automatically detect the value for this parameter if none is
2300 - 1: Enabled (default, if available)
2304 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2305 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2306 when dynamic FIFO sizing is enabled.
2307 - Values: 4 to 768 (default 256)
2311 <td>tx_thr_length</td>
2312 <td>Transmit Threshold length in 32 bit double words
2313 - Values: 8 to 128 (default 64)
2317 <td>rx_thr_length</td>
2318 <td>Receive Threshold length in 32 bit double words
2319 - Values: 8 to 128 (default 64)
2324 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2325 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2326 Rx transfers accordingly.
2327 The driver will automatically detect the value for this parameter if none is
2329 - Values: 0 to 7 (default 0)
2330 Bit values indicate:
2331 - 0: Thresholding disabled
2332 - 1: Thresholding enabled
2336 <td>dma_desc_enable</td>
2337 <td>Specifies whether to enable Descriptor DMA mode.
2338 The driver will automatically detect the value for this parameter if none is
2340 - 0: Descriptor DMA disabled
2341 - 1: Descriptor DMA (default, if available)
2346 <td>Specifies whether to enable MPI enhancement mode.
2347 The driver will automatically detect the value for this parameter if none is
2349 - 0: MPI disabled (default)
2355 <td>Specifies whether to enable PTI enhancement support.
2356 The driver will automatically detect the value for this parameter if none is
2358 - 0: PTI disabled (default)
2364 <td>Specifies whether to enable LPM support.
2365 The driver will automatically detect the value for this parameter if none is
2368 - 1: LPM enable (default, if available)
2372 <td>besl_enable</td>
2373 <td>Specifies whether to enable LPM Errata support.
2374 The driver will automatically detect the value for this parameter if none is
2376 - 0: LPM Errata disabled (default)
2377 - 1: LPM Errata enable
2381 <td>baseline_besl</td>
2382 <td>Specifies the baseline besl value.
2383 - Values: 0 to 15 (default 0)
2388 <td>Specifies the deep besl value.
2389 - Values: 0 to 15 (default 15)
2394 <td>Specifies whether to enable IC_USB capability.
2395 The driver will automatically detect the value for this parameter if none is
2397 - 0: IC_USB disabled (default, if available)
2402 <td>ahb_thr_ratio</td>
2403 <td>Specifies AHB Threshold ratio.
2404 - Values: 0 to 3 (default 0)
2409 <td>Specifies Power Down(Hibernation) Mode.
2410 The driver will automatically detect the value for this parameter if none is
2412 - 0: Power Down disabled (default)
2413 - 2: Power Down enabled
2418 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2419 run time. The driver will automatically detect the value for this parameter if
2420 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2421 the core might misbehave.
2422 - 0: Reload Control disabled (default)
2423 - 1: Reload Control enabled
2427 <td>dev_out_nak</td>
2428 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2429 The driver will automatically detect the value for this parameter if
2430 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2431 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2432 - 1: The core sets NAK after Bulk OUT transfer complete
2436 <td>cont_on_bna</td>
2437 <td>Specifies whether Enable Continue on BNA enabled or no.
2438 After receiving BNA interrupt the core disables the endpoint,when the
2439 endpoint is re-enabled by the application the
2440 - 0: Core starts processing from the DOEPDMA descriptor (default)
2441 - 1: Core starts processing from the descriptor which received the BNA.
2442 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2447 <td>This bit when programmed supports SINGLE transfers for remainder data
2448 in a transfer for DMA mode of operation.
2449 - 0: The remainder data will be sent using INCR burst size (default)
2450 - 1: The remainder data will be sent using SINGLE burst size.
2455 <td>Specifies whether ADP feature is enabled.
2456 The driver will automatically detect the value for this parameter if none is
2458 - 0: ADP feature disabled (default)
2459 - 1: ADP feature enabled
2464 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2466 - 0: OTG 2.0 support disabled (default)
2467 - 1: OTG 2.0 support enabled