1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
73 extern int pcd_init(struct platform_device *_dev);
74 extern int otg20_hcd_init(struct platform_device *_dev);
75 extern int host20_hcd_init(struct platform_device *_dev);
76 extern int pcd_remove(struct platform_device *_dev);
77 extern void hcd_remove(struct platform_device *_dev);
78 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
81 #ifdef CONFIG_RK_USB_UART
82 static u32 usb_to_uart_status;
84 /*-------------------------------------------------------------------------*/
85 /* Encapsulate the module parameter settings */
87 struct dwc_otg_driver_module_params {
91 int32_t dma_desc_enable;
92 int32_t dma_burst_size;
94 int32_t host_support_fs_ls_low_power;
95 int32_t host_ls_low_power_phy_clk;
96 int32_t enable_dynamic_fifo;
97 int32_t data_fifo_size;
98 int32_t dev_rx_fifo_size;
99 int32_t dev_nperio_tx_fifo_size;
100 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
101 int32_t host_rx_fifo_size;
102 int32_t host_nperio_tx_fifo_size;
103 int32_t host_perio_tx_fifo_size;
104 int32_t max_transfer_size;
105 int32_t max_packet_count;
106 int32_t host_channels;
107 int32_t dev_endpoints;
109 int32_t phy_utmi_width;
110 int32_t phy_ulpi_ddr;
111 int32_t phy_ulpi_ext_vbus;
115 int32_t en_multiple_tx_fifo;
116 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
118 uint32_t tx_thr_length;
119 uint32_t rx_thr_length;
124 int32_t baseline_besl;
127 int32_t ahb_thr_ratio;
137 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
139 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
141 .dma_desc_enable = 0,
142 .dma_burst_size = -1,
144 .host_support_fs_ls_low_power = -1,
145 .host_ls_low_power_phy_clk = -1,
146 .enable_dynamic_fifo = 1,
147 .data_fifo_size = -1,
148 .dev_rx_fifo_size = 0x120,
149 .dev_nperio_tx_fifo_size = 0x10,
150 .dev_perio_tx_fifo_size = {
151 /* dev_perio_tx_fifo_size_1 */
169 .host_rx_fifo_size = -1,
170 .host_nperio_tx_fifo_size = -1,
171 .host_perio_tx_fifo_size = -1,
172 .max_transfer_size = -1,
173 .max_packet_count = -1,
177 .phy_utmi_width = -1,
179 .phy_ulpi_ext_vbus = -1,
183 .en_multiple_tx_fifo = -1,
184 .dev_tx_fifo_size = {
185 /* dev_tx_fifo_size */
223 #ifdef CONFIG_USB20_HOST
224 static struct dwc_otg_driver_module_params dwc_host_module_params = {
226 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
228 .dma_desc_enable = 0,
229 .dma_burst_size = -1,
231 .host_support_fs_ls_low_power = -1,
232 .host_ls_low_power_phy_clk = -1,
233 .enable_dynamic_fifo = -1,
234 .data_fifo_size = -1,
235 .dev_rx_fifo_size = -1,
236 .dev_nperio_tx_fifo_size = -1,
237 .dev_perio_tx_fifo_size = {
238 /* dev_perio_tx_fifo_size_1 */
256 .host_rx_fifo_size = -1,
257 .host_nperio_tx_fifo_size = -1,
258 .host_perio_tx_fifo_size = -1,
259 .max_transfer_size = -1,
260 .max_packet_count = -1,
264 .phy_utmi_width = -1,
266 .phy_ulpi_ext_vbus = -1,
270 .en_multiple_tx_fifo = -1,
271 .dev_tx_fifo_size = {
272 /* dev_tx_fifo_size */
312 * This function shows the Driver Version.
314 static ssize_t version_show(struct device_driver *dev, char *buf)
316 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
320 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
323 * Global Debug Level Mask.
325 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
328 * This function shows the driver Debug Level.
330 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
332 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
336 * This function stores the driver Debug Level.
338 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
341 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
345 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
348 extern void hcd_start(dwc_otg_core_if_t *core_if);
349 extern struct usb_hub *g_dwc_otg_root_hub20;
350 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
352 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
354 dwc_otg_device_t *otg_dev = core_if->otg_dev;
355 struct dwc_otg_platform_data *pdata = otg_dev->pldata;
356 dctl_data_t dctl = {.d32 = 0 };
359 if (core_if->op_state == A_HOST) {
361 "dwc_otg_force_host,already in A_HOST mode,everest\n");
363 } else if (pdata->get_status(USB_STATUS_BVABLID) &&
364 core_if->pmic_vbus) {
366 "Please disconnect the USB cable first, and try again!\n");
370 core_if->op_state = A_HOST;
372 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
373 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
374 dctl.b.sftdiscon = 1;
375 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
377 local_irq_save(flags);
378 cil_pcd_stop(core_if);
380 * Initialize the Core for Host mode.
383 dwc_otg_core_init(core_if);
384 dwc_otg_enable_global_interrupts(core_if);
385 cil_hcd_start(core_if);
386 local_irq_restore(flags);
389 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
391 dwc_otg_device_t *otg_dev = core_if->otg_dev;
394 local_irq_save(flags);
396 if (core_if->op_state == B_PERIPHERAL) {
397 local_irq_restore(flags);
399 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
402 core_if->op_state = B_PERIPHERAL;
403 cil_hcd_stop(core_if);
404 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
405 otg_dev->pcd->phy_suspend = 1;
406 otg_dev->pcd->vbus_status = 0;
407 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
409 /* Reset the Controller */
410 dwc_otg_core_reset(core_if);
412 dwc_otg_core_init(core_if);
413 dwc_otg_disable_global_interrupts(core_if);
414 cil_pcd_start(core_if);
416 local_irq_restore(flags);
419 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
421 dwc_otg_device_t *otg_dev = g_otgdev;
422 dwc_otg_core_if_t *core_if = otg_dev->core_if;
424 return sprintf(buf, "%d\n", core_if->usb_mode);
427 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
430 int new_mode = simple_strtoul(buf, NULL, 16);
431 dwc_otg_device_t *otg_dev = g_otgdev;
432 dwc_otg_core_if_t *core_if;
433 struct dwc_otg_platform_data *pldata;
438 core_if = otg_dev->core_if;
439 pldata = otg_dev->pldata;
441 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
443 if (core_if->usb_mode == new_mode) {
447 if (pldata->phy_status == USB_PHY_SUSPEND) {
448 pldata->clock_enable(pldata, 1);
449 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
453 case USB_MODE_FORCE_HOST:
454 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
456 core_if->usb_mode = new_mode;
457 dwc_otg_force_host(core_if);
458 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
459 core_if->usb_mode = new_mode;
460 if (dwc_otg_is_host_mode(core_if))
461 dwc_otg_set_force_mode(core_if, new_mode);
463 dwc_otg_force_host(core_if);
467 case USB_MODE_FORCE_DEVICE:
468 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
469 core_if->usb_mode = new_mode;
470 dwc_otg_force_device(core_if);
471 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
472 core_if->usb_mode = new_mode;
473 if (dwc_otg_is_device_mode(core_if))
474 dwc_otg_set_force_mode(core_if, new_mode);
476 dwc_otg_force_device(core_if);
480 case USB_MODE_NORMAL:
481 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
482 core_if->usb_mode = new_mode;
483 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
484 dwc_otg_set_force_mode(core_if, new_mode);
486 if (dwc_otg_is_host_mode(core_if)) {
487 dwc_otg_force_host(core_if);
489 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
491 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
492 core_if->usb_mode = new_mode;
493 dwc_otg_set_force_mode(core_if, new_mode);
495 if (dwc_otg_is_device_mode(core_if)) {
496 dwc_otg_force_device(core_if);
507 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
508 force_usb_mode_store);
510 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
513 dwc_otg_device_t *otg_dev = g_otgdev;
514 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
515 return sprintf(_buf, "%d\n", _pcd->conn_en);
519 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
520 const char *_buf, size_t _count)
522 int enable = simple_strtoul(_buf, NULL, 10);
523 dwc_otg_device_t *otg_dev = g_otgdev;
524 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
525 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
527 _pcd->conn_en = enable;
531 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
532 dwc_otg_conn_en_store);
534 /* used for product vbus power control, SDK not need.
535 * If dwc_otg is host mode, enable vbus power.
536 * If dwc_otg is device mode, disable vbus power.
537 * return 1 - host mode, 0 - device mode.
539 int dwc_otg_usb_state(void)
541 dwc_otg_device_t *otg_dev = g_otgdev;
544 /* op_state is A_HOST */
545 if (1 == otg_dev->core_if->op_state)
547 /* op_state is B_PERIPHERAL */
548 else if (4 == otg_dev->core_if->op_state)
553 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
557 EXPORT_SYMBOL(dwc_otg_usb_state);
559 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
561 dwc_otg_device_t *otg_dev = g_otgdev;
564 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
566 return sprintf(_buf, "%d\n", 0);
569 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
571 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
573 dwc_otg_device_t *otg_dev = g_otgdev;
574 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
575 return sprintf(_buf, "%d\n", _pcd->vbus_status);
578 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
581 * This function is called during module intialization
582 * to pass module parameters to the DWC_OTG CORE.
584 static int set_parameters(dwc_otg_core_if_t *core_if,
585 struct dwc_otg_driver_module_params module_params)
590 if (module_params.otg_cap != -1) {
592 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
594 if (module_params.dma_enable != -1) {
596 dwc_otg_set_param_dma_enable(core_if,
597 module_params.dma_enable);
599 if (module_params.dma_desc_enable != -1) {
601 dwc_otg_set_param_dma_desc_enable(core_if,
602 module_params.dma_desc_enable);
604 if (module_params.opt != -1) {
605 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
607 if (module_params.dma_burst_size != -1) {
609 dwc_otg_set_param_dma_burst_size(core_if,
610 module_params.dma_burst_size);
612 if (module_params.host_support_fs_ls_low_power != -1) {
614 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
615 module_params.host_support_fs_ls_low_power);
617 if (module_params.enable_dynamic_fifo != -1) {
619 dwc_otg_set_param_enable_dynamic_fifo(core_if,
620 module_params.enable_dynamic_fifo);
622 if (module_params.data_fifo_size != -1) {
624 dwc_otg_set_param_data_fifo_size(core_if,
625 module_params.data_fifo_size);
627 if (module_params.dev_rx_fifo_size != -1) {
629 dwc_otg_set_param_dev_rx_fifo_size(core_if,
630 module_params.dev_rx_fifo_size);
632 if (module_params.dev_nperio_tx_fifo_size != -1) {
634 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
635 module_params.dev_nperio_tx_fifo_size);
637 if (module_params.host_rx_fifo_size != -1) {
639 dwc_otg_set_param_host_rx_fifo_size(core_if,
643 if (module_params.host_nperio_tx_fifo_size != -1) {
645 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
646 module_params.host_nperio_tx_fifo_size);
648 if (module_params.host_perio_tx_fifo_size != -1) {
650 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
651 module_params.host_perio_tx_fifo_size);
653 if (module_params.max_transfer_size != -1) {
655 dwc_otg_set_param_max_transfer_size(core_if,
656 module_params.max_transfer_size);
658 if (module_params.max_packet_count != -1) {
660 dwc_otg_set_param_max_packet_count(core_if,
661 module_params.max_packet_count);
663 if (module_params.host_channels != -1) {
665 dwc_otg_set_param_host_channels(core_if,
666 module_params.host_channels);
668 if (module_params.dev_endpoints != -1) {
670 dwc_otg_set_param_dev_endpoints(core_if,
671 module_params.dev_endpoints);
673 if (module_params.phy_type != -1) {
675 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
677 if (module_params.speed != -1) {
678 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
680 if (module_params.host_ls_low_power_phy_clk != -1) {
682 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
683 module_params.host_ls_low_power_phy_clk);
685 if (module_params.phy_ulpi_ddr != -1) {
687 dwc_otg_set_param_phy_ulpi_ddr(core_if,
688 module_params.phy_ulpi_ddr);
690 if (module_params.phy_ulpi_ext_vbus != -1) {
692 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
693 module_params.phy_ulpi_ext_vbus);
695 if (module_params.phy_utmi_width != -1) {
697 dwc_otg_set_param_phy_utmi_width(core_if,
698 module_params.phy_utmi_width);
700 if (module_params.ulpi_fs_ls != -1) {
702 dwc_otg_set_param_ulpi_fs_ls(core_if,
703 module_params.ulpi_fs_ls);
705 if (module_params.ts_dline != -1) {
707 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
709 if (module_params.i2c_enable != -1) {
711 dwc_otg_set_param_i2c_enable(core_if,
712 module_params.i2c_enable);
714 if (module_params.en_multiple_tx_fifo != -1) {
716 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
717 module_params.en_multiple_tx_fifo);
719 for (i = 0; i < 15; i++) {
720 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
722 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
723 module_params.dev_perio_tx_fifo_size
728 for (i = 0; i < 15; i++) {
729 if (module_params.dev_tx_fifo_size[i] != -1) {
730 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
731 module_params.dev_tx_fifo_size
735 if (module_params.thr_ctl != -1) {
737 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
739 if (module_params.mpi_enable != -1) {
741 dwc_otg_set_param_mpi_enable(core_if,
742 module_params.mpi_enable);
744 if (module_params.pti_enable != -1) {
746 dwc_otg_set_param_pti_enable(core_if,
747 module_params.pti_enable);
749 if (module_params.lpm_enable != -1) {
751 dwc_otg_set_param_lpm_enable(core_if,
752 module_params.lpm_enable);
754 if (module_params.besl_enable != -1) {
756 dwc_otg_set_param_besl_enable(core_if,
757 module_params.besl_enable);
759 if (module_params.baseline_besl != -1) {
761 dwc_otg_set_param_baseline_besl(core_if,
762 module_params.baseline_besl);
764 if (module_params.deep_besl != -1) {
766 dwc_otg_set_param_deep_besl(core_if,
767 module_params.deep_besl);
769 if (module_params.ic_usb_cap != -1) {
771 dwc_otg_set_param_ic_usb_cap(core_if,
772 module_params.ic_usb_cap);
774 if (module_params.tx_thr_length != -1) {
776 dwc_otg_set_param_tx_thr_length(core_if,
780 if (module_params.rx_thr_length != -1) {
782 dwc_otg_set_param_rx_thr_length(core_if,
783 module_params.rx_thr_length);
785 if (module_params.ahb_thr_ratio != -1) {
787 dwc_otg_set_param_ahb_thr_ratio(core_if,
791 if (module_params.power_down != -1) {
793 dwc_otg_set_param_power_down(core_if,
794 module_params.power_down);
796 if (module_params.reload_ctl != -1) {
798 dwc_otg_set_param_reload_ctl(core_if,
799 module_params.reload_ctl);
802 if (module_params.dev_out_nak != -1) {
804 dwc_otg_set_param_dev_out_nak(core_if,
805 module_params.dev_out_nak);
808 if (module_params.cont_on_bna != -1) {
810 dwc_otg_set_param_cont_on_bna(core_if,
811 module_params.cont_on_bna);
814 if (module_params.ahb_single != -1) {
816 dwc_otg_set_param_ahb_single(core_if,
817 module_params.ahb_single);
820 if (module_params.otg_ver != -1) {
822 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
824 if (module_params.adp_enable != -1) {
826 dwc_otg_set_param_adp_enable(core_if,
827 module_params.adp_enable);
833 * This function is the top level interrupt handler for the Common
834 * (Device and host modes) interrupts.
836 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
838 int32_t retval = IRQ_NONE;
840 retval = dwc_otg_handle_common_intr(dev);
842 /* S3C2410X_CLEAR_EINTPEND(); */
844 return IRQ_RETVAL(retval);
847 #ifdef CONFIG_USB20_HOST
849 * This function is called when a lm_device is unregistered with the
850 * dwc_otg_driver. This happens, for example, when the rmmod command is
851 * executed. The device may or may not be electrically present. If it is
852 * present, the driver stops device processing. Any resources used on behalf
853 * of this device are freed.
857 static int host20_driver_remove(struct platform_device *_dev)
860 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
861 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
864 /* Memory allocation for the dwc_otg_device failed. */
865 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
868 #ifndef DWC_DEVICE_ONLY
872 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
877 #ifndef DWC_HOST_ONLY
881 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
889 if (otg_dev->common_irq_installed) {
890 /* free_irq(_dev->irq, otg_dev); */
891 free_irq(platform_get_irq(_dev, 0), otg_dev);
893 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
898 if (otg_dev->core_if) {
899 dwc_otg_cil_remove(otg_dev->core_if);
901 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
906 * Remove the device attributes
908 dwc_otg_attr_remove(_dev);
913 if (otg_dev->os_dep.base) {
914 iounmap(otg_dev->os_dep.base);
919 * Clear the drvdata pointer.
922 dwc_set_device_platform_data(_dev, 0);
927 static const struct of_device_id usb20_host_of_match[] = {
930 .compatible = "rockchip,rk3188_usb20_host",
931 .data = &usb20host_pdata_rk3188,
934 .compatible = "rockchip,rk3288_usb20_host",
935 .data = &usb20host_pdata_rk3288,
938 .compatible = "rockchip,rk3036_usb20_host",
939 .data = &usb20host_pdata_rk3036,
942 .compatible = "rockchip,rk3126_usb20_host",
943 .data = &usb20host_pdata_rk3126,
949 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
952 * This function is called when an lm_device is bound to a
953 * dwc_otg_driver. It creates the driver components required to
954 * control the device (CIL, HCD, and PCD) and it initializes the
955 * device. The driver components are stored in a dwc_otg_device
956 * structure. A reference to the dwc_otg_device is saved in the
957 * lm_device. This allows the driver to access the dwc_otg_device
958 * structure on subsequent calls to driver methods for this device.
960 * @param _dev Bus device
962 static int host20_driver_probe(struct platform_device *_dev)
966 struct resource *res_base;
967 dwc_otg_device_t *dwc_otg_device;
968 struct device *dev = &_dev->dev;
969 struct device_node *node = _dev->dev.of_node;
970 struct dwc_otg_platform_data *pldata;
971 const struct of_device_id *match =
972 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
974 if (match && match->data) {
975 pldata = (void *)match->data;
978 dev_err(dev, "usb20otg match failed\n");
983 dev_err(dev, "device node not found\n");
990 if (pldata->clock_init) {
991 pldata->clock_init(pldata);
992 pldata->clock_enable(pldata, 1);
995 if (pldata->phy_suspend)
996 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
998 if (pldata->soft_reset)
999 pldata->soft_reset(pldata, RST_POR);
1001 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1003 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1005 if (!dwc_otg_device) {
1006 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1011 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1012 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1015 * Map the DWC_otg Core memory into virtual address space.
1018 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1020 if (!dwc_otg_device->os_dep.base) {
1021 dev_err(&_dev->dev, "ioremap() failed\n");
1022 DWC_FREE(dwc_otg_device);
1026 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1028 /* Set device flags indicating whether the HCD supports DMA. */
1029 if (!_dev->dev.dma_mask)
1030 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1031 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1036 * Initialize driver data to point to the global DWC_otg
1040 dwc_set_device_platform_data(_dev, dwc_otg_device);
1041 pldata->privdata = dwc_otg_device;
1042 dwc_otg_device->pldata = (void *)pldata;
1044 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1046 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1048 if (!dwc_otg_device->core_if) {
1049 dev_err(&_dev->dev, "CIL initialization failed!\n");
1054 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1057 * Attempt to ensure this device is really a DWC_otg Controller.
1058 * Read and verify the SNPSID register contents. The value should be
1059 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1060 * as in "OTG version 2.XX" or "OTG version 3.XX".
1063 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1065 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1067 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1068 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1074 * Validate parameter values.
1076 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1082 * Create Device Attributes in sysfs
1084 dwc_otg_attr_create(_dev);
1087 * Disable the global interrupt until all the interrupt
1088 * handlers are installed.
1090 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1093 * Install the interrupt handler for the common interrupts before
1094 * enabling common interrupts in core_init below.
1096 irq = platform_get_irq(_dev, 0);
1097 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1098 retval = request_irq(irq, dwc_otg_common_irq,
1099 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1101 DWC_ERROR("request of irq%d failed\n", irq);
1105 dwc_otg_device->common_irq_installed = 1;
1109 * Initialize the DWC_otg core.
1110 * In order to reduce the time of initialization,
1111 * we do core soft reset after connection detected.
1113 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1116 * Initialize the HCD
1118 retval = host20_hcd_init(_dev);
1120 DWC_ERROR("hcd_init failed\n");
1121 dwc_otg_device->hcd = NULL;
1125 clk_set_rate(pldata->phyclk_480m, 480000000);
1127 * Enable the global interrupt after all the interrupt
1128 * handlers are installed if there is no ADP support else
1129 * perform initial actions required for Internal ADP logic.
1131 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1132 if (pldata->phy_status == USB_PHY_ENABLED) {
1133 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1135 pldata->clock_enable(pldata, 0);
1137 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1139 dwc_otg_adp_start(dwc_otg_device->core_if,
1140 dwc_otg_is_host_mode(dwc_otg_device->
1146 host20_driver_remove(_dev);
1148 if (pldata->clock_enable)
1149 pldata->clock_enable(pldata, 0);
1155 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1161 static int dwc_otg_driver_resume(struct platform_device *_dev)
1166 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1168 struct device *dev = &_dev->dev;
1169 dwc_otg_device_t *otg_dev = dev->platform_data;
1170 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1171 struct dwc_otg_platform_data *pldata = otg_dev->pldata;
1172 dctl_data_t dctl = {.d32 = 0 };
1173 dwc_otg_pcd_t *pcd = core_if->otg_dev->pcd;
1175 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1176 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1178 if (dwc_otg_is_host_mode(core_if)) {
1179 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1180 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1182 cancel_delayed_work_sync(&pcd->check_vbus_work);
1183 /* soft disconnect */
1185 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1186 dctl.b.sftdiscon = 1;
1187 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1190 /* Clear any pending interrupts */
1191 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1193 if (pldata->dwc_otg_uart_mode != NULL)
1194 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1195 if (pldata->phy_suspend != NULL)
1196 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1201 * This structure defines the methods to be called by a bus driver
1202 * during the lifecycle of a device on that bus. Both drivers and
1203 * devices are registered with a bus driver. The bus driver matches
1204 * devices to drivers based on information in the device and driver
1207 * The probe function is called when the bus driver matches a device
1208 * to this driver. The remove function is called when a device is
1209 * unregistered with the bus driver.
1211 #ifdef CONFIG_USB20_HOST
1212 static struct platform_driver dwc_host_driver = {
1214 .name = (char *)dwc_host20_driver_name,
1215 .of_match_table = of_match_ptr(usb20_host_of_match),
1217 .probe = host20_driver_probe,
1218 .remove = host20_driver_remove,
1219 .suspend = dwc_otg_driver_suspend,
1220 .resume = dwc_otg_driver_resume,
1224 #ifdef CONFIG_USB20_OTG
1226 * This function is called when a lm_device is unregistered with the
1227 * dwc_otg_driver. This happens, for example, when the rmmod command is
1228 * executed. The device may or may not be electrically present. If it is
1229 * present, the driver stops device processing. Any resources used on behalf
1230 * of this device are freed.
1234 static int otg20_driver_remove(struct platform_device *_dev)
1237 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1238 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1241 /* Memory allocation for the dwc_otg_device failed. */
1242 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1245 #ifndef DWC_DEVICE_ONLY
1249 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1254 #ifndef DWC_HOST_ONLY
1258 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1265 if (otg_dev->common_irq_installed) {
1266 /* free_irq(_dev->irq, otg_dev); */
1267 free_irq(platform_get_irq(_dev, 0), otg_dev);
1269 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1274 if (otg_dev->core_if) {
1275 dwc_otg_cil_remove(otg_dev->core_if);
1277 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1282 * Remove the device attributes
1284 dwc_otg_attr_remove(_dev);
1287 * Return the memory.
1289 if (otg_dev->os_dep.base)
1290 iounmap(otg_dev->os_dep.base);
1294 * Clear the drvdata pointer.
1297 dwc_set_device_platform_data(_dev, 0);
1302 static const struct of_device_id usb20_otg_of_match[] = {
1305 .compatible = "rockchip,rk3188_usb20_otg",
1306 .data = &usb20otg_pdata_rk3188,
1309 .compatible = "rockchip,rk3288_usb20_otg",
1310 .data = &usb20otg_pdata_rk3288,
1313 .compatible = "rockchip,rk3036_usb20_otg",
1314 .data = &usb20otg_pdata_rk3036,
1317 .compatible = "rockchip,rk3126_usb20_otg",
1318 .data = &usb20otg_pdata_rk3126,
1323 .compatible = "rockchip,rk3368-usb",
1324 .data = &usb20otg_pdata_rk3368,
1330 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1333 * This function is called when an lm_device is bound to a
1334 * dwc_otg_driver. It creates the driver components required to
1335 * control the device (CIL, HCD, and PCD) and it initializes the
1336 * device. The driver components are stored in a dwc_otg_device
1337 * structure. A reference to the dwc_otg_device is saved in the
1338 * lm_device. This allows the driver to access the dwc_otg_device
1339 * structure on subsequent calls to driver methods for this device.
1341 * @param _dev Bus device
1343 static int otg20_driver_probe(struct platform_device *_dev)
1348 struct resource *res_base;
1349 dwc_otg_device_t *dwc_otg_device;
1350 struct device *dev = &_dev->dev;
1351 struct device_node *node = _dev->dev.of_node;
1352 struct dwc_otg_platform_data *pldata;
1353 const struct of_device_id *match =
1354 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1356 if (match && match->data) {
1357 pldata = (void *)match->data;
1360 dev_err(dev, "usb20otg match failed\n");
1365 dev_err(dev, "device node not found\n");
1369 if (pldata->hw_init)
1372 if (pldata->clock_init) {
1373 pldata->clock_init(pldata);
1374 pldata->clock_enable(pldata, 1);
1377 if (pldata->phy_suspend)
1378 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1380 if (pldata->dwc_otg_uart_mode)
1381 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1383 /* do reset later, because reset need about
1384 * 100ms to ensure otg id state change.
1387 if(pldata->soft_reset)
1388 pldata->soft_reset();
1392 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1394 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1396 if (!dwc_otg_device) {
1397 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1402 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1403 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1406 * Map the DWC_otg Core memory into virtual address space.
1409 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1411 if (!dwc_otg_device->os_dep.base) {
1412 dev_err(&_dev->dev, "ioremap() failed\n");
1413 DWC_FREE(dwc_otg_device);
1417 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1419 /* Set device flags indicating whether the HCD supports DMA. */
1420 if (!_dev->dev.dma_mask)
1421 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1422 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1427 * Initialize driver data to point to the global DWC_otg
1431 g_otgdev = dwc_otg_device;
1432 dwc_otg_dev = (struct device *)&_dev->dev;
1433 pldata->privdata = dwc_otg_device;
1434 dwc_otg_device->pldata = pldata;
1436 dwc_set_device_platform_data(_dev, dwc_otg_device);
1438 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1440 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1441 if (!dwc_otg_device->core_if) {
1442 dev_err(&_dev->dev, "CIL initialization failed!\n");
1447 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1449 * Attempt to ensure this device is really a DWC_otg Controller.
1450 * Read and verify the SNPSID register contents. The value should be
1451 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1452 * as in "OTG version 2.XX" or "OTG version 3.XX".
1455 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1457 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1459 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1460 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1466 * Validate parameter values.
1468 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1474 * Create Device Attributes in sysfs
1476 dwc_otg_attr_create(_dev);
1479 * Disable the global interrupt until all the interrupt
1480 * handlers are installed.
1482 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1485 * Install the interrupt handler for the common interrupts before
1486 * enabling common interrupts in core_init below.
1488 irq = platform_get_irq(_dev, 0);
1489 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1490 retval = request_irq(irq, dwc_otg_common_irq,
1491 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1493 DWC_ERROR("request of irq%d failed\n", irq);
1497 dwc_otg_device->common_irq_installed = 1;
1501 * Initialize the DWC_otg core.
1502 * In order to reduce the time of initialization,
1503 * we do core soft reset after connection detected.
1505 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1508 * 0 - USB_MODE_NORMAL
1509 * 1 - USB_MODE_FORCE_HOST
1510 * 2 - USB_MODE_FORCE_DEVICE
1512 of_property_read_u32(node, "rockchip,usb-mode", &val);
1513 dwc_otg_device->core_if->usb_mode = val;
1515 /* Indicate usb vbus get from pmic (e.g. rk81x) */
1516 dwc_otg_device->core_if->pmic_vbus = of_property_read_bool(node,
1517 "rockchip,usb-pmic-vbus");
1519 #ifndef DWC_HOST_ONLY
1521 * Initialize the PCD
1523 retval = pcd_init(_dev);
1525 DWC_ERROR("pcd_init failed\n");
1526 dwc_otg_device->pcd = NULL;
1530 #ifndef DWC_DEVICE_ONLY
1532 * Initialize the HCD
1534 retval = otg20_hcd_init(_dev);
1536 DWC_ERROR("hcd_init failed\n");
1537 dwc_otg_device->hcd = NULL;
1542 * Enable the global interrupt after all the interrupt
1543 * handlers are installed if there is no ADP support else
1544 * perform initial actions required for Internal ADP logic.
1546 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1547 if (dwc_otg_device->core_if->usb_mode == USB_MODE_NORMAL &&
1548 pldata->phy_status == USB_PHY_ENABLED) {
1549 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1551 pldata->clock_enable(pldata, 0);
1553 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1555 dwc_otg_adp_start(dwc_otg_device->core_if,
1556 dwc_otg_is_host_mode(dwc_otg_device->
1562 otg20_driver_remove(_dev);
1565 if (pldata->clock_enable)
1566 pldata->clock_enable(pldata, 0);
1572 static int dwc_otg_pm_suspend(struct device *dev)
1574 dwc_otg_device_t *dwc_otg_device;
1575 struct dwc_otg_platform_data *pdata_otg;
1577 dwc_otg_device = dev_get_platdata(dev);
1579 dev_dbg(dev, "dwc_otg PM suspend\n");
1581 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1584 pdata_otg = dwc_otg_device->pldata;
1585 pdata_otg->phy_suspend(pdata_otg, USB_PHY_SUSPEND);
1590 static int dwc_otg_pm_resume(struct device *dev)
1592 dwc_otg_device_t *dwc_otg_device;
1593 struct dwc_otg_platform_data *pdata_otg;
1595 dwc_otg_device = dev_get_platdata(dev);
1597 dev_dbg(dev, "dwc_otg PM resume\n");
1599 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1602 pdata_otg = dwc_otg_device->pldata;
1603 pdata_otg->phy_suspend(pdata_otg, USB_PHY_ENABLED);
1608 #define dwc_otg_pm_suspend NULL
1609 #define dwc_otg_pm_resume NULL
1612 static const struct dev_pm_ops dwc_otg_dev_pm_ops = {
1613 .suspend = dwc_otg_pm_suspend,
1614 .resume = dwc_otg_pm_resume,
1617 static struct platform_driver dwc_otg_driver = {
1619 .name = (char *)dwc_otg20_driver_name,
1620 .of_match_table = of_match_ptr(usb20_otg_of_match),
1622 .pm = &dwc_otg_dev_pm_ops,
1625 .probe = otg20_driver_probe,
1626 .remove = otg20_driver_remove,
1627 .suspend = dwc_otg_driver_suspend,
1628 .resume = dwc_otg_driver_resume,
1629 .shutdown = dwc_otg_driver_shutdown,
1633 void rk_usb_power_up(void)
1635 struct dwc_otg_platform_data *pldata_otg;
1636 #ifdef CONFIG_USB20_HOST
1637 struct dwc_otg_platform_data *pldata_host;
1639 #ifdef CONFIG_USB_EHCI_RK
1640 struct rkehci_platform_data *pldata_ehci;
1643 if (is_rk3288_usb()) {
1644 #ifdef CONFIG_RK_USB_UART
1645 /* enable USB bypass UART function */
1646 writel_relaxed(0x00c00000 | usb_to_uart_status,
1647 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1650 /* unset siddq,the analog blocks are powered up */
1651 #ifdef CONFIG_USB20_OTG
1652 pldata_otg = &usb20otg_pdata_rk3288;
1654 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1655 writel_relaxed((0x01 << 13) << 16,
1657 RK3288_GRF_UOC0_CON0);
1660 #ifdef CONFIG_USB20_HOST
1661 pldata_host = &usb20host_pdata_rk3288;
1663 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1664 writel_relaxed((0x01 << 13) << 16,
1666 RK3288_GRF_UOC2_CON0);
1669 #ifdef CONFIG_USB_EHCI_RK
1670 pldata_ehci = &rkehci_pdata_rk3288;
1672 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1673 writel_relaxed((0x01 << 13) << 16,
1675 RK3288_GRF_UOC1_CON0);
1680 dwc_otg_device_t *otg_dev = g_otgdev;
1685 pldata_otg = otg_dev->pldata;
1686 if (pldata_otg && pldata_otg->phy_power_down)
1687 pldata_otg->phy_power_down(PHY_POWER_UP);
1691 void rk_usb_power_down(void)
1693 struct dwc_otg_platform_data *pldata_otg;
1694 #ifdef CONFIG_USB20_HOST
1695 struct dwc_otg_platform_data *pldata_host;
1697 #ifdef CONFIG_USB_EHCI_RK
1698 struct rkehci_platform_data *pldata_ehci;
1701 if (is_rk3288_usb()) {
1702 #ifdef CONFIG_RK_USB_UART
1703 /* disable USB bypass UART function */
1704 usb_to_uart_status =
1705 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1706 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1708 /* set siddq,the analog blocks are powered down
1710 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1711 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1712 * and TESTBURNIN are set to 1'b0.
1713 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1714 #ifdef CONFIG_USB20_OTG
1715 pldata_otg = &usb20otg_pdata_rk3288;
1717 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1718 writel_relaxed((0x01 << 13) |
1719 ((0x01 << 13) << 16),
1721 RK3288_GRF_UOC0_CON0);
1724 #ifdef CONFIG_USB20_HOST
1725 pldata_host = &usb20host_pdata_rk3288;
1727 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1728 writel_relaxed((0x01 << 13) |
1729 ((0x01 << 13) << 16),
1731 RK3288_GRF_UOC2_CON0);
1734 #ifdef CONFIG_USB_EHCI_RK
1735 pldata_ehci = &rkehci_pdata_rk3288;
1737 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1738 writel_relaxed((0x01 << 13) |
1739 ((0x01 << 13) << 16),
1741 RK3288_GRF_UOC1_CON0);
1745 dwc_otg_device_t *otg_dev = g_otgdev;
1750 pldata_otg = otg_dev->pldata;
1751 if (pldata_otg && pldata_otg->phy_power_down)
1752 pldata_otg->phy_power_down(PHY_POWER_DOWN);
1756 EXPORT_SYMBOL(rk_usb_power_up);
1757 EXPORT_SYMBOL(rk_usb_power_down);
1759 * This function is called when the dwc_otg_driver is installed with the
1760 * insmod command. It registers the dwc_otg_driver structure with the
1761 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1762 * to be called. In addition, the bus driver will automatically expose
1763 * attributes defined for the device and driver in the special sysfs file
1768 static int __init dwc_otg_driver_init(void)
1773 #ifdef CONFIG_USB20_OTG
1774 /* register otg20 */
1775 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1776 DWC_DRIVER_VERSION);
1778 retval = platform_driver_register(&dwc_otg_driver);
1780 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1785 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1787 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1789 driver_create_file(&dwc_otg_driver.driver,
1790 &driver_attr_dwc_otg_conn_en);
1792 driver_create_file(&dwc_otg_driver.driver,
1793 &driver_attr_vbus_status);
1795 driver_create_file(&dwc_otg_driver.driver,
1796 &driver_attr_force_usb_mode);
1798 driver_create_file(&dwc_otg_driver.driver,
1799 &driver_attr_op_state);
1803 /* register host20 */
1804 #ifdef CONFIG_USB20_HOST
1805 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1806 DWC_DRIVER_VERSION);
1808 retval = platform_driver_register(&dwc_host_driver);
1810 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1815 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1817 driver_create_file(&dwc_host_driver.driver,
1818 &driver_attr_debuglevel);
1823 module_init(dwc_otg_driver_init);
1826 * This function is called when the driver is removed from the kernel
1827 * with the rmmod command. The driver unregisters itself with its bus
1831 static void __exit dwc_otg_driver_cleanup(void)
1833 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1835 #ifdef CONFIG_USB20_HOST
1837 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1838 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1839 platform_driver_unregister(&dwc_host_driver);
1840 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1843 #ifdef CONFIG_USB20_OTG
1845 driver_remove_file(&dwc_otg_driver.driver,
1846 &driver_attr_dwc_otg_conn_en);
1847 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1848 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1849 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1850 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1851 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1852 platform_driver_unregister(&dwc_otg_driver);
1853 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1857 module_exit(dwc_otg_driver_cleanup);
1859 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1860 MODULE_AUTHOR("Synopsys Inc.");
1861 MODULE_LICENSE("GPL");
1863 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1864 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1865 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1866 MODULE_PARM_DESC(opt, "OPT Mode");
1867 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1868 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1870 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1872 MODULE_PARM_DESC(dma_desc_enable,
1873 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1875 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1877 MODULE_PARM_DESC(dma_burst_size,
1878 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1879 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1880 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1881 module_param_named(host_support_fs_ls_low_power,
1882 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1884 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1885 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1886 module_param_named(host_ls_low_power_phy_clk,
1887 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1888 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1889 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1890 module_param_named(enable_dynamic_fifo,
1891 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1892 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1893 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1895 MODULE_PARM_DESC(data_fifo_size,
1896 "Total number of words in the data FIFO memory 32-32768");
1897 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1899 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1900 module_param_named(dev_nperio_tx_fifo_size,
1901 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1902 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1903 "Number of words in the non-periodic Tx FIFO 16-32768");
1904 module_param_named(dev_perio_tx_fifo_size_1,
1905 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1906 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1907 "Number of words in the periodic Tx FIFO 4-768");
1908 module_param_named(dev_perio_tx_fifo_size_2,
1909 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1910 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1911 "Number of words in the periodic Tx FIFO 4-768");
1912 module_param_named(dev_perio_tx_fifo_size_3,
1913 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1914 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1915 "Number of words in the periodic Tx FIFO 4-768");
1916 module_param_named(dev_perio_tx_fifo_size_4,
1917 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1918 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1919 "Number of words in the periodic Tx FIFO 4-768");
1920 module_param_named(dev_perio_tx_fifo_size_5,
1921 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1922 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1923 "Number of words in the periodic Tx FIFO 4-768");
1924 module_param_named(dev_perio_tx_fifo_size_6,
1925 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1926 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1927 "Number of words in the periodic Tx FIFO 4-768");
1928 module_param_named(dev_perio_tx_fifo_size_7,
1929 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1930 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1931 "Number of words in the periodic Tx FIFO 4-768");
1932 module_param_named(dev_perio_tx_fifo_size_8,
1933 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1934 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1935 "Number of words in the periodic Tx FIFO 4-768");
1936 module_param_named(dev_perio_tx_fifo_size_9,
1937 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1938 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1939 "Number of words in the periodic Tx FIFO 4-768");
1940 module_param_named(dev_perio_tx_fifo_size_10,
1941 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1942 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1943 "Number of words in the periodic Tx FIFO 4-768");
1944 module_param_named(dev_perio_tx_fifo_size_11,
1945 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1946 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1947 "Number of words in the periodic Tx FIFO 4-768");
1948 module_param_named(dev_perio_tx_fifo_size_12,
1949 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1950 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1951 "Number of words in the periodic Tx FIFO 4-768");
1952 module_param_named(dev_perio_tx_fifo_size_13,
1953 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1954 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1955 "Number of words in the periodic Tx FIFO 4-768");
1956 module_param_named(dev_perio_tx_fifo_size_14,
1957 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1958 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1959 "Number of words in the periodic Tx FIFO 4-768");
1960 module_param_named(dev_perio_tx_fifo_size_15,
1961 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1962 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1963 "Number of words in the periodic Tx FIFO 4-768");
1964 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1966 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1967 module_param_named(host_nperio_tx_fifo_size,
1968 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1969 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1970 "Number of words in the non-periodic Tx FIFO 16-32768");
1971 module_param_named(host_perio_tx_fifo_size,
1972 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1973 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1974 "Number of words in the host periodic Tx FIFO 16-32768");
1975 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1977 /** @todo Set the max to 512K, modify checks */
1978 MODULE_PARM_DESC(max_transfer_size,
1979 "The maximum transfer size supported in bytes 2047-65535");
1980 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1982 MODULE_PARM_DESC(max_packet_count,
1983 "The maximum number of packets in a transfer 15-511");
1984 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1986 MODULE_PARM_DESC(host_channels,
1987 "The number of host channel registers to use 1-16");
1988 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1990 MODULE_PARM_DESC(dev_endpoints,
1991 "The number of endpoints in addition to EP0 available for device mode 1-15");
1992 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1993 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1994 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1996 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1997 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1998 MODULE_PARM_DESC(phy_ulpi_ddr,
1999 "ULPI at double or single data rate 0=Single 1=Double");
2000 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
2002 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
2003 "ULPI PHY using internal or external vbus 0=Internal");
2004 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
2005 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
2006 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
2007 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
2008 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
2009 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
2010 module_param_named(debug, g_dbg_lvl, int, 0444);
2011 MODULE_PARM_DESC(debug, "");
2013 module_param_named(en_multiple_tx_fifo,
2014 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
2015 MODULE_PARM_DESC(en_multiple_tx_fifo,
2016 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
2017 module_param_named(dev_tx_fifo_size_1,
2018 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
2019 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
2020 module_param_named(dev_tx_fifo_size_2,
2021 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
2022 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
2023 module_param_named(dev_tx_fifo_size_3,
2024 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
2025 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
2026 module_param_named(dev_tx_fifo_size_4,
2027 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
2028 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
2029 module_param_named(dev_tx_fifo_size_5,
2030 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
2031 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2032 module_param_named(dev_tx_fifo_size_6,
2033 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2034 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2035 module_param_named(dev_tx_fifo_size_7,
2036 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2037 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2038 module_param_named(dev_tx_fifo_size_8,
2039 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2040 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2041 module_param_named(dev_tx_fifo_size_9,
2042 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2043 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2044 module_param_named(dev_tx_fifo_size_10,
2045 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2046 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2047 module_param_named(dev_tx_fifo_size_11,
2048 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2049 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2050 module_param_named(dev_tx_fifo_size_12,
2051 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2052 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2053 module_param_named(dev_tx_fifo_size_13,
2054 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2055 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2056 module_param_named(dev_tx_fifo_size_14,
2057 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2058 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2059 module_param_named(dev_tx_fifo_size_15,
2060 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2061 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2063 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2064 MODULE_PARM_DESC(thr_ctl,
2065 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2066 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2068 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2069 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2071 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2073 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2074 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2075 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2076 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2078 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2079 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2080 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2082 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2083 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2084 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2086 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2087 MODULE_PARM_DESC(ic_usb_cap,
2088 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2089 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2091 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2092 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2093 MODULE_PARM_DESC(power_down, "Power Down Mode");
2094 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2095 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2096 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2097 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2098 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2099 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2100 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2101 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2102 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2103 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2104 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2105 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2107 /** @page "Module Parameters"
2109 * The following parameters may be specified when starting the module.
2110 * These parameters define how the DWC_otg controller should be
2111 * configured. Parameter values are passed to the CIL initialization
2112 * function dwc_otg_cil_init
2114 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2118 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2122 <td>Specifies the OTG capabilities. The driver will automatically detect the
2123 value for this parameter if none is specified.
2124 - 0: HNP and SRP capable (default, if available)
2125 - 1: SRP Only capable
2126 - 2: No HNP/SRP capable
2131 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2132 The driver will automatically detect the value for this parameter if none is
2135 - 1: DMA (default, if available)
2139 <td>dma_burst_size</td>
2140 <td>The DMA Burst size (applicable only for External DMA Mode).
2141 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2146 <td>Specifies the maximum speed of operation in host and device mode. The
2147 actual speed depends on the speed of the attached device and the value of
2149 - 0: High Speed (default)
2154 <td>host_support_fs_ls_low_power</td>
2155 <td>Specifies whether low power mode is supported when attached to a Full
2156 Speed or Low Speed device in host mode.
2157 - 0: Don't support low power mode (default)
2158 - 1: Support low power mode
2162 <td>host_ls_low_power_phy_clk</td>
2163 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2164 Speed device in host mode. This parameter is applicable only if
2165 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2166 - 0: 48 MHz (default)
2171 <td>enable_dynamic_fifo</td>
2172 <td> Specifies whether FIFOs may be resized by the driver software.
2173 - 0: Use cC FIFO size parameters
2174 - 1: Allow dynamic FIFO sizing (default)
2178 <td>data_fifo_size</td>
2179 <td>Total number of 4-byte words in the data FIFO memory. This memory
2180 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2181 - Values: 32 to 32768 (default 8192)
2183 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2187 <td>dev_rx_fifo_size</td>
2188 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2189 FIFO sizing is enabled.
2190 - Values: 16 to 32768 (default 1064)
2194 <td>dev_nperio_tx_fifo_size</td>
2195 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2196 dynamic FIFO sizing is enabled.
2197 - Values: 16 to 32768 (default 1024)
2201 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2202 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2203 when dynamic FIFO sizing is enabled.
2204 - Values: 4 to 768 (default 256)
2208 <td>host_rx_fifo_size</td>
2209 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2211 - Values: 16 to 32768 (default 1024)
2215 <td>host_nperio_tx_fifo_size</td>
2216 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2217 dynamic FIFO sizing is enabled in the core.
2218 - Values: 16 to 32768 (default 1024)
2222 <td>host_perio_tx_fifo_size</td>
2223 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2225 - Values: 16 to 32768 (default 1024)
2229 <td>max_transfer_size</td>
2230 <td>The maximum transfer size supported in bytes.
2231 - Values: 2047 to 65,535 (default 65,535)
2235 <td>max_packet_count</td>
2236 <td>The maximum number of packets in a transfer.
2237 - Values: 15 to 511 (default 511)
2241 <td>host_channels</td>
2242 <td>The number of host channel registers to use.
2243 - Values: 1 to 16 (default 12)
2245 Note: The FPGA configuration supports a maximum of 12 host channels.
2249 <td>dev_endpoints</td>
2250 <td>The number of endpoints in addition to EP0 available for device mode
2252 - Values: 1 to 15 (default 6 IN and OUT)
2254 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2260 <td>Specifies the type of PHY interface to use. By default, the driver will
2261 automatically detect the phy_type.
2263 - 1: UTMI+ (default, if available)
2268 <td>phy_utmi_width</td>
2269 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2270 phy_type of UTMI+. Also, this parameter is applicable only if the
2271 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2272 core has been configured to work at either data path width.
2273 - Values: 8 or 16 bits (default 16)
2277 <td>phy_ulpi_ddr</td>
2278 <td>Specifies whether the ULPI operates at double or single data rate. This
2279 parameter is only applicable if phy_type is ULPI.
2280 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2281 - 1: double data rate ULPI interface with 4 bit wide data bus
2286 <td>Specifies whether to use the I2C interface for full speed PHY. This
2287 parameter is only applicable if PHY_TYPE is FS.
2288 - 0: Disabled (default)
2294 <td>Specifies whether to use ULPI FS/LS mode only.
2295 - 0: Disabled (default)
2301 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2302 - 0: Disabled (default)
2307 <td>en_multiple_tx_fifo</td>
2308 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2309 The driver will automatically detect the value for this parameter if none is
2312 - 1: Enabled (default, if available)
2316 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2317 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2318 when dynamic FIFO sizing is enabled.
2319 - Values: 4 to 768 (default 256)
2323 <td>tx_thr_length</td>
2324 <td>Transmit Threshold length in 32 bit double words
2325 - Values: 8 to 128 (default 64)
2329 <td>rx_thr_length</td>
2330 <td>Receive Threshold length in 32 bit double words
2331 - Values: 8 to 128 (default 64)
2336 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2337 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2338 Rx transfers accordingly.
2339 The driver will automatically detect the value for this parameter if none is
2341 - Values: 0 to 7 (default 0)
2342 Bit values indicate:
2343 - 0: Thresholding disabled
2344 - 1: Thresholding enabled
2348 <td>dma_desc_enable</td>
2349 <td>Specifies whether to enable Descriptor DMA mode.
2350 The driver will automatically detect the value for this parameter if none is
2352 - 0: Descriptor DMA disabled
2353 - 1: Descriptor DMA (default, if available)
2358 <td>Specifies whether to enable MPI enhancement mode.
2359 The driver will automatically detect the value for this parameter if none is
2361 - 0: MPI disabled (default)
2367 <td>Specifies whether to enable PTI enhancement support.
2368 The driver will automatically detect the value for this parameter if none is
2370 - 0: PTI disabled (default)
2376 <td>Specifies whether to enable LPM support.
2377 The driver will automatically detect the value for this parameter if none is
2380 - 1: LPM enable (default, if available)
2384 <td>besl_enable</td>
2385 <td>Specifies whether to enable LPM Errata support.
2386 The driver will automatically detect the value for this parameter if none is
2388 - 0: LPM Errata disabled (default)
2389 - 1: LPM Errata enable
2393 <td>baseline_besl</td>
2394 <td>Specifies the baseline besl value.
2395 - Values: 0 to 15 (default 0)
2400 <td>Specifies the deep besl value.
2401 - Values: 0 to 15 (default 15)
2406 <td>Specifies whether to enable IC_USB capability.
2407 The driver will automatically detect the value for this parameter if none is
2409 - 0: IC_USB disabled (default, if available)
2414 <td>ahb_thr_ratio</td>
2415 <td>Specifies AHB Threshold ratio.
2416 - Values: 0 to 3 (default 0)
2421 <td>Specifies Power Down(Hibernation) Mode.
2422 The driver will automatically detect the value for this parameter if none is
2424 - 0: Power Down disabled (default)
2425 - 2: Power Down enabled
2430 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2431 run time. The driver will automatically detect the value for this parameter if
2432 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2433 the core might misbehave.
2434 - 0: Reload Control disabled (default)
2435 - 1: Reload Control enabled
2439 <td>dev_out_nak</td>
2440 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2441 The driver will automatically detect the value for this parameter if
2442 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2443 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2444 - 1: The core sets NAK after Bulk OUT transfer complete
2448 <td>cont_on_bna</td>
2449 <td>Specifies whether Enable Continue on BNA enabled or no.
2450 After receiving BNA interrupt the core disables the endpoint,when the
2451 endpoint is re-enabled by the application the
2452 - 0: Core starts processing from the DOEPDMA descriptor (default)
2453 - 1: Core starts processing from the descriptor which received the BNA.
2454 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2459 <td>This bit when programmed supports SINGLE transfers for remainder data
2460 in a transfer for DMA mode of operation.
2461 - 0: The remainder data will be sent using INCR burst size (default)
2462 - 1: The remainder data will be sent using SINGLE burst size.
2467 <td>Specifies whether ADP feature is enabled.
2468 The driver will automatically detect the value for this parameter if none is
2470 - 0: ADP feature disabled (default)
2471 - 1: ADP feature enabled
2476 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2478 - 0: OTG 2.0 support disabled (default)
2479 - 1: OTG 2.0 support enabled