1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
93 #ifdef CONFIG_USB20_HOST
94 static struct usb20host_pdata_id usb20host_pdata[] = {
96 .name = "rk3188-usb20host",
97 .pdata = &usb20host_pdata_rk3188,
100 .name = "rk3288-usb20host",
101 .pdata = &usb20host_pdata_rk3288,
107 #ifdef CONFIG_RK_USB_UART
108 static u32 usb_to_uart_status;
110 /*-------------------------------------------------------------------------*/
111 /* Encapsulate the module parameter settings */
113 struct dwc_otg_driver_module_params {
117 int32_t dma_desc_enable;
118 int32_t dma_burst_size;
120 int32_t host_support_fs_ls_low_power;
121 int32_t host_ls_low_power_phy_clk;
122 int32_t enable_dynamic_fifo;
123 int32_t data_fifo_size;
124 int32_t dev_rx_fifo_size;
125 int32_t dev_nperio_tx_fifo_size;
126 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
127 int32_t host_rx_fifo_size;
128 int32_t host_nperio_tx_fifo_size;
129 int32_t host_perio_tx_fifo_size;
130 int32_t max_transfer_size;
131 int32_t max_packet_count;
132 int32_t host_channels;
133 int32_t dev_endpoints;
135 int32_t phy_utmi_width;
136 int32_t phy_ulpi_ddr;
137 int32_t phy_ulpi_ext_vbus;
141 int32_t en_multiple_tx_fifo;
142 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
144 uint32_t tx_thr_length;
145 uint32_t rx_thr_length;
150 int32_t baseline_besl;
153 int32_t ahb_thr_ratio;
163 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
165 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
167 .dma_desc_enable = 0,
168 .dma_burst_size = -1,
170 .host_support_fs_ls_low_power = -1,
171 .host_ls_low_power_phy_clk = -1,
172 .enable_dynamic_fifo = 1,
173 .data_fifo_size = -1,
174 .dev_rx_fifo_size = 0x120,
175 .dev_nperio_tx_fifo_size = 0x10,
176 .dev_perio_tx_fifo_size = {
177 /* dev_perio_tx_fifo_size_1 */
195 .host_rx_fifo_size = -1,
196 .host_nperio_tx_fifo_size = -1,
197 .host_perio_tx_fifo_size = -1,
198 .max_transfer_size = -1,
199 .max_packet_count = -1,
203 .phy_utmi_width = -1,
205 .phy_ulpi_ext_vbus = -1,
209 .en_multiple_tx_fifo = -1,
210 .dev_tx_fifo_size = {
211 /* dev_tx_fifo_size */
249 #ifdef CONFIG_USB20_HOST
250 static struct dwc_otg_driver_module_params dwc_host_module_params = {
252 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
254 .dma_desc_enable = 0,
255 .dma_burst_size = -1,
257 .host_support_fs_ls_low_power = -1,
258 .host_ls_low_power_phy_clk = -1,
259 .enable_dynamic_fifo = -1,
260 .data_fifo_size = -1,
261 .dev_rx_fifo_size = -1,
262 .dev_nperio_tx_fifo_size = -1,
263 .dev_perio_tx_fifo_size = {
264 /* dev_perio_tx_fifo_size_1 */
282 .host_rx_fifo_size = -1,
283 .host_nperio_tx_fifo_size = -1,
284 .host_perio_tx_fifo_size = -1,
285 .max_transfer_size = -1,
286 .max_packet_count = -1,
290 .phy_utmi_width = -1,
292 .phy_ulpi_ext_vbus = -1,
296 .en_multiple_tx_fifo = -1,
297 .dev_tx_fifo_size = {
298 /* dev_tx_fifo_size */
338 * This function shows the Driver Version.
340 static ssize_t version_show(struct device_driver *dev, char *buf)
342 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
346 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
349 * Global Debug Level Mask.
351 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
354 * This function shows the driver Debug Level.
356 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
358 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
362 * This function stores the driver Debug Level.
364 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
367 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
371 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
374 extern void hcd_start(dwc_otg_core_if_t *core_if);
375 extern struct usb_hub *g_dwc_otg_root_hub20;
376 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
378 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
380 dwc_otg_device_t *otg_dev = core_if->otg_dev;
381 dctl_data_t dctl = {.d32 = 0 };
384 if (core_if->op_state == A_HOST) {
385 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
388 core_if->op_state = A_HOST;
390 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
391 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
392 dctl.b.sftdiscon = 1;
393 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
395 local_irq_save(flags);
396 cil_pcd_stop(core_if);
398 * Initialize the Core for Host mode.
401 dwc_otg_core_init(core_if);
402 dwc_otg_enable_global_interrupts(core_if);
403 cil_hcd_start(core_if);
404 local_irq_restore(flags);
407 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
409 dwc_otg_device_t *otg_dev = core_if->otg_dev;
412 local_irq_save(flags);
414 if (core_if->op_state == B_PERIPHERAL) {
416 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
419 core_if->op_state = B_PERIPHERAL;
420 cil_hcd_stop(core_if);
421 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
422 otg_dev->pcd->phy_suspend = 1;
423 otg_dev->pcd->vbus_status = 0;
424 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
426 /* Reset the Controller */
427 dwc_otg_core_reset(core_if);
429 dwc_otg_core_init(core_if);
430 dwc_otg_disable_global_interrupts(core_if);
431 cil_pcd_start(core_if);
433 local_irq_restore(flags);
436 static void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
438 gusbcfg_data_t usbcfg = {.d32 = 0 };
439 printk("!!!dwc_otg_set_force_mode\n");
440 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
442 case USB_MODE_FORCE_HOST:
443 usbcfg.b.force_host_mode = 1;
444 usbcfg.b.force_dev_mode = 0;
446 case USB_MODE_FORCE_DEVICE:
447 usbcfg.b.force_host_mode = 0;
448 usbcfg.b.force_dev_mode = 1;
450 case USB_MODE_NORMAL:
451 usbcfg.b.force_host_mode = 0;
452 usbcfg.b.force_dev_mode = 0;
455 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
458 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
460 dwc_otg_device_t *otg_dev = g_otgdev;
461 dwc_otg_core_if_t *core_if = otg_dev->core_if;
463 return sprintf(buf, "%d\n", core_if->usb_mode);
466 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
469 int new_mode = simple_strtoul(buf, NULL, 16);
470 dwc_otg_device_t *otg_dev = g_otgdev;
471 dwc_otg_core_if_t *core_if;
472 struct dwc_otg_platform_data *pldata;
477 core_if = otg_dev->core_if;
478 pldata = otg_dev->pldata;
480 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
482 if (core_if->usb_mode == new_mode) {
486 if (pldata->phy_status == USB_PHY_SUSPEND) {
487 pldata->clock_enable(pldata, 1);
488 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
492 case USB_MODE_FORCE_HOST:
493 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
495 core_if->usb_mode = new_mode;
496 dwc_otg_force_host(core_if);
497 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
498 core_if->usb_mode = new_mode;
499 if (dwc_otg_is_host_mode(core_if))
500 dwc_otg_set_force_mode(core_if, new_mode);
502 dwc_otg_force_host(core_if);
506 case USB_MODE_FORCE_DEVICE:
507 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
508 core_if->usb_mode = new_mode;
509 dwc_otg_force_device(core_if);
510 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
511 core_if->usb_mode = new_mode;
512 if (dwc_otg_is_device_mode(core_if))
513 dwc_otg_set_force_mode(core_if, new_mode);
515 dwc_otg_force_device(core_if);
519 case USB_MODE_NORMAL:
520 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
521 core_if->usb_mode = new_mode;
522 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
523 dwc_otg_set_force_mode(core_if, new_mode);
525 if (dwc_otg_is_host_mode(core_if)) {
526 dwc_otg_force_host(core_if);
528 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
530 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
531 core_if->usb_mode = new_mode;
532 dwc_otg_set_force_mode(core_if, new_mode);
534 if (dwc_otg_is_device_mode(core_if)) {
535 dwc_otg_force_device(core_if);
546 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
547 force_usb_mode_store);
549 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
552 dwc_otg_device_t *otg_dev = g_otgdev;
553 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
554 return sprintf(_buf, "%d\n", _pcd->conn_en);
558 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
559 const char *_buf, size_t _count)
561 int enable = simple_strtoul(_buf, NULL, 10);
562 dwc_otg_device_t *otg_dev = g_otgdev;
563 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
564 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
566 _pcd->conn_en = enable;
570 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
571 dwc_otg_conn_en_store);
573 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
575 dwc_otg_device_t *otg_dev = g_otgdev;
576 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
577 return sprintf(_buf, "%d\n", _pcd->vbus_status);
580 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
583 * This function is called during module intialization
584 * to pass module parameters to the DWC_OTG CORE.
586 static int set_parameters(dwc_otg_core_if_t *core_if,
587 struct dwc_otg_driver_module_params module_params)
592 if (module_params.otg_cap != -1) {
594 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
596 if (module_params.dma_enable != -1) {
598 dwc_otg_set_param_dma_enable(core_if,
599 module_params.dma_enable);
601 if (module_params.dma_desc_enable != -1) {
603 dwc_otg_set_param_dma_desc_enable(core_if,
604 module_params.dma_desc_enable);
606 if (module_params.opt != -1) {
607 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
609 if (module_params.dma_burst_size != -1) {
611 dwc_otg_set_param_dma_burst_size(core_if,
612 module_params.dma_burst_size);
614 if (module_params.host_support_fs_ls_low_power != -1) {
616 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
617 module_params.host_support_fs_ls_low_power);
619 if (module_params.enable_dynamic_fifo != -1) {
621 dwc_otg_set_param_enable_dynamic_fifo(core_if,
622 module_params.enable_dynamic_fifo);
624 if (module_params.data_fifo_size != -1) {
626 dwc_otg_set_param_data_fifo_size(core_if,
627 module_params.data_fifo_size);
629 if (module_params.dev_rx_fifo_size != -1) {
631 dwc_otg_set_param_dev_rx_fifo_size(core_if,
632 module_params.dev_rx_fifo_size);
634 if (module_params.dev_nperio_tx_fifo_size != -1) {
636 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
637 module_params.dev_nperio_tx_fifo_size);
639 if (module_params.host_rx_fifo_size != -1) {
641 dwc_otg_set_param_host_rx_fifo_size(core_if,
645 if (module_params.host_nperio_tx_fifo_size != -1) {
647 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
648 module_params.host_nperio_tx_fifo_size);
650 if (module_params.host_perio_tx_fifo_size != -1) {
652 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
653 module_params.host_perio_tx_fifo_size);
655 if (module_params.max_transfer_size != -1) {
657 dwc_otg_set_param_max_transfer_size(core_if,
658 module_params.max_transfer_size);
660 if (module_params.max_packet_count != -1) {
662 dwc_otg_set_param_max_packet_count(core_if,
663 module_params.max_packet_count);
665 if (module_params.host_channels != -1) {
667 dwc_otg_set_param_host_channels(core_if,
668 module_params.host_channels);
670 if (module_params.dev_endpoints != -1) {
672 dwc_otg_set_param_dev_endpoints(core_if,
673 module_params.dev_endpoints);
675 if (module_params.phy_type != -1) {
677 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
679 if (module_params.speed != -1) {
680 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
682 if (module_params.host_ls_low_power_phy_clk != -1) {
684 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
685 module_params.host_ls_low_power_phy_clk);
687 if (module_params.phy_ulpi_ddr != -1) {
689 dwc_otg_set_param_phy_ulpi_ddr(core_if,
690 module_params.phy_ulpi_ddr);
692 if (module_params.phy_ulpi_ext_vbus != -1) {
694 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
695 module_params.phy_ulpi_ext_vbus);
697 if (module_params.phy_utmi_width != -1) {
699 dwc_otg_set_param_phy_utmi_width(core_if,
700 module_params.phy_utmi_width);
702 if (module_params.ulpi_fs_ls != -1) {
704 dwc_otg_set_param_ulpi_fs_ls(core_if,
705 module_params.ulpi_fs_ls);
707 if (module_params.ts_dline != -1) {
709 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
711 if (module_params.i2c_enable != -1) {
713 dwc_otg_set_param_i2c_enable(core_if,
714 module_params.i2c_enable);
716 if (module_params.en_multiple_tx_fifo != -1) {
718 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
719 module_params.en_multiple_tx_fifo);
721 for (i = 0; i < 15; i++) {
722 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
724 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
725 module_params.dev_perio_tx_fifo_size
730 for (i = 0; i < 15; i++) {
731 if (module_params.dev_tx_fifo_size[i] != -1) {
732 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
733 module_params.dev_tx_fifo_size
737 if (module_params.thr_ctl != -1) {
739 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
741 if (module_params.mpi_enable != -1) {
743 dwc_otg_set_param_mpi_enable(core_if,
744 module_params.mpi_enable);
746 if (module_params.pti_enable != -1) {
748 dwc_otg_set_param_pti_enable(core_if,
749 module_params.pti_enable);
751 if (module_params.lpm_enable != -1) {
753 dwc_otg_set_param_lpm_enable(core_if,
754 module_params.lpm_enable);
756 if (module_params.besl_enable != -1) {
758 dwc_otg_set_param_besl_enable(core_if,
759 module_params.besl_enable);
761 if (module_params.baseline_besl != -1) {
763 dwc_otg_set_param_baseline_besl(core_if,
764 module_params.baseline_besl);
766 if (module_params.deep_besl != -1) {
768 dwc_otg_set_param_deep_besl(core_if,
769 module_params.deep_besl);
771 if (module_params.ic_usb_cap != -1) {
773 dwc_otg_set_param_ic_usb_cap(core_if,
774 module_params.ic_usb_cap);
776 if (module_params.tx_thr_length != -1) {
778 dwc_otg_set_param_tx_thr_length(core_if,
782 if (module_params.rx_thr_length != -1) {
784 dwc_otg_set_param_rx_thr_length(core_if,
785 module_params.rx_thr_length);
787 if (module_params.ahb_thr_ratio != -1) {
789 dwc_otg_set_param_ahb_thr_ratio(core_if,
793 if (module_params.power_down != -1) {
795 dwc_otg_set_param_power_down(core_if,
796 module_params.power_down);
798 if (module_params.reload_ctl != -1) {
800 dwc_otg_set_param_reload_ctl(core_if,
801 module_params.reload_ctl);
804 if (module_params.dev_out_nak != -1) {
806 dwc_otg_set_param_dev_out_nak(core_if,
807 module_params.dev_out_nak);
810 if (module_params.cont_on_bna != -1) {
812 dwc_otg_set_param_cont_on_bna(core_if,
813 module_params.cont_on_bna);
816 if (module_params.ahb_single != -1) {
818 dwc_otg_set_param_ahb_single(core_if,
819 module_params.ahb_single);
822 if (module_params.otg_ver != -1) {
824 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
826 if (module_params.adp_enable != -1) {
828 dwc_otg_set_param_adp_enable(core_if,
829 module_params.adp_enable);
835 * This function is the top level interrupt handler for the Common
836 * (Device and host modes) interrupts.
838 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
840 int32_t retval = IRQ_NONE;
842 retval = dwc_otg_handle_common_intr(dev);
844 /* S3C2410X_CLEAR_EINTPEND(); */
846 return IRQ_RETVAL(retval);
849 #ifdef CONFIG_USB20_HOST
851 * This function is called when a lm_device is unregistered with the
852 * dwc_otg_driver. This happens, for example, when the rmmod command is
853 * executed. The device may or may not be electrically present. If it is
854 * present, the driver stops device processing. Any resources used on behalf
855 * of this device are freed.
859 static int host20_driver_remove(struct platform_device *_dev)
862 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
863 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
866 /* Memory allocation for the dwc_otg_device failed. */
867 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
870 #ifndef DWC_DEVICE_ONLY
874 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
879 #ifndef DWC_HOST_ONLY
883 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
891 if (otg_dev->common_irq_installed) {
892 /* free_irq(_dev->irq, otg_dev); */
893 free_irq(platform_get_irq(_dev, 0), otg_dev);
895 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
900 if (otg_dev->core_if) {
901 dwc_otg_cil_remove(otg_dev->core_if);
903 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
908 * Remove the device attributes
910 dwc_otg_attr_remove(_dev);
915 if (otg_dev->os_dep.base) {
916 iounmap(otg_dev->os_dep.base);
921 * Clear the drvdata pointer.
924 dwc_set_device_platform_data(_dev, 0);
929 static const struct of_device_id usb20_host_of_match[] = {
931 .compatible = "rockchip,rk3188_usb20_host",
932 .data = &usb20host_pdata[RK3188_USB_CTLR],
935 .compatible = "rockchip,rk3288_usb20_host",
936 .data = &usb20host_pdata[RK3288_USB_CTLR],
941 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
944 * This function is called when an lm_device is bound to a
945 * dwc_otg_driver. It creates the driver components required to
946 * control the device (CIL, HCD, and PCD) and it initializes the
947 * device. The driver components are stored in a dwc_otg_device
948 * structure. A reference to the dwc_otg_device is saved in the
949 * lm_device. This allows the driver to access the dwc_otg_device
950 * structure on subsequent calls to driver methods for this device.
952 * @param _dev Bus device
954 static int host20_driver_probe(struct platform_device *_dev)
958 struct resource *res_base;
959 dwc_otg_device_t *dwc_otg_device;
960 struct device *dev = &_dev->dev;
961 struct device_node *node = _dev->dev.of_node;
962 struct dwc_otg_platform_data *pldata;
963 struct usb20host_pdata_id *p;
964 const struct of_device_id *match =
965 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
968 p = (struct usb20host_pdata_id *)match->data;
970 dev_err(dev, "usb20host match failed\n");
974 dev->platform_data = p->pdata;
975 pldata = dev->platform_data;
979 dev_err(dev, "device node not found\n");
986 if (pldata->clock_init) {
987 pldata->clock_init(pldata);
988 pldata->clock_enable(pldata, 1);
991 if (pldata->phy_suspend)
992 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
994 if (pldata->soft_reset)
995 pldata->soft_reset();
997 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
999 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1001 if (!dwc_otg_device) {
1002 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1007 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1008 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1011 * Map the DWC_otg Core memory into virtual address space.
1014 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1016 if (!dwc_otg_device->os_dep.base) {
1017 dev_err(&_dev->dev, "ioremap() failed\n");
1018 DWC_FREE(dwc_otg_device);
1022 dev_dbg(&_dev->dev, "base=0x%08x\n",
1023 (unsigned)dwc_otg_device->os_dep.base);
1026 * Initialize driver data to point to the global DWC_otg
1030 dwc_set_device_platform_data(_dev, dwc_otg_device);
1031 pldata->privdata = dwc_otg_device;
1032 dwc_otg_device->pldata = (void *)pldata;
1034 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1036 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1038 if (!dwc_otg_device->core_if) {
1039 dev_err(&_dev->dev, "CIL initialization failed!\n");
1044 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1047 * Attempt to ensure this device is really a DWC_otg Controller.
1048 * Read and verify the SNPSID register contents. The value should be
1049 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1050 * as in "OTG version 2.XX" or "OTG version 3.XX".
1053 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1055 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1057 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1058 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1064 * Validate parameter values.
1066 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1072 * Create Device Attributes in sysfs
1074 dwc_otg_attr_create(_dev);
1077 * Disable the global interrupt until all the interrupt
1078 * handlers are installed.
1080 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1083 * Install the interrupt handler for the common interrupts before
1084 * enabling common interrupts in core_init below.
1086 irq = platform_get_irq(_dev, 0);
1087 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1088 retval = request_irq(irq, dwc_otg_common_irq,
1089 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1091 DWC_ERROR("request of irq%d failed\n", irq);
1095 dwc_otg_device->common_irq_installed = 1;
1099 * Initialize the DWC_otg core.
1100 * In order to reduce the time of initialization,
1101 * we do core soft reset after connection detected.
1103 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1106 * Initialize the HCD
1108 retval = host20_hcd_init(_dev);
1110 DWC_ERROR("hcd_init failed\n");
1111 dwc_otg_device->hcd = NULL;
1115 clk_set_rate(pldata->phyclk_480m, 480000000);
1117 * Enable the global interrupt after all the interrupt
1118 * handlers are installed if there is no ADP support else
1119 * perform initial actions required for Internal ADP logic.
1121 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1122 if (pldata->phy_status == USB_PHY_ENABLED) {
1123 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1125 pldata->clock_enable(pldata, 0);
1127 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1129 dwc_otg_adp_start(dwc_otg_device->core_if,
1130 dwc_otg_is_host_mode(dwc_otg_device->
1136 host20_driver_remove(_dev);
1138 if (pldata->clock_enable)
1139 pldata->clock_enable(pldata, 0);
1145 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1151 static int dwc_otg_driver_resume(struct platform_device *_dev)
1156 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1158 struct device *dev = &_dev->dev;
1159 dwc_otg_device_t *otg_dev = dev->platform_data;
1160 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1161 dctl_data_t dctl = {.d32 = 0 };
1163 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1164 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1165 if (dwc_otg_is_host_mode(core_if)) {
1166 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1167 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1169 /* soft disconnect */
1171 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1172 dctl.b.sftdiscon = 1;
1173 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1176 /* Clear any pending interrupts */
1177 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1182 * This structure defines the methods to be called by a bus driver
1183 * during the lifecycle of a device on that bus. Both drivers and
1184 * devices are registered with a bus driver. The bus driver matches
1185 * devices to drivers based on information in the device and driver
1188 * The probe function is called when the bus driver matches a device
1189 * to this driver. The remove function is called when a device is
1190 * unregistered with the bus driver.
1192 #ifdef CONFIG_USB20_HOST
1193 static struct platform_driver dwc_host_driver = {
1195 .name = (char *)dwc_host20_driver_name,
1196 .of_match_table = of_match_ptr(usb20_host_of_match),
1198 .probe = host20_driver_probe,
1199 .remove = host20_driver_remove,
1200 .suspend = dwc_otg_driver_suspend,
1201 .resume = dwc_otg_driver_resume,
1205 #ifdef CONFIG_USB20_OTG
1207 * This function is called when a lm_device is unregistered with the
1208 * dwc_otg_driver. This happens, for example, when the rmmod command is
1209 * executed. The device may or may not be electrically present. If it is
1210 * present, the driver stops device processing. Any resources used on behalf
1211 * of this device are freed.
1215 static int otg20_driver_remove(struct platform_device *_dev)
1218 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1219 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1222 /* Memory allocation for the dwc_otg_device failed. */
1223 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1226 #ifndef DWC_DEVICE_ONLY
1230 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1235 #ifndef DWC_HOST_ONLY
1239 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1246 if (otg_dev->common_irq_installed) {
1247 /* free_irq(_dev->irq, otg_dev); */
1248 free_irq(platform_get_irq(_dev, 0), otg_dev);
1250 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1255 if (otg_dev->core_if) {
1256 dwc_otg_cil_remove(otg_dev->core_if);
1258 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1263 * Remove the device attributes
1265 dwc_otg_attr_remove(_dev);
1268 * Return the memory.
1270 if (otg_dev->os_dep.base)
1271 iounmap(otg_dev->os_dep.base);
1275 * Clear the drvdata pointer.
1278 dwc_set_device_platform_data(_dev, 0);
1283 static const struct of_device_id usb20_otg_of_match[] = {
1285 .compatible = "rockchip,rk3188_usb20_otg",
1286 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1289 .compatible = "rockchip,rk3288_usb20_otg",
1290 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1296 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1299 * This function is called when an lm_device is bound to a
1300 * dwc_otg_driver. It creates the driver components required to
1301 * control the device (CIL, HCD, and PCD) and it initializes the
1302 * device. The driver components are stored in a dwc_otg_device
1303 * structure. A reference to the dwc_otg_device is saved in the
1304 * lm_device. This allows the driver to access the dwc_otg_device
1305 * structure on subsequent calls to driver methods for this device.
1307 * @param _dev Bus device
1309 static int otg20_driver_probe(struct platform_device *_dev)
1314 struct resource *res_base;
1315 dwc_otg_device_t *dwc_otg_device;
1316 struct device *dev = &_dev->dev;
1317 struct device_node *node = _dev->dev.of_node;
1318 struct dwc_otg_platform_data *pldata;
1319 struct usb20otg_pdata_id *p;
1320 const struct of_device_id *match =
1321 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1324 p = (struct usb20otg_pdata_id *)match->data;
1326 dev_err(dev, "usb20otg match failed\n");
1330 dev->platform_data = p->pdata;
1331 /* dev->platform_data = &usb20otg_pdata; */
1332 pldata = dev->platform_data;
1336 dev_err(dev, "device node not found\n");
1339 /*todo : move to usbdev_rk-XX.c */
1340 if (pldata->hw_init)
1343 if (pldata->clock_init) {
1344 pldata->clock_init(pldata);
1345 pldata->clock_enable(pldata, 1);
1348 if (pldata->phy_suspend)
1349 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1351 if (pldata->dwc_otg_uart_mode)
1352 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1354 /* do reset later, because reset need about
1355 * 100ms to ensure otg id state change.
1358 if(pldata->soft_reset)
1359 pldata->soft_reset();
1363 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1365 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1367 if (!dwc_otg_device) {
1368 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1373 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1374 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1377 * Map the DWC_otg Core memory into virtual address space.
1380 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1382 if (!dwc_otg_device->os_dep.base) {
1383 dev_err(&_dev->dev, "ioremap() failed\n");
1384 DWC_FREE(dwc_otg_device);
1388 dev_dbg(&_dev->dev, "base=0x%08x\n",
1389 (unsigned)dwc_otg_device->os_dep.base);
1392 * Initialize driver data to point to the global DWC_otg
1396 g_otgdev = dwc_otg_device;
1397 pldata->privdata = dwc_otg_device;
1398 dwc_otg_device->pldata = pldata;
1400 dwc_set_device_platform_data(_dev, dwc_otg_device);
1402 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1404 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1405 if (!dwc_otg_device->core_if) {
1406 dev_err(&_dev->dev, "CIL initialization failed!\n");
1411 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1413 * Attempt to ensure this device is really a DWC_otg Controller.
1414 * Read and verify the SNPSID register contents. The value should be
1415 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1416 * as in "OTG version 2.XX" or "OTG version 3.XX".
1419 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1421 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1423 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1424 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1430 * Validate parameter values.
1432 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1438 * Create Device Attributes in sysfs
1440 dwc_otg_attr_create(_dev);
1443 * Disable the global interrupt until all the interrupt
1444 * handlers are installed.
1446 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1449 * Install the interrupt handler for the common interrupts before
1450 * enabling common interrupts in core_init below.
1452 irq = platform_get_irq(_dev, 0);
1453 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1454 retval = request_irq(irq, dwc_otg_common_irq,
1455 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1457 DWC_ERROR("request of irq%d failed\n", irq);
1461 dwc_otg_device->common_irq_installed = 1;
1465 * Initialize the DWC_otg core.
1466 * In order to reduce the time of initialization,
1467 * we do core soft reset after connection detected.
1469 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1472 * 0 - USB_MODE_NORMAL
1473 * 1 - USB_MODE_FORCE_HOST
1474 * 2 - USB_MODE_FORCE_DEVICE
1476 of_property_read_u32(node, "rockchip,usb-mode", &val);
1477 dwc_otg_device->core_if->usb_mode = val;
1479 #ifndef DWC_HOST_ONLY
1481 * Initialize the PCD
1483 retval = pcd_init(_dev);
1485 DWC_ERROR("pcd_init failed\n");
1486 dwc_otg_device->pcd = NULL;
1490 #ifndef DWC_DEVICE_ONLY
1492 * Initialize the HCD
1494 retval = otg20_hcd_init(_dev);
1496 DWC_ERROR("hcd_init failed\n");
1497 dwc_otg_device->hcd = NULL;
1502 * Enable the global interrupt after all the interrupt
1503 * handlers are installed if there is no ADP support else
1504 * perform initial actions required for Internal ADP logic.
1506 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1507 if (pldata->phy_status == USB_PHY_ENABLED) {
1508 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1510 pldata->clock_enable(pldata, 0);
1512 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1514 dwc_otg_adp_start(dwc_otg_device->core_if,
1515 dwc_otg_is_host_mode(dwc_otg_device->
1521 otg20_driver_remove(_dev);
1524 if (pldata->clock_enable)
1525 pldata->clock_enable(pldata, 0);
1530 static struct platform_driver dwc_otg_driver = {
1532 .name = (char *)dwc_otg20_driver_name,
1533 .of_match_table = of_match_ptr(usb20_otg_of_match),
1535 .probe = otg20_driver_probe,
1536 .remove = otg20_driver_remove,
1537 .suspend = dwc_otg_driver_suspend,
1538 .resume = dwc_otg_driver_resume,
1539 .shutdown = dwc_otg_driver_shutdown,
1543 void rk_usb_power_up(void)
1545 struct dwc_otg_platform_data *pldata_otg;
1546 struct dwc_otg_platform_data *pldata_host;
1547 struct rkehci_platform_data *pldata_ehci;
1549 if (cpu_is_rk3288()) {
1550 #ifdef CONFIG_RK_USB_UART
1551 /* enable USB bypass UART function */
1552 writel_relaxed(0x00c00000 | usb_to_uart_status,
1553 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1556 /* unset siddq,the analog blocks are powered up */
1557 #ifdef CONFIG_USB20_OTG
1558 pldata_otg = &usb20otg_pdata_rk3288;
1560 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1561 writel_relaxed((0x01 << 13) << 16,
1563 RK3288_GRF_UOC0_CON0);
1566 #ifdef CONFIG_USB20_HOST
1567 pldata_host = &usb20host_pdata_rk3288;
1569 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1570 writel_relaxed((0x01 << 13) << 16,
1572 RK3288_GRF_UOC2_CON0);
1575 #ifdef CONFIG_USB_EHCI_RK
1576 pldata_ehci = &rkehci_pdata_rk3288;
1578 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1579 writel_relaxed((0x01 << 13) << 16,
1581 RK3288_GRF_UOC1_CON0);
1588 void rk_usb_power_down(void)
1590 struct dwc_otg_platform_data *pldata_otg;
1591 struct dwc_otg_platform_data *pldata_host;
1592 struct rkehci_platform_data *pldata_ehci;
1594 if (cpu_is_rk3288()) {
1595 #ifdef CONFIG_RK_USB_UART
1596 /* disable USB bypass UART function */
1597 usb_to_uart_status =
1598 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1599 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1601 /* set siddq,the analog blocks are powered down
1603 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1604 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1605 * and TESTBURNIN are set to 1'b0.
1606 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1607 #ifdef CONFIG_USB20_OTG
1608 pldata_otg = &usb20otg_pdata_rk3288;
1610 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1611 writel_relaxed((0x01 << 13) |
1612 ((0x01 << 13) << 16),
1614 RK3288_GRF_UOC0_CON0);
1617 #ifdef CONFIG_USB20_HOST
1618 pldata_host = &usb20host_pdata_rk3288;
1620 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1621 writel_relaxed((0x01 << 13) |
1622 ((0x01 << 13) << 16),
1624 RK3288_GRF_UOC2_CON0);
1627 #ifdef CONFIG_USB_EHCI_RK
1628 pldata_ehci = &rkehci_pdata_rk3288;
1630 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1631 writel_relaxed((0x01 << 13) |
1632 ((0x01 << 13) << 16),
1634 RK3288_GRF_UOC1_CON0);
1640 EXPORT_SYMBOL(rk_usb_power_up);
1641 EXPORT_SYMBOL(rk_usb_power_down);
1643 * This function is called when the dwc_otg_driver is installed with the
1644 * insmod command. It registers the dwc_otg_driver structure with the
1645 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1646 * to be called. In addition, the bus driver will automatically expose
1647 * attributes defined for the device and driver in the special sysfs file
1652 static int __init dwc_otg_driver_init(void)
1657 #ifdef CONFIG_USB20_OTG
1658 /* register otg20 */
1659 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1660 DWC_DRIVER_VERSION);
1662 retval = platform_driver_register(&dwc_otg_driver);
1664 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1669 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1671 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1673 driver_create_file(&dwc_otg_driver.driver,
1674 &driver_attr_dwc_otg_conn_en);
1676 driver_create_file(&dwc_otg_driver.driver,
1677 &driver_attr_vbus_status);
1679 driver_create_file(&dwc_otg_driver.driver,
1680 &driver_attr_force_usb_mode);
1684 /* register host20 */
1685 #ifdef CONFIG_USB20_HOST
1686 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1687 DWC_DRIVER_VERSION);
1689 retval = platform_driver_register(&dwc_host_driver);
1691 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1696 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1698 driver_create_file(&dwc_host_driver.driver,
1699 &driver_attr_debuglevel);
1704 module_init(dwc_otg_driver_init);
1707 * This function is called when the driver is removed from the kernel
1708 * with the rmmod command. The driver unregisters itself with its bus
1712 static void __exit dwc_otg_driver_cleanup(void)
1714 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1716 #ifdef CONFIG_USB20_HOST
1718 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1719 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1720 platform_driver_unregister(&dwc_host_driver);
1721 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1724 #ifdef CONFIG_USB20_OTG
1726 driver_remove_file(&dwc_otg_driver.driver,
1727 &driver_attr_dwc_otg_conn_en);
1728 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1729 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1730 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1731 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1732 platform_driver_unregister(&dwc_otg_driver);
1733 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1737 module_exit(dwc_otg_driver_cleanup);
1739 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1740 MODULE_AUTHOR("Synopsys Inc.");
1741 MODULE_LICENSE("GPL");
1743 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1744 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1745 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1746 MODULE_PARM_DESC(opt, "OPT Mode");
1747 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1748 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1750 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1752 MODULE_PARM_DESC(dma_desc_enable,
1753 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1755 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1757 MODULE_PARM_DESC(dma_burst_size,
1758 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1759 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1760 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1761 module_param_named(host_support_fs_ls_low_power,
1762 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1764 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1765 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1766 module_param_named(host_ls_low_power_phy_clk,
1767 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1768 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1769 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1770 module_param_named(enable_dynamic_fifo,
1771 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1772 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1773 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1775 MODULE_PARM_DESC(data_fifo_size,
1776 "Total number of words in the data FIFO memory 32-32768");
1777 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1779 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1780 module_param_named(dev_nperio_tx_fifo_size,
1781 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1782 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1783 "Number of words in the non-periodic Tx FIFO 16-32768");
1784 module_param_named(dev_perio_tx_fifo_size_1,
1785 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1786 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1787 "Number of words in the periodic Tx FIFO 4-768");
1788 module_param_named(dev_perio_tx_fifo_size_2,
1789 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1790 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1791 "Number of words in the periodic Tx FIFO 4-768");
1792 module_param_named(dev_perio_tx_fifo_size_3,
1793 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1794 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1795 "Number of words in the periodic Tx FIFO 4-768");
1796 module_param_named(dev_perio_tx_fifo_size_4,
1797 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1798 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1799 "Number of words in the periodic Tx FIFO 4-768");
1800 module_param_named(dev_perio_tx_fifo_size_5,
1801 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1802 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1803 "Number of words in the periodic Tx FIFO 4-768");
1804 module_param_named(dev_perio_tx_fifo_size_6,
1805 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1806 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1807 "Number of words in the periodic Tx FIFO 4-768");
1808 module_param_named(dev_perio_tx_fifo_size_7,
1809 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1810 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1811 "Number of words in the periodic Tx FIFO 4-768");
1812 module_param_named(dev_perio_tx_fifo_size_8,
1813 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1814 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1815 "Number of words in the periodic Tx FIFO 4-768");
1816 module_param_named(dev_perio_tx_fifo_size_9,
1817 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1818 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1819 "Number of words in the periodic Tx FIFO 4-768");
1820 module_param_named(dev_perio_tx_fifo_size_10,
1821 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1822 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1823 "Number of words in the periodic Tx FIFO 4-768");
1824 module_param_named(dev_perio_tx_fifo_size_11,
1825 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1826 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1827 "Number of words in the periodic Tx FIFO 4-768");
1828 module_param_named(dev_perio_tx_fifo_size_12,
1829 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1830 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1831 "Number of words in the periodic Tx FIFO 4-768");
1832 module_param_named(dev_perio_tx_fifo_size_13,
1833 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1834 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1835 "Number of words in the periodic Tx FIFO 4-768");
1836 module_param_named(dev_perio_tx_fifo_size_14,
1837 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1838 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1839 "Number of words in the periodic Tx FIFO 4-768");
1840 module_param_named(dev_perio_tx_fifo_size_15,
1841 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1842 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1843 "Number of words in the periodic Tx FIFO 4-768");
1844 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1846 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1847 module_param_named(host_nperio_tx_fifo_size,
1848 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1849 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1850 "Number of words in the non-periodic Tx FIFO 16-32768");
1851 module_param_named(host_perio_tx_fifo_size,
1852 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1853 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1854 "Number of words in the host periodic Tx FIFO 16-32768");
1855 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1857 /** @todo Set the max to 512K, modify checks */
1858 MODULE_PARM_DESC(max_transfer_size,
1859 "The maximum transfer size supported in bytes 2047-65535");
1860 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1862 MODULE_PARM_DESC(max_packet_count,
1863 "The maximum number of packets in a transfer 15-511");
1864 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1866 MODULE_PARM_DESC(host_channels,
1867 "The number of host channel registers to use 1-16");
1868 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1870 MODULE_PARM_DESC(dev_endpoints,
1871 "The number of endpoints in addition to EP0 available for device mode 1-15");
1872 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1873 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1874 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1876 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1877 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1878 MODULE_PARM_DESC(phy_ulpi_ddr,
1879 "ULPI at double or single data rate 0=Single 1=Double");
1880 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1882 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1883 "ULPI PHY using internal or external vbus 0=Internal");
1884 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1885 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1886 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1887 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1888 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1889 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1890 module_param_named(debug, g_dbg_lvl, int, 0444);
1891 MODULE_PARM_DESC(debug, "");
1893 module_param_named(en_multiple_tx_fifo,
1894 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1895 MODULE_PARM_DESC(en_multiple_tx_fifo,
1896 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1897 module_param_named(dev_tx_fifo_size_1,
1898 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1899 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1900 module_param_named(dev_tx_fifo_size_2,
1901 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1902 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1903 module_param_named(dev_tx_fifo_size_3,
1904 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1905 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1906 module_param_named(dev_tx_fifo_size_4,
1907 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1908 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1909 module_param_named(dev_tx_fifo_size_5,
1910 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1911 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1912 module_param_named(dev_tx_fifo_size_6,
1913 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1914 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1915 module_param_named(dev_tx_fifo_size_7,
1916 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1917 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1918 module_param_named(dev_tx_fifo_size_8,
1919 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1920 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1921 module_param_named(dev_tx_fifo_size_9,
1922 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1923 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1924 module_param_named(dev_tx_fifo_size_10,
1925 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1926 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1927 module_param_named(dev_tx_fifo_size_11,
1928 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1929 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1930 module_param_named(dev_tx_fifo_size_12,
1931 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1932 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1933 module_param_named(dev_tx_fifo_size_13,
1934 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1935 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1936 module_param_named(dev_tx_fifo_size_14,
1937 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1938 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1939 module_param_named(dev_tx_fifo_size_15,
1940 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1941 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1943 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1944 MODULE_PARM_DESC(thr_ctl,
1945 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1946 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1948 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1949 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1951 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1953 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1954 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1955 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1956 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1958 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
1959 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
1960 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
1962 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
1963 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
1964 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
1966 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1967 MODULE_PARM_DESC(ic_usb_cap,
1968 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1969 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
1971 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
1972 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
1973 MODULE_PARM_DESC(power_down, "Power Down Mode");
1974 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
1975 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
1976 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
1977 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
1978 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
1979 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
1980 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
1981 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
1982 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
1983 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
1984 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
1985 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
1987 /** @page "Module Parameters"
1989 * The following parameters may be specified when starting the module.
1990 * These parameters define how the DWC_otg controller should be
1991 * configured. Parameter values are passed to the CIL initialization
1992 * function dwc_otg_cil_init
1994 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1998 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2002 <td>Specifies the OTG capabilities. The driver will automatically detect the
2003 value for this parameter if none is specified.
2004 - 0: HNP and SRP capable (default, if available)
2005 - 1: SRP Only capable
2006 - 2: No HNP/SRP capable
2011 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2012 The driver will automatically detect the value for this parameter if none is
2015 - 1: DMA (default, if available)
2019 <td>dma_burst_size</td>
2020 <td>The DMA Burst size (applicable only for External DMA Mode).
2021 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2026 <td>Specifies the maximum speed of operation in host and device mode. The
2027 actual speed depends on the speed of the attached device and the value of
2029 - 0: High Speed (default)
2034 <td>host_support_fs_ls_low_power</td>
2035 <td>Specifies whether low power mode is supported when attached to a Full
2036 Speed or Low Speed device in host mode.
2037 - 0: Don't support low power mode (default)
2038 - 1: Support low power mode
2042 <td>host_ls_low_power_phy_clk</td>
2043 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2044 Speed device in host mode. This parameter is applicable only if
2045 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2046 - 0: 48 MHz (default)
2051 <td>enable_dynamic_fifo</td>
2052 <td> Specifies whether FIFOs may be resized by the driver software.
2053 - 0: Use cC FIFO size parameters
2054 - 1: Allow dynamic FIFO sizing (default)
2058 <td>data_fifo_size</td>
2059 <td>Total number of 4-byte words in the data FIFO memory. This memory
2060 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2061 - Values: 32 to 32768 (default 8192)
2063 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2067 <td>dev_rx_fifo_size</td>
2068 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2069 FIFO sizing is enabled.
2070 - Values: 16 to 32768 (default 1064)
2074 <td>dev_nperio_tx_fifo_size</td>
2075 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2076 dynamic FIFO sizing is enabled.
2077 - Values: 16 to 32768 (default 1024)
2081 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2082 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2083 when dynamic FIFO sizing is enabled.
2084 - Values: 4 to 768 (default 256)
2088 <td>host_rx_fifo_size</td>
2089 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2091 - Values: 16 to 32768 (default 1024)
2095 <td>host_nperio_tx_fifo_size</td>
2096 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2097 dynamic FIFO sizing is enabled in the core.
2098 - Values: 16 to 32768 (default 1024)
2102 <td>host_perio_tx_fifo_size</td>
2103 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2105 - Values: 16 to 32768 (default 1024)
2109 <td>max_transfer_size</td>
2110 <td>The maximum transfer size supported in bytes.
2111 - Values: 2047 to 65,535 (default 65,535)
2115 <td>max_packet_count</td>
2116 <td>The maximum number of packets in a transfer.
2117 - Values: 15 to 511 (default 511)
2121 <td>host_channels</td>
2122 <td>The number of host channel registers to use.
2123 - Values: 1 to 16 (default 12)
2125 Note: The FPGA configuration supports a maximum of 12 host channels.
2129 <td>dev_endpoints</td>
2130 <td>The number of endpoints in addition to EP0 available for device mode
2132 - Values: 1 to 15 (default 6 IN and OUT)
2134 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2140 <td>Specifies the type of PHY interface to use. By default, the driver will
2141 automatically detect the phy_type.
2143 - 1: UTMI+ (default, if available)
2148 <td>phy_utmi_width</td>
2149 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2150 phy_type of UTMI+. Also, this parameter is applicable only if the
2151 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2152 core has been configured to work at either data path width.
2153 - Values: 8 or 16 bits (default 16)
2157 <td>phy_ulpi_ddr</td>
2158 <td>Specifies whether the ULPI operates at double or single data rate. This
2159 parameter is only applicable if phy_type is ULPI.
2160 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2161 - 1: double data rate ULPI interface with 4 bit wide data bus
2166 <td>Specifies whether to use the I2C interface for full speed PHY. This
2167 parameter is only applicable if PHY_TYPE is FS.
2168 - 0: Disabled (default)
2174 <td>Specifies whether to use ULPI FS/LS mode only.
2175 - 0: Disabled (default)
2181 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2182 - 0: Disabled (default)
2187 <td>en_multiple_tx_fifo</td>
2188 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2189 The driver will automatically detect the value for this parameter if none is
2192 - 1: Enabled (default, if available)
2196 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2197 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2198 when dynamic FIFO sizing is enabled.
2199 - Values: 4 to 768 (default 256)
2203 <td>tx_thr_length</td>
2204 <td>Transmit Threshold length in 32 bit double words
2205 - Values: 8 to 128 (default 64)
2209 <td>rx_thr_length</td>
2210 <td>Receive Threshold length in 32 bit double words
2211 - Values: 8 to 128 (default 64)
2216 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2217 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2218 Rx transfers accordingly.
2219 The driver will automatically detect the value for this parameter if none is
2221 - Values: 0 to 7 (default 0)
2222 Bit values indicate:
2223 - 0: Thresholding disabled
2224 - 1: Thresholding enabled
2228 <td>dma_desc_enable</td>
2229 <td>Specifies whether to enable Descriptor DMA mode.
2230 The driver will automatically detect the value for this parameter if none is
2232 - 0: Descriptor DMA disabled
2233 - 1: Descriptor DMA (default, if available)
2238 <td>Specifies whether to enable MPI enhancement mode.
2239 The driver will automatically detect the value for this parameter if none is
2241 - 0: MPI disabled (default)
2247 <td>Specifies whether to enable PTI enhancement support.
2248 The driver will automatically detect the value for this parameter if none is
2250 - 0: PTI disabled (default)
2256 <td>Specifies whether to enable LPM support.
2257 The driver will automatically detect the value for this parameter if none is
2260 - 1: LPM enable (default, if available)
2264 <td>besl_enable</td>
2265 <td>Specifies whether to enable LPM Errata support.
2266 The driver will automatically detect the value for this parameter if none is
2268 - 0: LPM Errata disabled (default)
2269 - 1: LPM Errata enable
2273 <td>baseline_besl</td>
2274 <td>Specifies the baseline besl value.
2275 - Values: 0 to 15 (default 0)
2280 <td>Specifies the deep besl value.
2281 - Values: 0 to 15 (default 15)
2286 <td>Specifies whether to enable IC_USB capability.
2287 The driver will automatically detect the value for this parameter if none is
2289 - 0: IC_USB disabled (default, if available)
2294 <td>ahb_thr_ratio</td>
2295 <td>Specifies AHB Threshold ratio.
2296 - Values: 0 to 3 (default 0)
2301 <td>Specifies Power Down(Hibernation) Mode.
2302 The driver will automatically detect the value for this parameter if none is
2304 - 0: Power Down disabled (default)
2305 - 2: Power Down enabled
2310 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2311 run time. The driver will automatically detect the value for this parameter if
2312 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2313 the core might misbehave.
2314 - 0: Reload Control disabled (default)
2315 - 1: Reload Control enabled
2319 <td>dev_out_nak</td>
2320 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2321 The driver will automatically detect the value for this parameter if
2322 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2323 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2324 - 1: The core sets NAK after Bulk OUT transfer complete
2328 <td>cont_on_bna</td>
2329 <td>Specifies whether Enable Continue on BNA enabled or no.
2330 After receiving BNA interrupt the core disables the endpoint,when the
2331 endpoint is re-enabled by the application the
2332 - 0: Core starts processing from the DOEPDMA descriptor (default)
2333 - 1: Core starts processing from the descriptor which received the BNA.
2334 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2339 <td>This bit when programmed supports SINGLE transfers for remainder data
2340 in a transfer for DMA mode of operation.
2341 - 0: The remainder data will be sent using INCR burst size (default)
2342 - 1: The remainder data will be sent using SINGLE burst size.
2347 <td>Specifies whether ADP feature is enabled.
2348 The driver will automatically detect the value for this parameter if none is
2350 - 0: ADP feature disabled (default)
2351 - 1: ADP feature enabled
2356 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2358 - 0: OTG 2.0 support disabled (default)
2359 - 1: OTG 2.0 support enabled