mmc: sdhci-of-arasan: wakeup genpd when being in suspend
[firefly-linux-kernel-4.4.55.git] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or (at
9  * your option) any later version.
10  *
11  * Thanks to the following companies for their support:
12  *
13  *     - JMicron (hardware and technical support)
14  */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42         defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57                                         struct mmc_data *data);
58 static int sdhci_do_get_cd(struct sdhci_host *host);
59
60 #ifdef CONFIG_PM
61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
65 #else
66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67 {
68         return 0;
69 }
70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 {
72         return 0;
73 }
74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
75 {
76 }
77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
78 {
79 }
80 #endif
81
82 static void sdhci_dumpregs(struct sdhci_host *host)
83 {
84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
85                 mmc_hostname(host->mmc));
86
87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89                 sdhci_readw(host, SDHCI_HOST_VERSION));
90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94                 sdhci_readl(host, SDHCI_ARGUMENT),
95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107                 sdhci_readl(host, SDHCI_INT_STATUS));
108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109                 sdhci_readl(host, SDHCI_INT_ENABLE),
110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
115                 sdhci_readl(host, SDHCI_CAPABILITIES),
116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
118                 sdhci_readw(host, SDHCI_COMMAND),
119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
122
123         if (host->flags & SDHCI_USE_ADMA) {
124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
129                 else
130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
133         }
134
135         pr_debug(DRIVER_NAME ": ===========================================\n");
136 }
137
138 /*****************************************************************************\
139  *                                                                           *
140  * Low level functions                                                       *
141  *                                                                           *
142 \*****************************************************************************/
143
144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145 {
146         u32 present;
147
148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
150                 return;
151
152         if (enable) {
153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154                                       SDHCI_CARD_PRESENT;
155
156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157                                        SDHCI_INT_CARD_INSERT;
158         } else {
159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
160         }
161
162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
164 }
165
166 static void sdhci_enable_card_detection(struct sdhci_host *host)
167 {
168         sdhci_set_card_detection(host, true);
169 }
170
171 static void sdhci_disable_card_detection(struct sdhci_host *host)
172 {
173         sdhci_set_card_detection(host, false);
174 }
175
176 void sdhci_reset(struct sdhci_host *host, u8 mask)
177 {
178         unsigned long timeout;
179
180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
181
182         if (mask & SDHCI_RESET_ALL) {
183                 host->clock = 0;
184                 /* Reset-all turns off SD Bus Power */
185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186                         sdhci_runtime_pm_bus_off(host);
187         }
188
189         /* Wait max 100 ms */
190         timeout = 100;
191
192         /* hw clears the bit when it's done */
193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
194                 if (timeout == 0) {
195                         pr_err("%s: Reset 0x%x never completed.\n",
196                                 mmc_hostname(host->mmc), (int)mask);
197                         sdhci_dumpregs(host);
198                         return;
199                 }
200                 timeout--;
201                 mdelay(1);
202         }
203 }
204 EXPORT_SYMBOL_GPL(sdhci_reset);
205
206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207 {
208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
209                 if (!sdhci_do_get_cd(host))
210                         return;
211         }
212
213         host->ops->reset(host, mask);
214
215         if (mask & SDHCI_RESET_ALL) {
216                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217                         if (host->ops->enable_dma)
218                                 host->ops->enable_dma(host);
219                 }
220
221                 /* Resetting the controller clears many */
222                 host->preset_enabled = false;
223         }
224 }
225
226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
227
228 static void sdhci_init(struct sdhci_host *host, int soft)
229 {
230         if (soft)
231                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
232         else
233                 sdhci_do_reset(host, SDHCI_RESET_ALL);
234
235         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239                     SDHCI_INT_RESPONSE;
240
241         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
243
244         if (soft) {
245                 /* force clock reconfiguration */
246                 host->clock = 0;
247                 sdhci_set_ios(host->mmc, &host->mmc->ios);
248         }
249 }
250
251 static void sdhci_reinit(struct sdhci_host *host)
252 {
253         sdhci_init(host, 0);
254         sdhci_enable_card_detection(host);
255 }
256
257 static void sdhci_activate_led(struct sdhci_host *host)
258 {
259         u8 ctrl;
260
261         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
262         ctrl |= SDHCI_CTRL_LED;
263         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
264 }
265
266 static void sdhci_deactivate_led(struct sdhci_host *host)
267 {
268         u8 ctrl;
269
270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271         ctrl &= ~SDHCI_CTRL_LED;
272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
273 }
274
275 #ifdef SDHCI_USE_LEDS_CLASS
276 static void sdhci_led_control(struct led_classdev *led,
277         enum led_brightness brightness)
278 {
279         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
280         unsigned long flags;
281
282         spin_lock_irqsave(&host->lock, flags);
283
284         if (host->runtime_suspended)
285                 goto out;
286
287         if (brightness == LED_OFF)
288                 sdhci_deactivate_led(host);
289         else
290                 sdhci_activate_led(host);
291 out:
292         spin_unlock_irqrestore(&host->lock, flags);
293 }
294 #endif
295
296 /*****************************************************************************\
297  *                                                                           *
298  * Core functions                                                            *
299  *                                                                           *
300 \*****************************************************************************/
301
302 static void sdhci_read_block_pio(struct sdhci_host *host)
303 {
304         unsigned long flags;
305         size_t blksize, len, chunk;
306         u32 uninitialized_var(scratch);
307         u8 *buf;
308
309         DBG("PIO reading\n");
310
311         blksize = host->data->blksz;
312         chunk = 0;
313
314         local_irq_save(flags);
315
316         while (blksize) {
317                 BUG_ON(!sg_miter_next(&host->sg_miter));
318
319                 len = min(host->sg_miter.length, blksize);
320
321                 blksize -= len;
322                 host->sg_miter.consumed = len;
323
324                 buf = host->sg_miter.addr;
325
326                 while (len) {
327                         if (chunk == 0) {
328                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
329                                 chunk = 4;
330                         }
331
332                         *buf = scratch & 0xFF;
333
334                         buf++;
335                         scratch >>= 8;
336                         chunk--;
337                         len--;
338                 }
339         }
340
341         sg_miter_stop(&host->sg_miter);
342
343         local_irq_restore(flags);
344 }
345
346 static void sdhci_write_block_pio(struct sdhci_host *host)
347 {
348         unsigned long flags;
349         size_t blksize, len, chunk;
350         u32 scratch;
351         u8 *buf;
352
353         DBG("PIO writing\n");
354
355         blksize = host->data->blksz;
356         chunk = 0;
357         scratch = 0;
358
359         local_irq_save(flags);
360
361         while (blksize) {
362                 BUG_ON(!sg_miter_next(&host->sg_miter));
363
364                 len = min(host->sg_miter.length, blksize);
365
366                 blksize -= len;
367                 host->sg_miter.consumed = len;
368
369                 buf = host->sg_miter.addr;
370
371                 while (len) {
372                         scratch |= (u32)*buf << (chunk * 8);
373
374                         buf++;
375                         chunk++;
376                         len--;
377
378                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
379                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
380                                 chunk = 0;
381                                 scratch = 0;
382                         }
383                 }
384         }
385
386         sg_miter_stop(&host->sg_miter);
387
388         local_irq_restore(flags);
389 }
390
391 static void sdhci_transfer_pio(struct sdhci_host *host)
392 {
393         u32 mask;
394
395         BUG_ON(!host->data);
396
397         if (host->blocks == 0)
398                 return;
399
400         if (host->data->flags & MMC_DATA_READ)
401                 mask = SDHCI_DATA_AVAILABLE;
402         else
403                 mask = SDHCI_SPACE_AVAILABLE;
404
405         /*
406          * Some controllers (JMicron JMB38x) mess up the buffer bits
407          * for transfers < 4 bytes. As long as it is just one block,
408          * we can ignore the bits.
409          */
410         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411                 (host->data->blocks == 1))
412                 mask = ~0;
413
414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
415                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
416                         udelay(100);
417
418                 if (host->data->flags & MMC_DATA_READ)
419                         sdhci_read_block_pio(host);
420                 else
421                         sdhci_write_block_pio(host);
422
423                 host->blocks--;
424                 if (host->blocks == 0)
425                         break;
426         }
427
428         DBG("PIO transfer complete.\n");
429 }
430
431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
432 {
433         local_irq_save(*flags);
434         return kmap_atomic(sg_page(sg)) + sg->offset;
435 }
436
437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
438 {
439         kunmap_atomic(buffer);
440         local_irq_restore(*flags);
441 }
442
443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444                                   dma_addr_t addr, int len, unsigned cmd)
445 {
446         struct sdhci_adma2_64_desc *dma_desc = desc;
447
448         /* 32-bit and 64-bit descriptors have these members in same position */
449         dma_desc->cmd = cpu_to_le16(cmd);
450         dma_desc->len = cpu_to_le16(len);
451         dma_desc->addr_lo = cpu_to_le32((u32)addr);
452
453         if (host->flags & SDHCI_USE_64_BIT_DMA)
454                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
455 }
456
457 static void sdhci_adma_mark_end(void *desc)
458 {
459         struct sdhci_adma2_64_desc *dma_desc = desc;
460
461         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
462         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
463 }
464
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466         struct mmc_data *data)
467 {
468         int direction;
469
470         void *desc;
471         void *align;
472         dma_addr_t addr;
473         dma_addr_t align_addr;
474         int len, offset;
475
476         struct scatterlist *sg;
477         int i;
478         char *buffer;
479         unsigned long flags;
480
481         /*
482          * The spec does not specify endianness of descriptor table.
483          * We currently guess that it is LE.
484          */
485
486         if (data->flags & MMC_DATA_READ)
487                 direction = DMA_FROM_DEVICE;
488         else
489                 direction = DMA_TO_DEVICE;
490
491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
492                 host->align_buffer, host->align_buffer_sz, direction);
493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
494                 goto fail;
495         BUG_ON(host->align_addr & host->align_mask);
496
497         host->sg_count = sdhci_pre_dma_transfer(host, data);
498         if (host->sg_count < 0)
499                 goto unmap_align;
500
501         desc = host->adma_table;
502         align = host->align_buffer;
503
504         align_addr = host->align_addr;
505
506         for_each_sg(data->sg, sg, host->sg_count, i) {
507                 addr = sg_dma_address(sg);
508                 len = sg_dma_len(sg);
509
510                 /*
511                  * The SDHCI specification states that ADMA
512                  * addresses must be 32-bit aligned. If they
513                  * aren't, then we use a bounce buffer for
514                  * the (up to three) bytes that screw up the
515                  * alignment.
516                  */
517                 offset = (host->align_sz - (addr & host->align_mask)) &
518                          host->align_mask;
519                 if (offset) {
520                         if (data->flags & MMC_DATA_WRITE) {
521                                 buffer = sdhci_kmap_atomic(sg, &flags);
522                                 memcpy(align, buffer, offset);
523                                 sdhci_kunmap_atomic(buffer, &flags);
524                         }
525
526                         /* tran, valid */
527                         sdhci_adma_write_desc(host, desc, align_addr, offset,
528                                               ADMA2_TRAN_VALID);
529
530                         BUG_ON(offset > 65536);
531
532                         align += host->align_sz;
533                         align_addr += host->align_sz;
534
535                         desc += host->desc_sz;
536
537                         addr += offset;
538                         len -= offset;
539                 }
540
541                 BUG_ON(len > 65536);
542
543                 if (len) {
544                         /* tran, valid */
545                         sdhci_adma_write_desc(host, desc, addr, len,
546                                               ADMA2_TRAN_VALID);
547                         desc += host->desc_sz;
548                 }
549
550                 /*
551                  * If this triggers then we have a calculation bug
552                  * somewhere. :/
553                  */
554                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
555         }
556
557         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
558                 /*
559                 * Mark the last descriptor as the terminating descriptor
560                 */
561                 if (desc != host->adma_table) {
562                         desc -= host->desc_sz;
563                         sdhci_adma_mark_end(desc);
564                 }
565         } else {
566                 /*
567                 * Add a terminating entry.
568                 */
569
570                 /* nop, end, valid */
571                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
572         }
573
574         /*
575          * Resync align buffer as we might have changed it.
576          */
577         if (data->flags & MMC_DATA_WRITE) {
578                 dma_sync_single_for_device(mmc_dev(host->mmc),
579                         host->align_addr, host->align_buffer_sz, direction);
580         }
581
582         return 0;
583
584 unmap_align:
585         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
586                 host->align_buffer_sz, direction);
587 fail:
588         return -EINVAL;
589 }
590
591 static void sdhci_adma_table_post(struct sdhci_host *host,
592         struct mmc_data *data)
593 {
594         int direction;
595
596         struct scatterlist *sg;
597         int i, size;
598         void *align;
599         char *buffer;
600         unsigned long flags;
601         bool has_unaligned;
602
603         if (data->flags & MMC_DATA_READ)
604                 direction = DMA_FROM_DEVICE;
605         else
606                 direction = DMA_TO_DEVICE;
607
608         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
609                 host->align_buffer_sz, direction);
610
611         /* Do a quick scan of the SG list for any unaligned mappings */
612         has_unaligned = false;
613         for_each_sg(data->sg, sg, host->sg_count, i)
614                 if (sg_dma_address(sg) & host->align_mask) {
615                         has_unaligned = true;
616                         break;
617                 }
618
619         if (has_unaligned && data->flags & MMC_DATA_READ) {
620                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
621                         data->sg_len, direction);
622
623                 align = host->align_buffer;
624
625                 for_each_sg(data->sg, sg, host->sg_count, i) {
626                         if (sg_dma_address(sg) & host->align_mask) {
627                                 size = host->align_sz -
628                                        (sg_dma_address(sg) & host->align_mask);
629
630                                 buffer = sdhci_kmap_atomic(sg, &flags);
631                                 memcpy(buffer, align, size);
632                                 sdhci_kunmap_atomic(buffer, &flags);
633
634                                 align += host->align_sz;
635                         }
636                 }
637         }
638
639         if (data->host_cookie == COOKIE_MAPPED) {
640                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
641                         data->sg_len, direction);
642                 data->host_cookie = COOKIE_UNMAPPED;
643         }
644 }
645
646 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
647 {
648         u8 count;
649         struct mmc_data *data = cmd->data;
650         unsigned target_timeout, current_timeout;
651
652         /*
653          * If the host controller provides us with an incorrect timeout
654          * value, just skip the check and use 0xE.  The hardware may take
655          * longer to time out, but that's much better than having a too-short
656          * timeout value.
657          */
658         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
659                 return 0xE;
660
661         /* Unspecified timeout, assume max */
662         if (!data && !cmd->busy_timeout)
663                 return 0xE;
664
665         /* timeout in us */
666         if (!data)
667                 target_timeout = cmd->busy_timeout * 1000;
668         else {
669                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
670                 if (host->clock && data->timeout_clks) {
671                         unsigned long long val;
672
673                         /*
674                          * data->timeout_clks is in units of clock cycles.
675                          * host->clock is in Hz.  target_timeout is in us.
676                          * Hence, us = 1000000 * cycles / Hz.  Round up.
677                          */
678                         val = 1000000 * data->timeout_clks;
679                         if (do_div(val, host->clock))
680                                 target_timeout++;
681                         target_timeout += val;
682                 }
683         }
684
685         /*
686          * Figure out needed cycles.
687          * We do this in steps in order to fit inside a 32 bit int.
688          * The first step is the minimum timeout, which will have a
689          * minimum resolution of 6 bits:
690          * (1) 2^13*1000 > 2^22,
691          * (2) host->timeout_clk < 2^16
692          *     =>
693          *     (1) / (2) > 2^6
694          */
695         count = 0;
696         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
697         while (current_timeout < target_timeout) {
698                 count++;
699                 current_timeout <<= 1;
700                 if (count >= 0xF)
701                         break;
702         }
703
704         if (count >= 0xF) {
705                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
706                     mmc_hostname(host->mmc), count, cmd->opcode);
707                 count = 0xE;
708         }
709
710         return count;
711 }
712
713 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
714 {
715         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
716         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
717
718         if (host->flags & SDHCI_REQ_USE_DMA)
719                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
720         else
721                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
722
723         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
724         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
725 }
726
727 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
728 {
729         u8 count;
730
731         if (host->ops->set_timeout) {
732                 host->ops->set_timeout(host, cmd);
733         } else {
734                 count = sdhci_calc_timeout(host, cmd);
735                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
736         }
737 }
738
739 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
740 {
741         u8 ctrl;
742         struct mmc_data *data = cmd->data;
743         int ret;
744
745         WARN_ON(host->data);
746
747         if (data || (cmd->flags & MMC_RSP_BUSY))
748                 sdhci_set_timeout(host, cmd);
749
750         if (!data)
751                 return;
752
753         /* Sanity checks */
754         BUG_ON(data->blksz * data->blocks > 524288);
755         BUG_ON(data->blksz > host->mmc->max_blk_size);
756         BUG_ON(data->blocks > 65535);
757
758         host->data = data;
759         host->data_early = 0;
760         host->data->bytes_xfered = 0;
761
762         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
763                 host->flags |= SDHCI_REQ_USE_DMA;
764
765         /*
766          * FIXME: This doesn't account for merging when mapping the
767          * scatterlist.
768          */
769         if (host->flags & SDHCI_REQ_USE_DMA) {
770                 int broken, i;
771                 struct scatterlist *sg;
772
773                 broken = 0;
774                 if (host->flags & SDHCI_USE_ADMA) {
775                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
776                                 broken = 1;
777                 } else {
778                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
779                                 broken = 1;
780                 }
781
782                 if (unlikely(broken)) {
783                         for_each_sg(data->sg, sg, data->sg_len, i) {
784                                 if (sg->length & 0x3) {
785                                         DBG("Reverting to PIO because of "
786                                                 "transfer size (%d)\n",
787                                                 sg->length);
788                                         host->flags &= ~SDHCI_REQ_USE_DMA;
789                                         break;
790                                 }
791                         }
792                 }
793         }
794
795         /*
796          * The assumption here being that alignment is the same after
797          * translation to device address space.
798          */
799         if (host->flags & SDHCI_REQ_USE_DMA) {
800                 int broken, i;
801                 struct scatterlist *sg;
802
803                 broken = 0;
804                 if (host->flags & SDHCI_USE_ADMA) {
805                         /*
806                          * As we use 3 byte chunks to work around
807                          * alignment problems, we need to check this
808                          * quirk.
809                          */
810                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
811                                 broken = 1;
812                 } else {
813                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
814                                 broken = 1;
815                 }
816
817                 if (unlikely(broken)) {
818                         for_each_sg(data->sg, sg, data->sg_len, i) {
819                                 if (sg->offset & 0x3) {
820                                         DBG("Reverting to PIO because of "
821                                                 "bad alignment\n");
822                                         host->flags &= ~SDHCI_REQ_USE_DMA;
823                                         break;
824                                 }
825                         }
826                 }
827         }
828
829         if (host->flags & SDHCI_REQ_USE_DMA) {
830                 if (host->flags & SDHCI_USE_ADMA) {
831                         ret = sdhci_adma_table_pre(host, data);
832                         if (ret) {
833                                 /*
834                                  * This only happens when someone fed
835                                  * us an invalid request.
836                                  */
837                                 WARN_ON(1);
838                                 host->flags &= ~SDHCI_REQ_USE_DMA;
839                         } else {
840                                 sdhci_writel(host, host->adma_addr,
841                                         SDHCI_ADMA_ADDRESS);
842                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
843                                         sdhci_writel(host,
844                                                      (u64)host->adma_addr >> 32,
845                                                      SDHCI_ADMA_ADDRESS_HI);
846                         }
847                 } else {
848                         int sg_cnt;
849
850                         sg_cnt = sdhci_pre_dma_transfer(host, data);
851                         if (sg_cnt <= 0) {
852                                 /*
853                                  * This only happens when someone fed
854                                  * us an invalid request.
855                                  */
856                                 WARN_ON(1);
857                                 host->flags &= ~SDHCI_REQ_USE_DMA;
858                         } else {
859                                 WARN_ON(sg_cnt != 1);
860                                 sdhci_writel(host, sg_dma_address(data->sg),
861                                         SDHCI_DMA_ADDRESS);
862                         }
863                 }
864         }
865
866         /*
867          * Always adjust the DMA selection as some controllers
868          * (e.g. JMicron) can't do PIO properly when the selection
869          * is ADMA.
870          */
871         if (host->version >= SDHCI_SPEC_200) {
872                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
873                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
874                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
875                         (host->flags & SDHCI_USE_ADMA)) {
876                         if (host->flags & SDHCI_USE_64_BIT_DMA)
877                                 ctrl |= SDHCI_CTRL_ADMA64;
878                         else
879                                 ctrl |= SDHCI_CTRL_ADMA32;
880                 } else {
881                         ctrl |= SDHCI_CTRL_SDMA;
882                 }
883                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
884         }
885
886         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
887                 int flags;
888
889                 flags = SG_MITER_ATOMIC;
890                 if (host->data->flags & MMC_DATA_READ)
891                         flags |= SG_MITER_TO_SG;
892                 else
893                         flags |= SG_MITER_FROM_SG;
894                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
895                 host->blocks = data->blocks;
896         }
897
898         sdhci_set_transfer_irqs(host);
899
900         /* Set the DMA boundary value and block size */
901         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
902                 data->blksz), SDHCI_BLOCK_SIZE);
903         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
904 }
905
906 static void sdhci_set_transfer_mode(struct sdhci_host *host,
907         struct mmc_command *cmd)
908 {
909         u16 mode = 0;
910         struct mmc_data *data = cmd->data;
911
912         if (data == NULL) {
913                 if (host->quirks2 &
914                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
915                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
916                 } else {
917                 /* clear Auto CMD settings for no data CMDs */
918                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
919                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
920                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
921                 }
922                 return;
923         }
924
925         WARN_ON(!host->data);
926
927         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
928                 mode = SDHCI_TRNS_BLK_CNT_EN;
929
930         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
931                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
932                 /*
933                  * If we are sending CMD23, CMD12 never gets sent
934                  * on successful completion (so no Auto-CMD12).
935                  */
936                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
937                     (cmd->opcode != SD_IO_RW_EXTENDED))
938                         mode |= SDHCI_TRNS_AUTO_CMD12;
939                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
940                         mode |= SDHCI_TRNS_AUTO_CMD23;
941                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
942                 }
943         }
944
945         if (data->flags & MMC_DATA_READ)
946                 mode |= SDHCI_TRNS_READ;
947         if (host->flags & SDHCI_REQ_USE_DMA)
948                 mode |= SDHCI_TRNS_DMA;
949
950         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
951 }
952
953 static void sdhci_finish_data(struct sdhci_host *host)
954 {
955         struct mmc_data *data;
956
957         BUG_ON(!host->data);
958
959         data = host->data;
960         host->data = NULL;
961
962         if (host->flags & SDHCI_REQ_USE_DMA) {
963                 if (host->flags & SDHCI_USE_ADMA)
964                         sdhci_adma_table_post(host, data);
965                 else {
966                         if (data->host_cookie == COOKIE_MAPPED) {
967                                 dma_unmap_sg(mmc_dev(host->mmc),
968                                         data->sg, data->sg_len,
969                                         (data->flags & MMC_DATA_READ) ?
970                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
971                                 data->host_cookie = COOKIE_UNMAPPED;
972                         }
973                 }
974         }
975
976         /*
977          * The specification states that the block count register must
978          * be updated, but it does not specify at what point in the
979          * data flow. That makes the register entirely useless to read
980          * back so we have to assume that nothing made it to the card
981          * in the event of an error.
982          */
983         if (data->error)
984                 data->bytes_xfered = 0;
985         else
986                 data->bytes_xfered = data->blksz * data->blocks;
987
988         /*
989          * Need to send CMD12 if -
990          * a) open-ended multiblock transfer (no CMD23)
991          * b) error in multiblock transfer
992          */
993         if (data->stop &&
994             (data->error ||
995              !host->mrq->sbc)) {
996
997                 /*
998                  * The controller needs a reset of internal state machines
999                  * upon error conditions.
1000                  */
1001                 if (data->error) {
1002                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1003                         sdhci_do_reset(host, SDHCI_RESET_DATA);
1004                 }
1005
1006                 sdhci_send_command(host, data->stop);
1007         } else
1008                 tasklet_schedule(&host->finish_tasklet);
1009 }
1010
1011 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1012 {
1013         int flags;
1014         u32 mask;
1015         unsigned long timeout;
1016
1017         WARN_ON(host->cmd);
1018
1019         /* Wait max 10 ms */
1020         timeout = 10;
1021
1022         mask = SDHCI_CMD_INHIBIT;
1023         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1024                 mask |= SDHCI_DATA_INHIBIT;
1025
1026         /* We shouldn't wait for data inihibit for stop commands, even
1027            though they might use busy signaling */
1028         if (host->mrq->data && (cmd == host->mrq->data->stop))
1029                 mask &= ~SDHCI_DATA_INHIBIT;
1030
1031         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1032                 if (timeout == 0) {
1033                         pr_err("%s: Controller never released "
1034                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1035                         sdhci_dumpregs(host);
1036                         cmd->error = -EIO;
1037                         tasklet_schedule(&host->finish_tasklet);
1038                         return;
1039                 }
1040                 timeout--;
1041                 mdelay(1);
1042         }
1043
1044         timeout = jiffies;
1045         if (!cmd->data && cmd->busy_timeout > 9000)
1046                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1047         else
1048                 timeout += 10 * HZ;
1049         mod_timer(&host->timer, timeout);
1050
1051         host->cmd = cmd;
1052         host->busy_handle = 0;
1053
1054         sdhci_prepare_data(host, cmd);
1055
1056         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1057
1058         sdhci_set_transfer_mode(host, cmd);
1059
1060         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1061                 pr_err("%s: Unsupported response type!\n",
1062                         mmc_hostname(host->mmc));
1063                 cmd->error = -EINVAL;
1064                 tasklet_schedule(&host->finish_tasklet);
1065                 return;
1066         }
1067
1068         if (!(cmd->flags & MMC_RSP_PRESENT))
1069                 flags = SDHCI_CMD_RESP_NONE;
1070         else if (cmd->flags & MMC_RSP_136)
1071                 flags = SDHCI_CMD_RESP_LONG;
1072         else if (cmd->flags & MMC_RSP_BUSY)
1073                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1074         else
1075                 flags = SDHCI_CMD_RESP_SHORT;
1076
1077         if (cmd->flags & MMC_RSP_CRC)
1078                 flags |= SDHCI_CMD_CRC;
1079         if (cmd->flags & MMC_RSP_OPCODE)
1080                 flags |= SDHCI_CMD_INDEX;
1081
1082         /* CMD19 is special in that the Data Present Select should be set */
1083         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1084             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1085                 flags |= SDHCI_CMD_DATA;
1086
1087         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1088 }
1089 EXPORT_SYMBOL_GPL(sdhci_send_command);
1090
1091 static void sdhci_finish_command(struct sdhci_host *host)
1092 {
1093         int i;
1094
1095         BUG_ON(host->cmd == NULL);
1096
1097         if (host->cmd->flags & MMC_RSP_PRESENT) {
1098                 if (host->cmd->flags & MMC_RSP_136) {
1099                         /* CRC is stripped so we need to do some shifting. */
1100                         for (i = 0;i < 4;i++) {
1101                                 host->cmd->resp[i] = sdhci_readl(host,
1102                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1103                                 if (i != 3)
1104                                         host->cmd->resp[i] |=
1105                                                 sdhci_readb(host,
1106                                                 SDHCI_RESPONSE + (3-i)*4-1);
1107                         }
1108                 } else {
1109                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1110                 }
1111         }
1112
1113         host->cmd->error = 0;
1114
1115         /* Finished CMD23, now send actual command. */
1116         if (host->cmd == host->mrq->sbc) {
1117                 host->cmd = NULL;
1118                 sdhci_send_command(host, host->mrq->cmd);
1119         } else {
1120
1121                 /* Processed actual command. */
1122                 if (host->data && host->data_early)
1123                         sdhci_finish_data(host);
1124
1125                 if (!host->cmd->data)
1126                         tasklet_schedule(&host->finish_tasklet);
1127
1128                 host->cmd = NULL;
1129         }
1130 }
1131
1132 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1133 {
1134         u16 preset = 0;
1135
1136         switch (host->timing) {
1137         case MMC_TIMING_UHS_SDR12:
1138                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1139                 break;
1140         case MMC_TIMING_UHS_SDR25:
1141                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1142                 break;
1143         case MMC_TIMING_UHS_SDR50:
1144                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1145                 break;
1146         case MMC_TIMING_UHS_SDR104:
1147         case MMC_TIMING_MMC_HS200:
1148                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1149                 break;
1150         case MMC_TIMING_UHS_DDR50:
1151         case MMC_TIMING_MMC_DDR52:
1152                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1153                 break;
1154         case MMC_TIMING_MMC_HS400:
1155                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1156                 break;
1157         default:
1158                 pr_warn("%s: Invalid UHS-I mode selected\n",
1159                         mmc_hostname(host->mmc));
1160                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1161                 break;
1162         }
1163         return preset;
1164 }
1165
1166 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1167 {
1168         int div = 0; /* Initialized for compiler warning */
1169         int real_div = div, clk_mul = 1;
1170         u16 clk = 0;
1171         unsigned long timeout;
1172         bool switch_base_clk = false;
1173
1174         host->mmc->actual_clock = 0;
1175
1176         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1177         if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1178                 mdelay(1);
1179
1180         if (clock == 0)
1181                 return;
1182
1183         if (host->version >= SDHCI_SPEC_300) {
1184                 if (host->preset_enabled) {
1185                         u16 pre_val;
1186
1187                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1188                         pre_val = sdhci_get_preset_value(host);
1189                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1190                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1191                         if (host->clk_mul &&
1192                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1193                                 clk = SDHCI_PROG_CLOCK_MODE;
1194                                 real_div = div + 1;
1195                                 clk_mul = host->clk_mul;
1196                         } else {
1197                                 real_div = max_t(int, 1, div << 1);
1198                         }
1199                         goto clock_set;
1200                 }
1201
1202                 /*
1203                  * Check if the Host Controller supports Programmable Clock
1204                  * Mode.
1205                  */
1206                 if (host->clk_mul) {
1207                         for (div = 1; div <= 1024; div++) {
1208                                 if ((host->max_clk * host->clk_mul / div)
1209                                         <= clock)
1210                                         break;
1211                         }
1212                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1213                                 /*
1214                                  * Set Programmable Clock Mode in the Clock
1215                                  * Control register.
1216                                  */
1217                                 clk = SDHCI_PROG_CLOCK_MODE;
1218                                 real_div = div;
1219                                 clk_mul = host->clk_mul;
1220                                 div--;
1221                         } else {
1222                                 /*
1223                                  * Divisor can be too small to reach clock
1224                                  * speed requirement. Then use the base clock.
1225                                  */
1226                                 switch_base_clk = true;
1227                         }
1228                 }
1229
1230                 if (!host->clk_mul || switch_base_clk) {
1231                         /* Version 3.00 divisors must be a multiple of 2. */
1232                         if (host->max_clk <= clock)
1233                                 div = 1;
1234                         else {
1235                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1236                                      div += 2) {
1237                                         if ((host->max_clk / div) <= clock)
1238                                                 break;
1239                                 }
1240                         }
1241                         real_div = div;
1242                         div >>= 1;
1243                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1244                                 && !div && host->max_clk <= 25000000)
1245                                 div = 1;
1246                 }
1247         } else {
1248                 /* Version 2.00 divisors must be a power of 2. */
1249                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1250                         if ((host->max_clk / div) <= clock)
1251                                 break;
1252                 }
1253                 real_div = div;
1254                 div >>= 1;
1255         }
1256
1257 clock_set:
1258         if (real_div)
1259                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1260         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1261         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1262                 << SDHCI_DIVIDER_HI_SHIFT;
1263         clk |= SDHCI_CLOCK_INT_EN;
1264         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1265
1266         /* Wait max 20 ms */
1267         timeout = 20;
1268         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1269                 & SDHCI_CLOCK_INT_STABLE)) {
1270                 if (timeout == 0) {
1271                         pr_err("%s: Internal clock never "
1272                                 "stabilised.\n", mmc_hostname(host->mmc));
1273                         sdhci_dumpregs(host);
1274                         return;
1275                 }
1276                 timeout--;
1277                 mdelay(1);
1278         }
1279
1280         clk |= SDHCI_CLOCK_CARD_EN;
1281         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1282 }
1283 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1284
1285 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1286                             unsigned short vdd)
1287 {
1288         struct mmc_host *mmc = host->mmc;
1289         u8 pwr = 0;
1290
1291         if (!IS_ERR(mmc->supply.vmmc)) {
1292                 spin_unlock_irq(&host->lock);
1293                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1294                 spin_lock_irq(&host->lock);
1295
1296                 if (mode != MMC_POWER_OFF)
1297                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1298                 else
1299                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1300
1301                 return;
1302         }
1303
1304         if (mode != MMC_POWER_OFF) {
1305                 switch (1 << vdd) {
1306                 case MMC_VDD_165_195:
1307                         pwr = SDHCI_POWER_180;
1308                         break;
1309                 case MMC_VDD_29_30:
1310                 case MMC_VDD_30_31:
1311                         pwr = SDHCI_POWER_300;
1312                         break;
1313                 case MMC_VDD_32_33:
1314                 case MMC_VDD_33_34:
1315                         pwr = SDHCI_POWER_330;
1316                         break;
1317                 default:
1318                         BUG();
1319                 }
1320         }
1321
1322         if (host->pwr == pwr)
1323                 return;
1324
1325         host->pwr = pwr;
1326
1327         if (pwr == 0) {
1328                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1329                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1330                         sdhci_runtime_pm_bus_off(host);
1331                 vdd = 0;
1332         } else {
1333                 /*
1334                  * Spec says that we should clear the power reg before setting
1335                  * a new value. Some controllers don't seem to like this though.
1336                  */
1337                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1338                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1339
1340                 /*
1341                  * At least the Marvell CaFe chip gets confused if we set the
1342                  * voltage and set turn on power at the same time, so set the
1343                  * voltage first.
1344                  */
1345                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1346                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1347
1348                 pwr |= SDHCI_POWER_ON;
1349
1350                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1351
1352                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1353                         sdhci_runtime_pm_bus_on(host);
1354
1355                 /*
1356                  * Some controllers need an extra 10ms delay of 10ms before
1357                  * they can apply clock after applying power
1358                  */
1359                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1360                         mdelay(10);
1361         }
1362 }
1363
1364 /*****************************************************************************\
1365  *                                                                           *
1366  * MMC callbacks                                                             *
1367  *                                                                           *
1368 \*****************************************************************************/
1369
1370 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1371 {
1372         struct sdhci_host *host;
1373         int present;
1374         unsigned long flags;
1375
1376         host = mmc_priv(mmc);
1377
1378         sdhci_runtime_pm_get(host);
1379
1380         /* Firstly check card presence */
1381         present = mmc->ops->get_cd(mmc);
1382
1383         spin_lock_irqsave(&host->lock, flags);
1384
1385         WARN_ON(host->mrq != NULL);
1386
1387 #ifndef SDHCI_USE_LEDS_CLASS
1388         sdhci_activate_led(host);
1389 #endif
1390
1391         /*
1392          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1393          * requests if Auto-CMD12 is enabled.
1394          */
1395         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1396                 if (mrq->stop) {
1397                         mrq->data->stop = NULL;
1398                         mrq->stop = NULL;
1399                 }
1400         }
1401
1402         host->mrq = mrq;
1403
1404         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1405                 host->mrq->cmd->error = -ENOMEDIUM;
1406                 tasklet_schedule(&host->finish_tasklet);
1407         } else {
1408                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1409                         sdhci_send_command(host, mrq->sbc);
1410                 else
1411                         sdhci_send_command(host, mrq->cmd);
1412         }
1413
1414         mmiowb();
1415         spin_unlock_irqrestore(&host->lock, flags);
1416 }
1417
1418 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1419 {
1420         u8 ctrl;
1421
1422         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1423         if (width == MMC_BUS_WIDTH_8) {
1424                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1425                 if (host->version >= SDHCI_SPEC_300)
1426                         ctrl |= SDHCI_CTRL_8BITBUS;
1427         } else {
1428                 if (host->version >= SDHCI_SPEC_300)
1429                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1430                 if (width == MMC_BUS_WIDTH_4)
1431                         ctrl |= SDHCI_CTRL_4BITBUS;
1432                 else
1433                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1434         }
1435         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1436 }
1437 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1438
1439 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1440 {
1441         u16 ctrl_2;
1442
1443         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1444         /* Select Bus Speed Mode for host */
1445         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1446         if ((timing == MMC_TIMING_MMC_HS200) ||
1447             (timing == MMC_TIMING_UHS_SDR104))
1448                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1449         else if (timing == MMC_TIMING_UHS_SDR12)
1450                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1451         else if (timing == MMC_TIMING_UHS_SDR25)
1452                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1453         else if (timing == MMC_TIMING_UHS_SDR50)
1454                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1455         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1456                  (timing == MMC_TIMING_MMC_DDR52))
1457                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1458         else if (timing == MMC_TIMING_MMC_HS400)
1459                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1460         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1461 }
1462 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1463
1464 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1465 {
1466         unsigned long flags;
1467         u8 ctrl;
1468         struct mmc_host *mmc = host->mmc;
1469
1470         spin_lock_irqsave(&host->lock, flags);
1471
1472         if (host->flags & SDHCI_DEVICE_DEAD) {
1473                 spin_unlock_irqrestore(&host->lock, flags);
1474                 if (!IS_ERR(mmc->supply.vmmc) &&
1475                     ios->power_mode == MMC_POWER_OFF)
1476                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1477                 return;
1478         }
1479
1480         /*
1481          * Reset the chip on each power off.
1482          * Should clear out any weird states.
1483          */
1484         if (ios->power_mode == MMC_POWER_OFF) {
1485                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1486                 sdhci_reinit(host);
1487         }
1488
1489         if (host->version >= SDHCI_SPEC_300 &&
1490                 (ios->power_mode == MMC_POWER_UP) &&
1491                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1492                 sdhci_enable_preset_value(host, false);
1493
1494         if (!ios->clock || ios->clock != host->clock) {
1495                 host->ops->set_clock(host, ios->clock);
1496                 host->clock = ios->clock;
1497
1498                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1499                     host->clock) {
1500                         host->timeout_clk = host->mmc->actual_clock ?
1501                                                 host->mmc->actual_clock / 1000 :
1502                                                 host->clock / 1000;
1503                         host->mmc->max_busy_timeout =
1504                                 host->ops->get_max_timeout_count ?
1505                                 host->ops->get_max_timeout_count(host) :
1506                                 1 << 27;
1507                         host->mmc->max_busy_timeout /= host->timeout_clk;
1508                 }
1509         }
1510
1511         sdhci_set_power(host, ios->power_mode, ios->vdd);
1512
1513         if (host->ops->platform_send_init_74_clocks)
1514                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1515
1516         host->ops->set_bus_width(host, ios->bus_width);
1517
1518         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1519
1520         if ((ios->timing == MMC_TIMING_SD_HS ||
1521              ios->timing == MMC_TIMING_MMC_HS)
1522             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1523                 ctrl |= SDHCI_CTRL_HISPD;
1524         else
1525                 ctrl &= ~SDHCI_CTRL_HISPD;
1526
1527         if (host->version >= SDHCI_SPEC_300) {
1528                 u16 clk, ctrl_2;
1529
1530                 /* In case of UHS-I modes, set High Speed Enable */
1531                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1532                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1533                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1534                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1535                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1536                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1537                     (ios->timing == MMC_TIMING_UHS_SDR25))
1538                         ctrl |= SDHCI_CTRL_HISPD;
1539
1540                 if (!host->preset_enabled) {
1541                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1542                         /*
1543                          * We only need to set Driver Strength if the
1544                          * preset value enable is not set.
1545                          */
1546                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1547                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1548                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1549                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1550                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1551                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1552                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1553                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1554                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1555                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1556                         else {
1557                                 pr_warn("%s: invalid driver type, default to "
1558                                         "driver type B\n", mmc_hostname(mmc));
1559                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1560                         }
1561
1562                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1563                 } else {
1564                         /*
1565                          * According to SDHC Spec v3.00, if the Preset Value
1566                          * Enable in the Host Control 2 register is set, we
1567                          * need to reset SD Clock Enable before changing High
1568                          * Speed Enable to avoid generating clock gliches.
1569                          */
1570
1571                         /* Reset SD Clock Enable */
1572                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1573                         clk &= ~SDHCI_CLOCK_CARD_EN;
1574                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1575
1576                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1577
1578                         /* Re-enable SD Clock */
1579                         host->ops->set_clock(host, host->clock);
1580                 }
1581
1582                 /* Reset SD Clock Enable */
1583                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1584                 clk &= ~SDHCI_CLOCK_CARD_EN;
1585                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1586
1587                 host->ops->set_uhs_signaling(host, ios->timing);
1588                 host->timing = ios->timing;
1589
1590                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1591                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1592                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1593                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1594                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1595                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1596                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1597                         u16 preset;
1598
1599                         sdhci_enable_preset_value(host, true);
1600                         preset = sdhci_get_preset_value(host);
1601                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1602                                 >> SDHCI_PRESET_DRV_SHIFT;
1603                 }
1604
1605                 /* Re-enable SD Clock */
1606                 host->ops->set_clock(host, host->clock);
1607         } else
1608                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1609
1610         /*
1611          * Some (ENE) controllers go apeshit on some ios operation,
1612          * signalling timeout and CRC errors even on CMD0. Resetting
1613          * it on each ios seems to solve the problem.
1614          */
1615         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1616                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1617
1618         mmiowb();
1619         spin_unlock_irqrestore(&host->lock, flags);
1620 }
1621
1622 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1623 {
1624         struct sdhci_host *host = mmc_priv(mmc);
1625
1626         sdhci_runtime_pm_get(host);
1627         sdhci_do_set_ios(host, ios);
1628         sdhci_runtime_pm_put(host);
1629 }
1630
1631 static int sdhci_do_get_cd(struct sdhci_host *host)
1632 {
1633         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1634
1635         if (host->flags & SDHCI_DEVICE_DEAD)
1636                 return 0;
1637
1638         /* If nonremovable, assume that the card is always present. */
1639         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1640                 return 1;
1641
1642         /*
1643          * Try slot gpio detect, if defined it take precedence
1644          * over build in controller functionality
1645          */
1646         if (!IS_ERR_VALUE(gpio_cd))
1647                 return !!gpio_cd;
1648
1649         /* If polling, assume that the card is always present. */
1650         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1651                 return 1;
1652
1653         /* Host native card detect */
1654         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1655 }
1656
1657 static int sdhci_get_cd(struct mmc_host *mmc)
1658 {
1659         struct sdhci_host *host = mmc_priv(mmc);
1660         int ret;
1661
1662         sdhci_runtime_pm_get(host);
1663         ret = sdhci_do_get_cd(host);
1664         sdhci_runtime_pm_put(host);
1665         return ret;
1666 }
1667
1668 static int sdhci_check_ro(struct sdhci_host *host)
1669 {
1670         unsigned long flags;
1671         int is_readonly;
1672
1673         spin_lock_irqsave(&host->lock, flags);
1674
1675         if (host->flags & SDHCI_DEVICE_DEAD)
1676                 is_readonly = 0;
1677         else if (host->ops->get_ro)
1678                 is_readonly = host->ops->get_ro(host);
1679         else
1680                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1681                                 & SDHCI_WRITE_PROTECT);
1682
1683         spin_unlock_irqrestore(&host->lock, flags);
1684
1685         /* This quirk needs to be replaced by a callback-function later */
1686         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1687                 !is_readonly : is_readonly;
1688 }
1689
1690 #define SAMPLE_COUNT    5
1691
1692 static int sdhci_do_get_ro(struct sdhci_host *host)
1693 {
1694         int i, ro_count;
1695
1696         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1697                 return sdhci_check_ro(host);
1698
1699         ro_count = 0;
1700         for (i = 0; i < SAMPLE_COUNT; i++) {
1701                 if (sdhci_check_ro(host)) {
1702                         if (++ro_count > SAMPLE_COUNT / 2)
1703                                 return 1;
1704                 }
1705                 msleep(30);
1706         }
1707         return 0;
1708 }
1709
1710 static void sdhci_hw_reset(struct mmc_host *mmc)
1711 {
1712         struct sdhci_host *host = mmc_priv(mmc);
1713
1714         if (host->ops && host->ops->hw_reset)
1715                 host->ops->hw_reset(host);
1716 }
1717
1718 static int sdhci_get_ro(struct mmc_host *mmc)
1719 {
1720         struct sdhci_host *host = mmc_priv(mmc);
1721         int ret;
1722
1723         sdhci_runtime_pm_get(host);
1724         ret = sdhci_do_get_ro(host);
1725         sdhci_runtime_pm_put(host);
1726         return ret;
1727 }
1728
1729 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1730 {
1731         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1732                 if (enable)
1733                         host->ier |= SDHCI_INT_CARD_INT;
1734                 else
1735                         host->ier &= ~SDHCI_INT_CARD_INT;
1736
1737                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1738                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1739                 mmiowb();
1740         }
1741 }
1742
1743 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1744 {
1745         struct sdhci_host *host = mmc_priv(mmc);
1746         unsigned long flags;
1747
1748         sdhci_runtime_pm_get(host);
1749
1750         spin_lock_irqsave(&host->lock, flags);
1751         if (enable)
1752                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1753         else
1754                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1755
1756         sdhci_enable_sdio_irq_nolock(host, enable);
1757         spin_unlock_irqrestore(&host->lock, flags);
1758
1759         sdhci_runtime_pm_put(host);
1760 }
1761
1762 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1763                                                 struct mmc_ios *ios)
1764 {
1765         struct mmc_host *mmc = host->mmc;
1766         u16 ctrl;
1767         int ret;
1768
1769         /*
1770          * Signal Voltage Switching is only applicable for Host Controllers
1771          * v3.00 and above.
1772          */
1773         if (host->version < SDHCI_SPEC_300)
1774                 return 0;
1775
1776         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1777
1778         switch (ios->signal_voltage) {
1779         case MMC_SIGNAL_VOLTAGE_330:
1780                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1781                 ctrl &= ~SDHCI_CTRL_VDD_180;
1782                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1783
1784                 if (!IS_ERR(mmc->supply.vqmmc)) {
1785                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1786                                                     3600000);
1787                         if (ret) {
1788                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1789                                         mmc_hostname(mmc));
1790                                 return -EIO;
1791                         }
1792                 }
1793                 /* Wait for 5ms */
1794                 usleep_range(5000, 5500);
1795
1796                 /* 3.3V regulator output should be stable within 5 ms */
1797                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1798                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1799                         return 0;
1800
1801                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1802                         mmc_hostname(mmc));
1803
1804                 return -EAGAIN;
1805         case MMC_SIGNAL_VOLTAGE_180:
1806                 if (!IS_ERR(mmc->supply.vqmmc)) {
1807                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1808                                         1700000, 1950000);
1809                         if (ret) {
1810                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1811                                         mmc_hostname(mmc));
1812                                 return -EIO;
1813                         }
1814                 }
1815
1816                 /*
1817                  * Enable 1.8V Signal Enable in the Host Control2
1818                  * register
1819                  */
1820                 ctrl |= SDHCI_CTRL_VDD_180;
1821                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1822
1823                 /* Some controller need to do more when switching */
1824                 if (host->ops->voltage_switch)
1825                         host->ops->voltage_switch(host);
1826
1827                 /* 1.8V regulator output should be stable within 5 ms */
1828                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1829                 if (ctrl & SDHCI_CTRL_VDD_180)
1830                         return 0;
1831
1832                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1833                         mmc_hostname(mmc));
1834
1835                 return -EAGAIN;
1836         case MMC_SIGNAL_VOLTAGE_120:
1837                 if (!IS_ERR(mmc->supply.vqmmc)) {
1838                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1839                                                     1300000);
1840                         if (ret) {
1841                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1842                                         mmc_hostname(mmc));
1843                                 return -EIO;
1844                         }
1845                 }
1846                 return 0;
1847         default:
1848                 /* No signal voltage switch required */
1849                 return 0;
1850         }
1851 }
1852
1853 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1854         struct mmc_ios *ios)
1855 {
1856         struct sdhci_host *host = mmc_priv(mmc);
1857         int err;
1858
1859         if (host->version < SDHCI_SPEC_300)
1860                 return 0;
1861         sdhci_runtime_pm_get(host);
1862         err = sdhci_do_start_signal_voltage_switch(host, ios);
1863         sdhci_runtime_pm_put(host);
1864         return err;
1865 }
1866
1867 static int sdhci_card_busy(struct mmc_host *mmc)
1868 {
1869         struct sdhci_host *host = mmc_priv(mmc);
1870         u32 present_state;
1871
1872         sdhci_runtime_pm_get(host);
1873         /* Check whether DAT[0] is 0 */
1874         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1875         sdhci_runtime_pm_put(host);
1876
1877         return !(present_state & SDHCI_DATA_0_LVL_MASK);
1878 }
1879
1880 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1881 {
1882         struct sdhci_host *host = mmc_priv(mmc);
1883         unsigned long flags;
1884
1885         spin_lock_irqsave(&host->lock, flags);
1886         host->flags |= SDHCI_HS400_TUNING;
1887         spin_unlock_irqrestore(&host->lock, flags);
1888
1889         return 0;
1890 }
1891
1892 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1893 {
1894         struct sdhci_host *host = mmc_priv(mmc);
1895         u16 ctrl;
1896         int tuning_loop_counter = MAX_TUNING_LOOP;
1897         int err = 0;
1898         unsigned long flags;
1899         unsigned int tuning_count = 0;
1900         bool hs400_tuning;
1901
1902         sdhci_runtime_pm_get(host);
1903         spin_lock_irqsave(&host->lock, flags);
1904
1905         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1906         host->flags &= ~SDHCI_HS400_TUNING;
1907
1908         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1909                 tuning_count = host->tuning_count;
1910
1911         /*
1912          * The Host Controller needs tuning in case of SDR104 and DDR50
1913          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1914          * the Capabilities register.
1915          * If the Host Controller supports the HS200 mode then the
1916          * tuning function has to be executed.
1917          */
1918         switch (host->timing) {
1919         /* HS400 tuning is done in HS200 mode */
1920         case MMC_TIMING_MMC_HS400:
1921                 err = -EINVAL;
1922                 goto out_unlock;
1923
1924         case MMC_TIMING_MMC_HS200:
1925                 /*
1926                  * Periodic re-tuning for HS400 is not expected to be needed, so
1927                  * disable it here.
1928                  */
1929                 if (hs400_tuning)
1930                         tuning_count = 0;
1931                 break;
1932
1933         case MMC_TIMING_UHS_SDR104:
1934         case MMC_TIMING_UHS_DDR50:
1935                 break;
1936
1937         case MMC_TIMING_UHS_SDR50:
1938                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1939                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1940                         break;
1941                 /* FALLTHROUGH */
1942
1943         default:
1944                 goto out_unlock;
1945         }
1946
1947         if (host->ops->platform_execute_tuning) {
1948                 spin_unlock_irqrestore(&host->lock, flags);
1949                 err = host->ops->platform_execute_tuning(host, opcode);
1950                 sdhci_runtime_pm_put(host);
1951                 return err;
1952         }
1953
1954         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1955         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1956         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1957                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1958         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1959
1960         /*
1961          * As per the Host Controller spec v3.00, tuning command
1962          * generates Buffer Read Ready interrupt, so enable that.
1963          *
1964          * Note: The spec clearly says that when tuning sequence
1965          * is being performed, the controller does not generate
1966          * interrupts other than Buffer Read Ready interrupt. But
1967          * to make sure we don't hit a controller bug, we _only_
1968          * enable Buffer Read Ready interrupt here.
1969          */
1970         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1971         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1972
1973         /*
1974          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1975          * of loops reaches 40 times or a timeout of 150ms occurs.
1976          */
1977         do {
1978                 struct mmc_command cmd = {0};
1979                 struct mmc_request mrq = {NULL};
1980
1981                 cmd.opcode = opcode;
1982                 cmd.arg = 0;
1983                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1984                 cmd.retries = 0;
1985                 cmd.data = NULL;
1986                 cmd.error = 0;
1987
1988                 if (tuning_loop_counter-- == 0)
1989                         break;
1990
1991                 mrq.cmd = &cmd;
1992                 host->mrq = &mrq;
1993
1994                 /*
1995                  * In response to CMD19, the card sends 64 bytes of tuning
1996                  * block to the Host Controller. So we set the block size
1997                  * to 64 here.
1998                  */
1999                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2000                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2001                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2002                                              SDHCI_BLOCK_SIZE);
2003                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2004                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2005                                              SDHCI_BLOCK_SIZE);
2006                 } else {
2007                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2008                                      SDHCI_BLOCK_SIZE);
2009                 }
2010
2011                 /*
2012                  * The tuning block is sent by the card to the host controller.
2013                  * So we set the TRNS_READ bit in the Transfer Mode register.
2014                  * This also takes care of setting DMA Enable and Multi Block
2015                  * Select in the same register to 0.
2016                  */
2017                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2018
2019                 sdhci_send_command(host, &cmd);
2020
2021                 host->cmd = NULL;
2022                 host->mrq = NULL;
2023
2024                 spin_unlock_irqrestore(&host->lock, flags);
2025                 /* Wait for Buffer Read Ready interrupt */
2026                 wait_event_interruptible_timeout(host->buf_ready_int,
2027                                         (host->tuning_done == 1),
2028                                         msecs_to_jiffies(50));
2029                 spin_lock_irqsave(&host->lock, flags);
2030
2031                 if (!host->tuning_done) {
2032                         pr_info(DRIVER_NAME ": Timeout waiting for "
2033                                 "Buffer Read Ready interrupt during tuning "
2034                                 "procedure, falling back to fixed sampling "
2035                                 "clock\n");
2036                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2037                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2038                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2039                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2040
2041                         err = -EIO;
2042                         goto out;
2043                 }
2044
2045                 host->tuning_done = 0;
2046
2047                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2048
2049                 /* eMMC spec does not require a delay between tuning cycles */
2050                 if (opcode == MMC_SEND_TUNING_BLOCK)
2051                         mdelay(1);
2052         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2053
2054         /*
2055          * The Host Driver has exhausted the maximum number of loops allowed,
2056          * so use fixed sampling frequency.
2057          */
2058         if (tuning_loop_counter < 0) {
2059                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2060                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2061         }
2062         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2063                 pr_info(DRIVER_NAME ": Tuning procedure"
2064                         " failed, falling back to fixed sampling"
2065                         " clock\n");
2066                 err = -EIO;
2067         }
2068
2069 out:
2070         if (tuning_count) {
2071                 /*
2072                  * In case tuning fails, host controllers which support
2073                  * re-tuning can try tuning again at a later time, when the
2074                  * re-tuning timer expires.  So for these controllers, we
2075                  * return 0. Since there might be other controllers who do not
2076                  * have this capability, we return error for them.
2077                  */
2078                 err = 0;
2079         }
2080
2081         host->mmc->retune_period = err ? 0 : tuning_count;
2082
2083         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2084         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2085 out_unlock:
2086         spin_unlock_irqrestore(&host->lock, flags);
2087         sdhci_runtime_pm_put(host);
2088
2089         return err;
2090 }
2091
2092 static int sdhci_select_drive_strength(struct mmc_card *card,
2093                                        unsigned int max_dtr, int host_drv,
2094                                        int card_drv, int *drv_type)
2095 {
2096         struct sdhci_host *host = mmc_priv(card->host);
2097
2098         if (!host->ops->select_drive_strength)
2099                 return 0;
2100
2101         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2102                                                 card_drv, drv_type);
2103 }
2104
2105 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2106 {
2107         /* Host Controller v3.00 defines preset value registers */
2108         if (host->version < SDHCI_SPEC_300)
2109                 return;
2110
2111         /*
2112          * We only enable or disable Preset Value if they are not already
2113          * enabled or disabled respectively. Otherwise, we bail out.
2114          */
2115         if (host->preset_enabled != enable) {
2116                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2117
2118                 if (enable)
2119                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2120                 else
2121                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2122
2123                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2124
2125                 if (enable)
2126                         host->flags |= SDHCI_PV_ENABLED;
2127                 else
2128                         host->flags &= ~SDHCI_PV_ENABLED;
2129
2130                 host->preset_enabled = enable;
2131         }
2132 }
2133
2134 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2135                                 int err)
2136 {
2137         struct sdhci_host *host = mmc_priv(mmc);
2138         struct mmc_data *data = mrq->data;
2139
2140         if (host->flags & SDHCI_REQ_USE_DMA) {
2141                 if (data->host_cookie == COOKIE_GIVEN ||
2142                                 data->host_cookie == COOKIE_MAPPED)
2143                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2144                                          data->flags & MMC_DATA_WRITE ?
2145                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2146                 data->host_cookie = COOKIE_UNMAPPED;
2147         }
2148 }
2149
2150 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2151                                        struct mmc_data *data)
2152 {
2153         int sg_count;
2154
2155         if (data->host_cookie == COOKIE_MAPPED) {
2156                 data->host_cookie = COOKIE_GIVEN;
2157                 return data->sg_count;
2158         }
2159
2160         WARN_ON(data->host_cookie == COOKIE_GIVEN);
2161
2162         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2163                                 data->flags & MMC_DATA_WRITE ?
2164                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2165
2166         if (sg_count == 0)
2167                 return -ENOSPC;
2168
2169         data->sg_count = sg_count;
2170         data->host_cookie = COOKIE_MAPPED;
2171
2172         return sg_count;
2173 }
2174
2175 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2176                                bool is_first_req)
2177 {
2178         struct sdhci_host *host = mmc_priv(mmc);
2179
2180         mrq->data->host_cookie = COOKIE_UNMAPPED;
2181
2182         if (host->flags & SDHCI_REQ_USE_DMA)
2183                 sdhci_pre_dma_transfer(host, mrq->data);
2184 }
2185
2186 static void sdhci_card_event(struct mmc_host *mmc)
2187 {
2188         struct sdhci_host *host = mmc_priv(mmc);
2189         unsigned long flags;
2190         int present;
2191
2192         /* First check if client has provided their own card event */
2193         if (host->ops->card_event)
2194                 host->ops->card_event(host);
2195
2196         present = sdhci_do_get_cd(host);
2197
2198         spin_lock_irqsave(&host->lock, flags);
2199
2200         /* Check host->mrq first in case we are runtime suspended */
2201         if (host->mrq && !present) {
2202                 pr_err("%s: Card removed during transfer!\n",
2203                         mmc_hostname(host->mmc));
2204                 pr_err("%s: Resetting controller.\n",
2205                         mmc_hostname(host->mmc));
2206
2207                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2208                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2209
2210                 host->mrq->cmd->error = -ENOMEDIUM;
2211                 tasklet_schedule(&host->finish_tasklet);
2212         }
2213
2214         spin_unlock_irqrestore(&host->lock, flags);
2215 }
2216
2217 static const struct mmc_host_ops sdhci_ops = {
2218         .request        = sdhci_request,
2219         .post_req       = sdhci_post_req,
2220         .pre_req        = sdhci_pre_req,
2221         .set_ios        = sdhci_set_ios,
2222         .get_cd         = sdhci_get_cd,
2223         .get_ro         = sdhci_get_ro,
2224         .hw_reset       = sdhci_hw_reset,
2225         .enable_sdio_irq = sdhci_enable_sdio_irq,
2226         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2227         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2228         .execute_tuning                 = sdhci_execute_tuning,
2229         .select_drive_strength          = sdhci_select_drive_strength,
2230         .card_event                     = sdhci_card_event,
2231         .card_busy      = sdhci_card_busy,
2232 };
2233
2234 /*****************************************************************************\
2235  *                                                                           *
2236  * Tasklets                                                                  *
2237  *                                                                           *
2238 \*****************************************************************************/
2239
2240 static void sdhci_tasklet_finish(unsigned long param)
2241 {
2242         struct sdhci_host *host;
2243         unsigned long flags;
2244         struct mmc_request *mrq;
2245
2246         host = (struct sdhci_host*)param;
2247
2248         spin_lock_irqsave(&host->lock, flags);
2249
2250         /*
2251          * If this tasklet gets rescheduled while running, it will
2252          * be run again afterwards but without any active request.
2253          */
2254         if (!host->mrq) {
2255                 spin_unlock_irqrestore(&host->lock, flags);
2256                 return;
2257         }
2258
2259         del_timer(&host->timer);
2260
2261         mrq = host->mrq;
2262
2263         /*
2264          * The controller needs a reset of internal state machines
2265          * upon error conditions.
2266          */
2267         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2268             ((mrq->cmd && mrq->cmd->error) ||
2269              (mrq->sbc && mrq->sbc->error) ||
2270              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2271                             (mrq->data->stop && mrq->data->stop->error))) ||
2272              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2273
2274                 /* Some controllers need this kick or reset won't work here */
2275                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2276                         /* This is to force an update */
2277                         host->ops->set_clock(host, host->clock);
2278
2279                 /* Spec says we should do both at the same time, but Ricoh
2280                    controllers do not like that. */
2281                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2282                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2283         }
2284
2285         host->mrq = NULL;
2286         host->cmd = NULL;
2287         host->data = NULL;
2288
2289 #ifndef SDHCI_USE_LEDS_CLASS
2290         sdhci_deactivate_led(host);
2291 #endif
2292
2293         mmiowb();
2294         spin_unlock_irqrestore(&host->lock, flags);
2295
2296         mmc_request_done(host->mmc, mrq);
2297         sdhci_runtime_pm_put(host);
2298 }
2299
2300 static void sdhci_timeout_timer(unsigned long data)
2301 {
2302         struct sdhci_host *host;
2303         unsigned long flags;
2304
2305         host = (struct sdhci_host*)data;
2306
2307         spin_lock_irqsave(&host->lock, flags);
2308
2309         if (host->mrq) {
2310                 pr_err("%s: Timeout waiting for hardware "
2311                         "interrupt.\n", mmc_hostname(host->mmc));
2312                 sdhci_dumpregs(host);
2313
2314                 if (host->data) {
2315                         host->data->error = -ETIMEDOUT;
2316                         sdhci_finish_data(host);
2317                 } else {
2318                         if (host->cmd)
2319                                 host->cmd->error = -ETIMEDOUT;
2320                         else
2321                                 host->mrq->cmd->error = -ETIMEDOUT;
2322
2323                         tasklet_schedule(&host->finish_tasklet);
2324                 }
2325         }
2326
2327         mmiowb();
2328         spin_unlock_irqrestore(&host->lock, flags);
2329 }
2330
2331 /*****************************************************************************\
2332  *                                                                           *
2333  * Interrupt handling                                                        *
2334  *                                                                           *
2335 \*****************************************************************************/
2336
2337 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2338 {
2339         BUG_ON(intmask == 0);
2340
2341         if (!host->cmd) {
2342                 pr_err("%s: Got command interrupt 0x%08x even "
2343                         "though no command operation was in progress.\n",
2344                         mmc_hostname(host->mmc), (unsigned)intmask);
2345                 sdhci_dumpregs(host);
2346                 return;
2347         }
2348
2349         if (intmask & SDHCI_INT_TIMEOUT)
2350                 host->cmd->error = -ETIMEDOUT;
2351         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2352                         SDHCI_INT_INDEX))
2353                 host->cmd->error = -EILSEQ;
2354
2355         if (host->cmd->error) {
2356                 tasklet_schedule(&host->finish_tasklet);
2357                 return;
2358         }
2359
2360         /*
2361          * The host can send and interrupt when the busy state has
2362          * ended, allowing us to wait without wasting CPU cycles.
2363          * Unfortunately this is overloaded on the "data complete"
2364          * interrupt, so we need to take some care when handling
2365          * it.
2366          *
2367          * Note: The 1.0 specification is a bit ambiguous about this
2368          *       feature so there might be some problems with older
2369          *       controllers.
2370          */
2371         if (host->cmd->flags & MMC_RSP_BUSY) {
2372                 if (host->cmd->data)
2373                         DBG("Cannot wait for busy signal when also "
2374                                 "doing a data transfer");
2375                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2376                                 && !host->busy_handle) {
2377                         /* Mark that command complete before busy is ended */
2378                         host->busy_handle = 1;
2379                         return;
2380                 }
2381
2382                 /* The controller does not support the end-of-busy IRQ,
2383                  * fall through and take the SDHCI_INT_RESPONSE */
2384         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2385                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2386                 *mask &= ~SDHCI_INT_DATA_END;
2387         }
2388
2389         if (intmask & SDHCI_INT_RESPONSE)
2390                 sdhci_finish_command(host);
2391 }
2392
2393 #ifdef CONFIG_MMC_DEBUG
2394 static void sdhci_adma_show_error(struct sdhci_host *host)
2395 {
2396         const char *name = mmc_hostname(host->mmc);
2397         void *desc = host->adma_table;
2398
2399         sdhci_dumpregs(host);
2400
2401         while (true) {
2402                 struct sdhci_adma2_64_desc *dma_desc = desc;
2403
2404                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2405                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2406                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2407                             le32_to_cpu(dma_desc->addr_lo),
2408                             le16_to_cpu(dma_desc->len),
2409                             le16_to_cpu(dma_desc->cmd));
2410                 else
2411                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2412                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2413                             le16_to_cpu(dma_desc->len),
2414                             le16_to_cpu(dma_desc->cmd));
2415
2416                 desc += host->desc_sz;
2417
2418                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2419                         break;
2420         }
2421 }
2422 #else
2423 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2424 #endif
2425
2426 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2427 {
2428         u32 command;
2429         BUG_ON(intmask == 0);
2430
2431         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2432         if (intmask & SDHCI_INT_DATA_AVAIL) {
2433                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2434                 if (command == MMC_SEND_TUNING_BLOCK ||
2435                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2436                         host->tuning_done = 1;
2437                         wake_up(&host->buf_ready_int);
2438                         return;
2439                 }
2440         }
2441
2442         if (!host->data) {
2443                 /*
2444                  * The "data complete" interrupt is also used to
2445                  * indicate that a busy state has ended. See comment
2446                  * above in sdhci_cmd_irq().
2447                  */
2448                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2449                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2450                                 host->cmd->error = -ETIMEDOUT;
2451                                 tasklet_schedule(&host->finish_tasklet);
2452                                 return;
2453                         }
2454                         if (intmask & SDHCI_INT_DATA_END) {
2455                                 /*
2456                                  * Some cards handle busy-end interrupt
2457                                  * before the command completed, so make
2458                                  * sure we do things in the proper order.
2459                                  */
2460                                 if (host->busy_handle)
2461                                         sdhci_finish_command(host);
2462                                 else
2463                                         host->busy_handle = 1;
2464                                 return;
2465                         }
2466                 }
2467
2468                 pr_err("%s: Got data interrupt 0x%08x even "
2469                         "though no data operation was in progress.\n",
2470                         mmc_hostname(host->mmc), (unsigned)intmask);
2471                 sdhci_dumpregs(host);
2472
2473                 return;
2474         }
2475
2476         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2477                 host->data->error = -ETIMEDOUT;
2478         else if (intmask & SDHCI_INT_DATA_END_BIT)
2479                 host->data->error = -EILSEQ;
2480         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2481                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2482                         != MMC_BUS_TEST_R)
2483                 host->data->error = -EILSEQ;
2484         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2485                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2486                 sdhci_adma_show_error(host);
2487                 host->data->error = -EIO;
2488                 if (host->ops->adma_workaround)
2489                         host->ops->adma_workaround(host, intmask);
2490         }
2491
2492         if (host->data->error)
2493                 sdhci_finish_data(host);
2494         else {
2495                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2496                         sdhci_transfer_pio(host);
2497
2498                 /*
2499                  * We currently don't do anything fancy with DMA
2500                  * boundaries, but as we can't disable the feature
2501                  * we need to at least restart the transfer.
2502                  *
2503                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2504                  * should return a valid address to continue from, but as
2505                  * some controllers are faulty, don't trust them.
2506                  */
2507                 if (intmask & SDHCI_INT_DMA_END) {
2508                         u32 dmastart, dmanow;
2509                         dmastart = sg_dma_address(host->data->sg);
2510                         dmanow = dmastart + host->data->bytes_xfered;
2511                         /*
2512                          * Force update to the next DMA block boundary.
2513                          */
2514                         dmanow = (dmanow &
2515                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2516                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2517                         host->data->bytes_xfered = dmanow - dmastart;
2518                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2519                                 " next 0x%08x\n",
2520                                 mmc_hostname(host->mmc), dmastart,
2521                                 host->data->bytes_xfered, dmanow);
2522                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2523                 }
2524
2525                 if (intmask & SDHCI_INT_DATA_END) {
2526                         if (host->cmd) {
2527                                 /*
2528                                  * Data managed to finish before the
2529                                  * command completed. Make sure we do
2530                                  * things in the proper order.
2531                                  */
2532                                 host->data_early = 1;
2533                         } else {
2534                                 sdhci_finish_data(host);
2535                         }
2536                 }
2537         }
2538 }
2539
2540 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2541 {
2542         irqreturn_t result = IRQ_NONE;
2543         struct sdhci_host *host = dev_id;
2544         u32 intmask, mask, unexpected = 0;
2545         int max_loops = 16;
2546
2547         spin_lock(&host->lock);
2548
2549         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2550                 spin_unlock(&host->lock);
2551                 return IRQ_NONE;
2552         }
2553
2554         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2555         if (!intmask || intmask == 0xffffffff) {
2556                 result = IRQ_NONE;
2557                 goto out;
2558         }
2559
2560         do {
2561                 /* Clear selected interrupts. */
2562                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2563                                   SDHCI_INT_BUS_POWER);
2564                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2565
2566                 DBG("*** %s got interrupt: 0x%08x\n",
2567                         mmc_hostname(host->mmc), intmask);
2568
2569                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2570                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2571                                       SDHCI_CARD_PRESENT;
2572
2573                         /*
2574                          * There is a observation on i.mx esdhc.  INSERT
2575                          * bit will be immediately set again when it gets
2576                          * cleared, if a card is inserted.  We have to mask
2577                          * the irq to prevent interrupt storm which will
2578                          * freeze the system.  And the REMOVE gets the
2579                          * same situation.
2580                          *
2581                          * More testing are needed here to ensure it works
2582                          * for other platforms though.
2583                          */
2584                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2585                                        SDHCI_INT_CARD_REMOVE);
2586                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2587                                                SDHCI_INT_CARD_INSERT;
2588                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2589                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2590
2591                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2592                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2593
2594                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2595                                                        SDHCI_INT_CARD_REMOVE);
2596                         result = IRQ_WAKE_THREAD;
2597                 }
2598
2599                 if (intmask & SDHCI_INT_CMD_MASK)
2600                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2601                                       &intmask);
2602
2603                 if (intmask & SDHCI_INT_DATA_MASK)
2604                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2605
2606                 if (intmask & SDHCI_INT_BUS_POWER)
2607                         pr_err("%s: Card is consuming too much power!\n",
2608                                 mmc_hostname(host->mmc));
2609
2610                 if (intmask & SDHCI_INT_CARD_INT) {
2611                         sdhci_enable_sdio_irq_nolock(host, false);
2612                         host->thread_isr |= SDHCI_INT_CARD_INT;
2613                         result = IRQ_WAKE_THREAD;
2614                 }
2615
2616                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2617                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2618                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2619                              SDHCI_INT_CARD_INT);
2620
2621                 if (intmask) {
2622                         unexpected |= intmask;
2623                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2624                 }
2625
2626                 if (result == IRQ_NONE)
2627                         result = IRQ_HANDLED;
2628
2629                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2630         } while (intmask && --max_loops);
2631 out:
2632         spin_unlock(&host->lock);
2633
2634         if (unexpected) {
2635                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2636                            mmc_hostname(host->mmc), unexpected);
2637                 sdhci_dumpregs(host);
2638         }
2639
2640         return result;
2641 }
2642
2643 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2644 {
2645         struct sdhci_host *host = dev_id;
2646         unsigned long flags;
2647         u32 isr;
2648
2649         spin_lock_irqsave(&host->lock, flags);
2650         isr = host->thread_isr;
2651         host->thread_isr = 0;
2652         spin_unlock_irqrestore(&host->lock, flags);
2653
2654         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2655                 sdhci_card_event(host->mmc);
2656                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2657         }
2658
2659         if (isr & SDHCI_INT_CARD_INT) {
2660                 sdio_run_irqs(host->mmc);
2661
2662                 spin_lock_irqsave(&host->lock, flags);
2663                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2664                         sdhci_enable_sdio_irq_nolock(host, true);
2665                 spin_unlock_irqrestore(&host->lock, flags);
2666         }
2667
2668         return isr ? IRQ_HANDLED : IRQ_NONE;
2669 }
2670
2671 /*****************************************************************************\
2672  *                                                                           *
2673  * Suspend/resume                                                            *
2674  *                                                                           *
2675 \*****************************************************************************/
2676
2677 #ifdef CONFIG_PM
2678 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2679 {
2680         u8 val;
2681         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2682                         | SDHCI_WAKE_ON_INT;
2683
2684         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2685         val |= mask ;
2686         /* Avoid fake wake up */
2687         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2688                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2689         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2690 }
2691 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2692
2693 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2694 {
2695         u8 val;
2696         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2697                         | SDHCI_WAKE_ON_INT;
2698
2699         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2700         val &= ~mask;
2701         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2702 }
2703
2704 int sdhci_suspend_host(struct sdhci_host *host)
2705 {
2706         sdhci_disable_card_detection(host);
2707
2708         mmc_retune_timer_stop(host->mmc);
2709         mmc_retune_needed(host->mmc);
2710
2711         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2712                 host->ier = 0;
2713                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2714                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2715                 free_irq(host->irq, host);
2716         } else {
2717                 sdhci_enable_irq_wakeups(host);
2718         }
2719         return 0;
2720 }
2721
2722 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2723
2724 int sdhci_resume_host(struct sdhci_host *host)
2725 {
2726         int ret = 0;
2727
2728         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2729                 if (host->ops->enable_dma)
2730                         host->ops->enable_dma(host);
2731         }
2732
2733         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2734             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2735                 /* Card keeps power but host controller does not */
2736                 sdhci_init(host, 0);
2737                 host->pwr = 0;
2738                 host->clock = 0;
2739                 sdhci_do_set_ios(host, &host->mmc->ios);
2740         } else {
2741                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2742                 mmiowb();
2743         }
2744
2745         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2746                 ret = request_threaded_irq(host->irq, sdhci_irq,
2747                                            sdhci_thread_irq, IRQF_SHARED,
2748                                            mmc_hostname(host->mmc), host);
2749                 if (ret)
2750                         return ret;
2751         } else {
2752                 sdhci_disable_irq_wakeups(host);
2753         }
2754
2755         sdhci_enable_card_detection(host);
2756
2757         return ret;
2758 }
2759
2760 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2761
2762 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2763 {
2764         return pm_runtime_get_sync(host->mmc->parent);
2765 }
2766
2767 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2768 {
2769         pm_runtime_mark_last_busy(host->mmc->parent);
2770         return pm_runtime_put_autosuspend(host->mmc->parent);
2771 }
2772
2773 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2774 {
2775         if (host->bus_on)
2776                 return;
2777         host->bus_on = true;
2778         pm_runtime_get_noresume(host->mmc->parent);
2779 }
2780
2781 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2782 {
2783         if (!host->bus_on)
2784                 return;
2785         host->bus_on = false;
2786         pm_runtime_put_noidle(host->mmc->parent);
2787 }
2788
2789 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2790 {
2791         unsigned long flags;
2792
2793         mmc_retune_timer_stop(host->mmc);
2794         mmc_retune_needed(host->mmc);
2795
2796         spin_lock_irqsave(&host->lock, flags);
2797         host->ier &= SDHCI_INT_CARD_INT;
2798         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2799         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2800         spin_unlock_irqrestore(&host->lock, flags);
2801
2802         synchronize_hardirq(host->irq);
2803
2804         spin_lock_irqsave(&host->lock, flags);
2805         host->runtime_suspended = true;
2806         spin_unlock_irqrestore(&host->lock, flags);
2807
2808         return 0;
2809 }
2810 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2811
2812 int sdhci_runtime_resume_host(struct sdhci_host *host)
2813 {
2814         unsigned long flags;
2815         int host_flags = host->flags;
2816
2817         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2818                 if (host->ops->enable_dma)
2819                         host->ops->enable_dma(host);
2820         }
2821
2822         sdhci_init(host, 0);
2823
2824         /* Force clock and power re-program */
2825         host->pwr = 0;
2826         host->clock = 0;
2827         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2828         sdhci_do_set_ios(host, &host->mmc->ios);
2829
2830         if ((host_flags & SDHCI_PV_ENABLED) &&
2831                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2832                 spin_lock_irqsave(&host->lock, flags);
2833                 sdhci_enable_preset_value(host, true);
2834                 spin_unlock_irqrestore(&host->lock, flags);
2835         }
2836
2837         spin_lock_irqsave(&host->lock, flags);
2838
2839         host->runtime_suspended = false;
2840
2841         /* Enable SDIO IRQ */
2842         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2843                 sdhci_enable_sdio_irq_nolock(host, true);
2844
2845         /* Enable Card Detection */
2846         sdhci_enable_card_detection(host);
2847
2848         spin_unlock_irqrestore(&host->lock, flags);
2849
2850         return 0;
2851 }
2852 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2853
2854 #endif /* CONFIG_PM */
2855
2856 /*****************************************************************************\
2857  *                                                                           *
2858  * Device allocation/registration                                            *
2859  *                                                                           *
2860 \*****************************************************************************/
2861
2862 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2863         size_t priv_size)
2864 {
2865         struct mmc_host *mmc;
2866         struct sdhci_host *host;
2867
2868         WARN_ON(dev == NULL);
2869
2870         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2871         if (!mmc)
2872                 return ERR_PTR(-ENOMEM);
2873
2874         host = mmc_priv(mmc);
2875         host->mmc = mmc;
2876         host->mmc_host_ops = sdhci_ops;
2877         mmc->ops = &host->mmc_host_ops;
2878
2879         return host;
2880 }
2881
2882 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2883
2884 int sdhci_add_host(struct sdhci_host *host)
2885 {
2886         struct mmc_host *mmc;
2887         u32 caps[2] = {0, 0};
2888         u32 max_current_caps;
2889         unsigned int ocr_avail;
2890         unsigned int override_timeout_clk;
2891         u32 max_clk;
2892         int ret;
2893
2894         WARN_ON(host == NULL);
2895         if (host == NULL)
2896                 return -EINVAL;
2897
2898         mmc = host->mmc;
2899
2900         if (debug_quirks)
2901                 host->quirks = debug_quirks;
2902         if (debug_quirks2)
2903                 host->quirks2 = debug_quirks2;
2904
2905         override_timeout_clk = host->timeout_clk;
2906
2907         sdhci_do_reset(host, SDHCI_RESET_ALL);
2908
2909         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2910         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2911                                 >> SDHCI_SPEC_VER_SHIFT;
2912         if (host->version > SDHCI_SPEC_300) {
2913                 pr_err("%s: Unknown controller version (%d). "
2914                         "You may experience problems.\n", mmc_hostname(mmc),
2915                         host->version);
2916         }
2917
2918         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2919                 sdhci_readl(host, SDHCI_CAPABILITIES);
2920
2921         if (host->version >= SDHCI_SPEC_300)
2922                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2923                         host->caps1 :
2924                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2925
2926         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2927                 host->flags |= SDHCI_USE_SDMA;
2928         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2929                 DBG("Controller doesn't have SDMA capability\n");
2930         else
2931                 host->flags |= SDHCI_USE_SDMA;
2932
2933         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2934                 (host->flags & SDHCI_USE_SDMA)) {
2935                 DBG("Disabling DMA as it is marked broken\n");
2936                 host->flags &= ~SDHCI_USE_SDMA;
2937         }
2938
2939         if ((host->version >= SDHCI_SPEC_200) &&
2940                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2941                 host->flags |= SDHCI_USE_ADMA;
2942
2943         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2944                 (host->flags & SDHCI_USE_ADMA)) {
2945                 DBG("Disabling ADMA as it is marked broken\n");
2946                 host->flags &= ~SDHCI_USE_ADMA;
2947         }
2948
2949         /*
2950          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2951          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2952          * that during the first call to ->enable_dma().  Similarly
2953          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2954          * implement.
2955          */
2956         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2957                 host->flags |= SDHCI_USE_64_BIT_DMA;
2958
2959         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2960                 if (host->ops->enable_dma) {
2961                         if (host->ops->enable_dma(host)) {
2962                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2963                                         mmc_hostname(mmc));
2964                                 host->flags &=
2965                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2966                         }
2967                 }
2968         }
2969
2970         /* SDMA does not support 64-bit DMA */
2971         if (host->flags & SDHCI_USE_64_BIT_DMA)
2972                 host->flags &= ~SDHCI_USE_SDMA;
2973
2974         if (host->flags & SDHCI_USE_ADMA) {
2975                 /*
2976                  * The DMA descriptor table size is calculated as the maximum
2977                  * number of segments times 2, to allow for an alignment
2978                  * descriptor for each segment, plus 1 for a nop end descriptor,
2979                  * all multipled by the descriptor size.
2980                  */
2981                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2982                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2983                                               SDHCI_ADMA2_64_DESC_SZ;
2984                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2985                                                 SDHCI_ADMA2_64_ALIGN;
2986                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2987                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
2988                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2989                 } else {
2990                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2991                                               SDHCI_ADMA2_32_DESC_SZ;
2992                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2993                                                 SDHCI_ADMA2_32_ALIGN;
2994                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2995                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
2996                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2997                 }
2998                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2999                                                       host->adma_table_sz,
3000                                                       &host->adma_addr,
3001                                                       GFP_KERNEL);
3002                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3003                 if (!host->adma_table || !host->align_buffer) {
3004                         if (host->adma_table)
3005                                 dma_free_coherent(mmc_dev(mmc),
3006                                                   host->adma_table_sz,
3007                                                   host->adma_table,
3008                                                   host->adma_addr);
3009                         kfree(host->align_buffer);
3010                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3011                                 mmc_hostname(mmc));
3012                         host->flags &= ~SDHCI_USE_ADMA;
3013                         host->adma_table = NULL;
3014                         host->align_buffer = NULL;
3015                 } else if (host->adma_addr & host->align_mask) {
3016                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3017                                 mmc_hostname(mmc));
3018                         host->flags &= ~SDHCI_USE_ADMA;
3019                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3020                                           host->adma_table, host->adma_addr);
3021                         kfree(host->align_buffer);
3022                         host->adma_table = NULL;
3023                         host->align_buffer = NULL;
3024                 }
3025         }
3026
3027         /*
3028          * If we use DMA, then it's up to the caller to set the DMA
3029          * mask, but PIO does not need the hw shim so we set a new
3030          * mask here in that case.
3031          */
3032         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3033                 host->dma_mask = DMA_BIT_MASK(64);
3034                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3035         }
3036
3037         if (host->version >= SDHCI_SPEC_300)
3038                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3039                         >> SDHCI_CLOCK_BASE_SHIFT;
3040         else
3041                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3042                         >> SDHCI_CLOCK_BASE_SHIFT;
3043
3044         host->max_clk *= 1000000;
3045         if (host->max_clk == 0 || host->quirks &
3046                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {