drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  42         defined(CONFIG_MMC_SDHCI_MODULE))
  43 #define SDHCI_USE_LEDS_CLASS
  44 #endif
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  57                                         struct mmc_data *data);
  58 static int sdhci_do_get_cd(struct sdhci_host *host);
  59
  60 #ifdef CONFIG_PM
  61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  65 #else
  66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  67 {
  68         return 0;
  69 }
  70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  71 {
  72         return 0;
  73 }
  74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  75 {
  76 }
  77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  78 {
  79 }
  80 #endif
  81
  82 static void sdhci_dumpregs(struct sdhci_host *host)
  83 {
  84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  85                 mmc_hostname(host->mmc));
  86
  87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  89                 sdhci_readw(host, SDHCI_HOST_VERSION));
  90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_ARGUMENT),
  95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 107                 sdhci_readl(host, SDHCI_INT_STATUS));
 108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 109                 sdhci_readl(host, SDHCI_INT_ENABLE),
 110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 115                 sdhci_readl(host, SDHCI_CAPABILITIES),
 116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_COMMAND),
 119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 122
 123         if (host->flags & SDHCI_USE_ADMA) {
 124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 129                 else
 130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 133         }
 134
 135         pr_debug(DRIVER_NAME ": ===========================================\n");
 136 }
 137
 138 /*****************************************************************************\
 139  *                                                                           *
 140  * Low level functions                                                       *
 141  *                                                                           *
 142 \*****************************************************************************/
 143
 144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 145 {
 146         u32 present;
 147
 148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 150                 return;
 151
 152         if (enable) {
 153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                                       SDHCI_CARD_PRESENT;
 155
 156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 157                                        SDHCI_INT_CARD_INSERT;
 158         } else {
 159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 160         }
 161
 162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 164 }
 165
 166 static void sdhci_enable_card_detection(struct sdhci_host *host)
 167 {
 168         sdhci_set_card_detection(host, true);
 169 }
 170
 171 static void sdhci_disable_card_detection(struct sdhci_host *host)
 172 {
 173         sdhci_set_card_detection(host, false);
 174 }
 175
 176 void sdhci_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         unsigned long timeout;
 179
 180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 181
 182         if (mask & SDHCI_RESET_ALL) {
 183                 host->clock = 0;
 184                 /* Reset-all turns off SD Bus Power */
 185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 186                         sdhci_runtime_pm_bus_off(host);
 187         }
 188
 189         /* Wait max 100 ms */
 190         timeout = 100;
 191
 192         /* hw clears the bit when it's done */
 193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 194                 if (timeout == 0) {
 195                         pr_err("%s: Reset 0x%x never completed.\n",
 196                                 mmc_hostname(host->mmc), (int)mask);
 197                         sdhci_dumpregs(host);
 198                         return;
 199                 }
 200                 timeout--;
 201                 mdelay(1);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 if (!sdhci_do_get_cd(host))
 210                         return;
 211         }
 212
 213         host->ops->reset(host, mask);
 214
 215         if (mask & SDHCI_RESET_ALL) {
 216                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 217                         if (host->ops->enable_dma)
 218                                 host->ops->enable_dma(host);
 219                 }
 220
 221                 /* Resetting the controller clears many */
 222                 host->preset_enabled = false;
 223         }
 224 }
 225
 226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 227
 228 static void sdhci_init(struct sdhci_host *host, int soft)
 229 {
 230         if (soft)
 231                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 232         else
 233                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 234
 235         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 236                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 237                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 238                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 239                     SDHCI_INT_RESPONSE;
 240
 241         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 242         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 243
 244         if (soft) {
 245                 /* force clock reconfiguration */
 246                 host->clock = 0;
 247                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 248         }
 249 }
 250
 251 static void sdhci_reinit(struct sdhci_host *host)
 252 {
 253         sdhci_init(host, 0);
 254         sdhci_enable_card_detection(host);
 255 }
 256
 257 static void sdhci_activate_led(struct sdhci_host *host)
 258 {
 259         u8 ctrl;
 260
 261         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 262         ctrl |= SDHCI_CTRL_LED;
 263         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 264 }
 265
 266 static void sdhci_deactivate_led(struct sdhci_host *host)
 267 {
 268         u8 ctrl;
 269
 270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 271         ctrl &= ~SDHCI_CTRL_LED;
 272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 273 }
 274
 275 #ifdef SDHCI_USE_LEDS_CLASS
 276 static void sdhci_led_control(struct led_classdev *led,
 277         enum led_brightness brightness)
 278 {
 279         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&host->lock, flags);
 283
 284         if (host->runtime_suspended)
 285                 goto out;
 286
 287         if (brightness == LED_OFF)
 288                 sdhci_deactivate_led(host);
 289         else
 290                 sdhci_activate_led(host);
 291 out:
 292         spin_unlock_irqrestore(&host->lock, flags);
 293 }
 294 #endif
 295
 296 /*****************************************************************************\
 297  *                                                                           *
 298  * Core functions                                                            *
 299  *                                                                           *
 300 \*****************************************************************************/
 301
 302 static void sdhci_read_block_pio(struct sdhci_host *host)
 303 {
 304         unsigned long flags;
 305         size_t blksize, len, chunk;
 306         u32 uninitialized_var(scratch);
 307         u8 *buf;
 308
 309         DBG("PIO reading\n");
 310
 311         blksize = host->data->blksz;
 312         chunk = 0;
 313
 314         local_irq_save(flags);
 315
 316         while (blksize) {
 317                 BUG_ON(!sg_miter_next(&host->sg_miter));
 318
 319                 len = min(host->sg_miter.length, blksize);
 320
 321                 blksize -= len;
 322                 host->sg_miter.consumed = len;
 323
 324                 buf = host->sg_miter.addr;
 325
 326                 while (len) {
 327                         if (chunk == 0) {
 328                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 329                                 chunk = 4;
 330                         }
 331
 332                         *buf = scratch & 0xFF;
 333
 334                         buf++;
 335                         scratch >>= 8;
 336                         chunk--;
 337                         len--;
 338                 }
 339         }
 340
 341         sg_miter_stop(&host->sg_miter);
 342
 343         local_irq_restore(flags);
 344 }
 345
 346 static void sdhci_write_block_pio(struct sdhci_host *host)
 347 {
 348         unsigned long flags;
 349         size_t blksize, len, chunk;
 350         u32 scratch;
 351         u8 *buf;
 352
 353         DBG("PIO writing\n");
 354
 355         blksize = host->data->blksz;
 356         chunk = 0;
 357         scratch = 0;
 358
 359         local_irq_save(flags);
 360
 361         while (blksize) {
 362                 BUG_ON(!sg_miter_next(&host->sg_miter));
 363
 364                 len = min(host->sg_miter.length, blksize);
 365
 366                 blksize -= len;
 367                 host->sg_miter.consumed = len;
 368
 369                 buf = host->sg_miter.addr;
 370
 371                 while (len) {
 372                         scratch |= (u32)*buf << (chunk * 8);
 373
 374                         buf++;
 375                         chunk++;
 376                         len--;
 377
 378                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 379                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 380                                 chunk = 0;
 381                                 scratch = 0;
 382                         }
 383                 }
 384         }
 385
 386         sg_miter_stop(&host->sg_miter);
 387
 388         local_irq_restore(flags);
 389 }
 390
 391 static void sdhci_transfer_pio(struct sdhci_host *host)
 392 {
 393         u32 mask;
 394
 395         BUG_ON(!host->data);
 396
 397         if (host->blocks == 0)
 398                 return;
 399
 400         if (host->data->flags & MMC_DATA_READ)
 401                 mask = SDHCI_DATA_AVAILABLE;
 402         else
 403                 mask = SDHCI_SPACE_AVAILABLE;
 404
 405         /*
 406          * Some controllers (JMicron JMB38x) mess up the buffer bits
 407          * for transfers < 4 bytes. As long as it is just one block,
 408          * we can ignore the bits.
 409          */
 410         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 411                 (host->data->blocks == 1))
 412                 mask = ~0;
 413
 414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 415                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 416                         udelay(100);
 417
 418                 if (host->data->flags & MMC_DATA_READ)
 419                         sdhci_read_block_pio(host);
 420                 else
 421                         sdhci_write_block_pio(host);
 422
 423                 host->blocks--;
 424                 if (host->blocks == 0)
 425                         break;
 426         }
 427
 428         DBG("PIO transfer complete.\n");
 429 }
 430
 431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 432 {
 433         local_irq_save(*flags);
 434         return kmap_atomic(sg_page(sg)) + sg->offset;
 435 }
 436
 437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 438 {
 439         kunmap_atomic(buffer);
 440         local_irq_restore(*flags);
 441 }
 442
 443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 444                                   dma_addr_t addr, int len, unsigned cmd)
 445 {
 446         struct sdhci_adma2_64_desc *dma_desc = desc;
 447
 448         /* 32-bit and 64-bit descriptors have these members in same position */
 449         dma_desc->cmd = cpu_to_le16(cmd);
 450         dma_desc->len = cpu_to_le16(len);
 451         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 452
 453         if (host->flags & SDHCI_USE_64_BIT_DMA)
 454                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 455 }
 456
 457 static void sdhci_adma_mark_end(void *desc)
 458 {
 459         struct sdhci_adma2_64_desc *dma_desc = desc;
 460
 461         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 462         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 463 }
 464
 465 static int sdhci_adma_table_pre(struct sdhci_host *host,
 466         struct mmc_data *data)
 467 {
 468         int direction;
 469
 470         void *desc;
 471         void *align;
 472         dma_addr_t addr;
 473         dma_addr_t align_addr;
 474         int len, offset;
 475
 476         struct scatterlist *sg;
 477         int i;
 478         char *buffer;
 479         unsigned long flags;
 480
 481         /*
 482          * The spec does not specify endianness of descriptor table.
 483          * We currently guess that it is LE.
 484          */
 485
 486         if (data->flags & MMC_DATA_READ)
 487                 direction = DMA_FROM_DEVICE;
 488         else
 489                 direction = DMA_TO_DEVICE;
 490
 491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 492                 host->align_buffer, host->align_buffer_sz, direction);
 493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 494                 goto fail;
 495         BUG_ON(host->align_addr & SDHCI_ADMA2_MASK);
 496
 497         host->sg_count = sdhci_pre_dma_transfer(host, data);
 498         if (host->sg_count < 0)
 499                 goto unmap_align;
 500
 501         desc = host->adma_table;
 502         align = host->align_buffer;
 503
 504         align_addr = host->align_addr;
 505
 506         for_each_sg(data->sg, sg, host->sg_count, i) {
 507                 addr = sg_dma_address(sg);
 508                 len = sg_dma_len(sg);
 509
 510                 /*
 511                  * The SDHCI specification states that ADMA
 512                  * addresses must be 32-bit aligned. If they
 513                  * aren't, then we use a bounce buffer for
 514                  * the (up to three) bytes that screw up the
 515                  * alignment.
 516                  */
 517                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 518                          SDHCI_ADMA2_MASK;
 519                 if (offset) {
 520                         if (data->flags & MMC_DATA_WRITE) {
 521                                 buffer = sdhci_kmap_atomic(sg, &flags);
 522                                 memcpy(align, buffer, offset);
 523                                 sdhci_kunmap_atomic(buffer, &flags);
 524                         }
 525
 526                         /* tran, valid */
 527                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 528                                               ADMA2_TRAN_VALID);
 529
 530                         BUG_ON(offset > 65536);
 531
 532                         align += SDHCI_ADMA2_ALIGN;
 533                         align_addr += SDHCI_ADMA2_ALIGN;
 534
 535                         desc += host->desc_sz;
 536
 537                         addr += offset;
 538                         len -= offset;
 539                 }
 540
 541                 BUG_ON(len > 65536);
 542
 543                 if (len) {
 544                         /* tran, valid */
 545                         sdhci_adma_write_desc(host, desc, addr, len,
 546                                               ADMA2_TRAN_VALID);
 547                         desc += host->desc_sz;
 548                 }
 549
 550                 /*
 551                  * If this triggers then we have a calculation bug
 552                  * somewhere. :/
 553                  */
 554                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 555         }
 556
 557         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 558                 /*
 559                 * Mark the last descriptor as the terminating descriptor
 560                 */
 561                 if (desc != host->adma_table) {
 562                         desc -= host->desc_sz;
 563                         sdhci_adma_mark_end(desc);
 564                 }
 565         } else {
 566                 /*
 567                 * Add a terminating entry.
 568                 */
 569
 570                 /* nop, end, valid */
 571                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 572         }
 573
 574         /*
 575          * Resync align buffer as we might have changed it.
 576          */
 577         if (data->flags & MMC_DATA_WRITE) {
 578                 dma_sync_single_for_device(mmc_dev(host->mmc),
 579                         host->align_addr, host->align_buffer_sz, direction);
 580         }
 581
 582         return 0;
 583
 584 unmap_align:
 585         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 586                 host->align_buffer_sz, direction);
 587 fail:
 588         return -EINVAL;
 589 }
 590
 591 static void sdhci_adma_table_post(struct sdhci_host *host,
 592         struct mmc_data *data)
 593 {
 594         int direction;
 595
 596         struct scatterlist *sg;
 597         int i, size;
 598         void *align;
 599         char *buffer;
 600         unsigned long flags;
 601         bool has_unaligned;
 602
 603         if (data->flags & MMC_DATA_READ)
 604                 direction = DMA_FROM_DEVICE;
 605         else
 606                 direction = DMA_TO_DEVICE;
 607
 608         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 609                 host->align_buffer_sz, direction);
 610
 611         /* Do a quick scan of the SG list for any unaligned mappings */
 612         has_unaligned = false;
 613         for_each_sg(data->sg, sg, host->sg_count, i)
 614                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 615                         has_unaligned = true;
 616                         break;
 617                 }
 618
 619         if (has_unaligned && data->flags & MMC_DATA_READ) {
 620                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 621                         data->sg_len, direction);
 622
 623                 align = host->align_buffer;
 624
 625                 for_each_sg(data->sg, sg, host->sg_count, i) {
 626                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 627                                 size = SDHCI_ADMA2_ALIGN -
 628                                        (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 629
 630                                 buffer = sdhci_kmap_atomic(sg, &flags);
 631                                 memcpy(buffer, align, size);
 632                                 sdhci_kunmap_atomic(buffer, &flags);
 633
 634                                 align += SDHCI_ADMA2_ALIGN;
 635                         }
 636                 }
 637         }
 638
 639         if (data->host_cookie == COOKIE_MAPPED) {
 640                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 641                         data->sg_len, direction);
 642                 data->host_cookie = COOKIE_UNMAPPED;
 643         }
 644 }
 645
 646 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 647 {
 648         u8 count;
 649         struct mmc_data *data = cmd->data;
 650         unsigned target_timeout, current_timeout;
 651
 652         /*
 653          * If the host controller provides us with an incorrect timeout
 654          * value, just skip the check and use 0xE.  The hardware may take
 655          * longer to time out, but that's much better than having a too-short
 656          * timeout value.
 657          */
 658         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 659                 return 0xE;
 660
 661         /* Unspecified timeout, assume max */
 662         if (!data && !cmd->busy_timeout)
 663                 return 0xE;
 664
 665         /* timeout in us */
 666         if (!data)
 667                 target_timeout = cmd->busy_timeout * 1000;
 668         else {
 669                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
 670                 if (host->clock && data->timeout_clks) {
 671                         unsigned long long val;
 672
 673                         /*
 674                          * data->timeout_clks is in units of clock cycles.
 675                          * host->clock is in Hz.  target_timeout is in us.
 676                          * Hence, us = 1000000 * cycles / Hz.  Round up.
 677                          */
 678                         val = 1000000ULL * data->timeout_clks;
 679                         if (do_div(val, host->clock))
 680                                 target_timeout++;
 681                         target_timeout += val;
 682                 }
 683         }
 684
 685         /*
 686          * Figure out needed cycles.
 687          * We do this in steps in order to fit inside a 32 bit int.
 688          * The first step is the minimum timeout, which will have a
 689          * minimum resolution of 6 bits:
 690          * (1) 2^13*1000 > 2^22,
 691          * (2) host->timeout_clk < 2^16
 692          *     =>
 693          *     (1) / (2) > 2^6
 694          */
 695         count = 0;
 696         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 697         while (current_timeout < target_timeout) {
 698                 count++;
 699                 current_timeout <<= 1;
 700                 if (count >= 0xF)
 701                         break;
 702         }
 703
 704         if (count >= 0xF) {
 705                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 706                     mmc_hostname(host->mmc), count, cmd->opcode);
 707                 count = 0xE;
 708         }
 709
 710         return count;
 711 }
 712
 713 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 714 {
 715         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 716         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 717
 718         if (host->flags & SDHCI_REQ_USE_DMA)
 719                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 720         else
 721                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 722
 723         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 724         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 725 }
 726
 727 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 728 {
 729         u8 count;
 730
 731         if (host->ops->set_timeout) {
 732                 host->ops->set_timeout(host, cmd);
 733         } else {
 734                 count = sdhci_calc_timeout(host, cmd);
 735                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 736         }
 737 }
 738
 739 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 740 {
 741         u8 ctrl;
 742         struct mmc_data *data = cmd->data;
 743         int ret;
 744
 745         WARN_ON(host->data);
 746
 747         if (data || (cmd->flags & MMC_RSP_BUSY))
 748                 sdhci_set_timeout(host, cmd);
 749
 750         if (!data)
 751                 return;
 752
 753         /* Sanity checks */
 754         BUG_ON(data->blksz * data->blocks > 524288);
 755         BUG_ON(data->blksz > host->mmc->max_blk_size);
 756         BUG_ON(data->blocks > 65535);
 757
 758         host->data = data;
 759         host->data_early = 0;
 760         host->data->bytes_xfered = 0;
 761
 762         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 763                 host->flags |= SDHCI_REQ_USE_DMA;
 764
 765         /*
 766          * FIXME: This doesn't account for merging when mapping the
 767          * scatterlist.
 768          */
 769         if (host->flags & SDHCI_REQ_USE_DMA) {
 770                 int broken, i;
 771                 struct scatterlist *sg;
 772
 773                 broken = 0;
 774                 if (host->flags & SDHCI_USE_ADMA) {
 775                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 776                                 broken = 1;
 777                 } else {
 778                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 779                                 broken = 1;
 780                 }
 781
 782                 if (unlikely(broken)) {
 783                         for_each_sg(data->sg, sg, data->sg_len, i) {
 784                                 if (sg->length & 0x3) {
 785                                         DBG("Reverting to PIO because of "
 786                                                 "transfer size (%d)\n",
 787                                                 sg->length);
 788                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 789                                         break;
 790                                 }
 791                         }
 792                 }
 793         }
 794
 795         /*
 796          * The assumption here being that alignment is the same after
 797          * translation to device address space.
 798          */
 799         if (host->flags & SDHCI_REQ_USE_DMA) {
 800                 int broken, i;
 801                 struct scatterlist *sg;
 802
 803                 broken = 0;
 804                 if (host->flags & SDHCI_USE_ADMA) {
 805                         /*
 806                          * As we use 3 byte chunks to work around
 807                          * alignment problems, we need to check this
 808                          * quirk.
 809                          */
 810                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 811                                 broken = 1;
 812                 } else {
 813                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 814                                 broken = 1;
 815                 }
 816
 817                 if (unlikely(broken)) {
 818                         for_each_sg(data->sg, sg, data->sg_len, i) {
 819                                 if (sg->offset & 0x3) {
 820                                         DBG("Reverting to PIO because of "
 821                                                 "bad alignment\n");
 822                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 823                                         break;
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         if (host->flags & SDHCI_REQ_USE_DMA) {
 830                 if (host->flags & SDHCI_USE_ADMA) {
 831                         ret = sdhci_adma_table_pre(host, data);
 832                         if (ret) {
 833                                 /*
 834                                  * This only happens when someone fed
 835                                  * us an invalid request.
 836                                  */
 837                                 WARN_ON(1);
 838                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 839                         } else {
 840                                 sdhci_writel(host, host->adma_addr,
 841                                         SDHCI_ADMA_ADDRESS);
 842                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 843                                         sdhci_writel(host,
 844                                                      (u64)host->adma_addr >> 32,
 845                                                      SDHCI_ADMA_ADDRESS_HI);
 846                         }
 847                 } else {
 848                         int sg_cnt;
 849
 850                         sg_cnt = sdhci_pre_dma_transfer(host, data);
 851                         if (sg_cnt <= 0) {
 852                                 /*
 853                                  * This only happens when someone fed
 854                                  * us an invalid request.
 855                                  */
 856                                 WARN_ON(1);
 857                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 858                         } else {
 859                                 WARN_ON(sg_cnt != 1);
 860                                 sdhci_writel(host, sg_dma_address(data->sg),
 861                                         SDHCI_DMA_ADDRESS);
 862                         }
 863                 }
 864         }
 865
 866         /*
 867          * Always adjust the DMA selection as some controllers
 868          * (e.g. JMicron) can't do PIO properly when the selection
 869          * is ADMA.
 870          */
 871         if (host->version >= SDHCI_SPEC_200) {
 872                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 873                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 874                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 875                         (host->flags & SDHCI_USE_ADMA)) {
 876                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 877                                 ctrl |= SDHCI_CTRL_ADMA64;
 878                         else
 879                                 ctrl |= SDHCI_CTRL_ADMA32;
 880                 } else {
 881                         ctrl |= SDHCI_CTRL_SDMA;
 882                 }
 883                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 884         }
 885
 886         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 887                 int flags;
 888
 889                 flags = SG_MITER_ATOMIC;
 890                 if (host->data->flags & MMC_DATA_READ)
 891                         flags |= SG_MITER_TO_SG;
 892                 else
 893                         flags |= SG_MITER_FROM_SG;
 894                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 895                 host->blocks = data->blocks;
 896         }
 897
 898         sdhci_set_transfer_irqs(host);
 899
 900         /* Set the DMA boundary value and block size */
 901         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 902                 data->blksz), SDHCI_BLOCK_SIZE);
 903         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 904 }
 905
 906 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 907         struct mmc_command *cmd)
 908 {
 909         u16 mode = 0;
 910         struct mmc_data *data = cmd->data;
 911
 912         if (data == NULL) {
 913                 if (host->quirks2 &
 914                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 915                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 916                 } else {
 917                 /* clear Auto CMD settings for no data CMDs */
 918                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 919                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 920                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 921                 }
 922                 return;
 923         }
 924
 925         WARN_ON(!host->data);
 926
 927         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 928                 mode = SDHCI_TRNS_BLK_CNT_EN;
 929
 930         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 931                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 932                 /*
 933                  * If we are sending CMD23, CMD12 never gets sent
 934                  * on successful completion (so no Auto-CMD12).
 935                  */
 936                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 937                     (cmd->opcode != SD_IO_RW_EXTENDED))
 938                         mode |= SDHCI_TRNS_AUTO_CMD12;
 939                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 940                         mode |= SDHCI_TRNS_AUTO_CMD23;
 941                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 942                 }
 943         }
 944
 945         if (data->flags & MMC_DATA_READ)
 946                 mode |= SDHCI_TRNS_READ;
 947         if (host->flags & SDHCI_REQ_USE_DMA)
 948                 mode |= SDHCI_TRNS_DMA;
 949
 950         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 951 }
 952
 953 static void sdhci_finish_data(struct sdhci_host *host)
 954 {
 955         struct mmc_data *data;
 956
 957         BUG_ON(!host->data);
 958
 959         data = host->data;
 960         host->data = NULL;
 961
 962         if (host->flags & SDHCI_REQ_USE_DMA) {
 963                 if (host->flags & SDHCI_USE_ADMA)
 964                         sdhci_adma_table_post(host, data);
 965                 else {
 966                         if (data->host_cookie == COOKIE_MAPPED) {
 967                                 dma_unmap_sg(mmc_dev(host->mmc),
 968                                         data->sg, data->sg_len,
 969                                         (data->flags & MMC_DATA_READ) ?
 970                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 971                                 data->host_cookie = COOKIE_UNMAPPED;
 972                         }
 973                 }
 974         }
 975
 976         /*
 977          * The specification states that the block count register must
 978          * be updated, but it does not specify at what point in the
 979          * data flow. That makes the register entirely useless to read
 980          * back so we have to assume that nothing made it to the card
 981          * in the event of an error.
 982          */
 983         if (data->error)
 984                 data->bytes_xfered = 0;
 985         else
 986                 data->bytes_xfered = data->blksz * data->blocks;
 987
 988         /*
 989          * Need to send CMD12 if -
 990          * a) open-ended multiblock transfer (no CMD23)
 991          * b) error in multiblock transfer
 992          */
 993         if (data->stop &&
 994             (data->error ||
 995              !host->mrq->sbc)) {
 996
 997                 /*
 998                  * The controller needs a reset of internal state machines
 999                  * upon error conditions.
1000                  */
1001                 if (data->error) {
1002                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1003                         sdhci_do_reset(host, SDHCI_RESET_DATA);
1004                 }
1005
1006                 sdhci_send_command(host, data->stop);
1007         } else
1008                 tasklet_schedule(&host->finish_tasklet);
1009 }
1010
1011 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1012 {
1013         int flags;
1014         u32 mask;
1015         unsigned long timeout;
1016
1017         WARN_ON(host->cmd);
1018
1019         /* Wait max 10 ms */
1020         timeout = 10;
1021
1022         mask = SDHCI_CMD_INHIBIT;
1023         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1024                 mask |= SDHCI_DATA_INHIBIT;
1025
1026         /* We shouldn't wait for data inihibit for stop commands, even
1027            though they might use busy signaling */
1028         if (host->mrq->data && (cmd == host->mrq->data->stop))
1029                 mask &= ~SDHCI_DATA_INHIBIT;
1030
1031         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1032                 if (timeout == 0) {
1033                         pr_err("%s: Controller never released "
1034                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1035                         sdhci_dumpregs(host);
1036                         cmd->error = -EIO;
1037                         tasklet_schedule(&host->finish_tasklet);
1038                         return;
1039                 }
1040                 timeout--;
1041                 mdelay(1);
1042         }
1043
1044         timeout = jiffies;
1045         if (!cmd->data && cmd->busy_timeout > 9000)
1046                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1047         else
1048                 timeout += 10 * HZ;
1049         mod_timer(&host->timer, timeout);
1050
1051         host->cmd = cmd;
1052         host->busy_handle = 0;
1053
1054         sdhci_prepare_data(host, cmd);
1055
1056         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1057
1058         sdhci_set_transfer_mode(host, cmd);
1059
1060         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1061                 pr_err("%s: Unsupported response type!\n",
1062                         mmc_hostname(host->mmc));
1063                 cmd->error = -EINVAL;
1064                 tasklet_schedule(&host->finish_tasklet);
1065                 return;
1066         }
1067
1068         if (!(cmd->flags & MMC_RSP_PRESENT))
1069                 flags = SDHCI_CMD_RESP_NONE;
1070         else if (cmd->flags & MMC_RSP_136)
1071                 flags = SDHCI_CMD_RESP_LONG;
1072         else if (cmd->flags & MMC_RSP_BUSY)
1073                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1074         else
1075                 flags = SDHCI_CMD_RESP_SHORT;
1076
1077         if (cmd->flags & MMC_RSP_CRC)
1078                 flags |= SDHCI_CMD_CRC;
1079         if (cmd->flags & MMC_RSP_OPCODE)
1080                 flags |= SDHCI_CMD_INDEX;
1081
1082         /* CMD19 is special in that the Data Present Select should be set */
1083         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1084             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1085                 flags |= SDHCI_CMD_DATA;
1086
1087         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1088 }
1089 EXPORT_SYMBOL_GPL(sdhci_send_command);
1090
1091 static void sdhci_finish_command(struct sdhci_host *host)
1092 {
1093         int i;
1094
1095         BUG_ON(host->cmd == NULL);
1096
1097         if (host->cmd->flags & MMC_RSP_PRESENT) {
1098                 if (host->cmd->flags & MMC_RSP_136) {
1099                         /* CRC is stripped so we need to do some shifting. */
1100                         for (i = 0;i < 4;i++) {
1101                                 host->cmd->resp[i] = sdhci_readl(host,
1102                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1103                                 if (i != 3)
1104                                         host->cmd->resp[i] |=
1105                                                 sdhci_readb(host,
1106                                                 SDHCI_RESPONSE + (3-i)*4-1);
1107                         }
1108                 } else {
1109                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1110                 }
1111         }
1112
1113         host->cmd->error = 0;
1114
1115         /* Finished CMD23, now send actual command. */
1116         if (host->cmd == host->mrq->sbc) {
1117                 host->cmd = NULL;
1118                 sdhci_send_command(host, host->mrq->cmd);
1119         } else {
1120
1121                 /* Processed actual command. */
1122                 if (host->data && host->data_early)
1123                         sdhci_finish_data(host);
1124
1125                 if (!host->cmd->data)
1126                         tasklet_schedule(&host->finish_tasklet);
1127
1128                 host->cmd = NULL;
1129         }
1130 }
1131
1132 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1133 {
1134         u16 preset = 0;
1135
1136         switch (host->timing) {
1137         case MMC_TIMING_UHS_SDR12:
1138                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1139                 break;
1140         case MMC_TIMING_UHS_SDR25:
1141                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1142                 break;
1143         case MMC_TIMING_UHS_SDR50:
1144                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1145                 break;
1146         case MMC_TIMING_UHS_SDR104:
1147         case MMC_TIMING_MMC_HS200:
1148                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1149                 break;
1150         case MMC_TIMING_UHS_DDR50:
1151         case MMC_TIMING_MMC_DDR52:
1152                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1153                 break;
1154         case MMC_TIMING_MMC_HS400:
1155                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1156                 break;
1157         default:
1158                 pr_warn("%s: Invalid UHS-I mode selected\n",
1159                         mmc_hostname(host->mmc));
1160                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1161                 break;
1162         }
1163         return preset;
1164 }
1165
1166 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1167 {
1168         int div = 0; /* Initialized for compiler warning */
1169         int real_div = div, clk_mul = 1;
1170         u16 clk = 0;
1171         unsigned long timeout;
1172         bool switch_base_clk = false;
1173
1174         host->mmc->actual_clock = 0;
1175
1176         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1177         if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1178                 mdelay(1);
1179
1180         if (clock == 0)
1181                 return;
1182
1183         if (host->version >= SDHCI_SPEC_300) {
1184                 if (host->preset_enabled) {
1185                         u16 pre_val;
1186
1187                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1188                         pre_val = sdhci_get_preset_value(host);
1189                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1190                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1191                         if (host->clk_mul &&
1192                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1193                                 clk = SDHCI_PROG_CLOCK_MODE;
1194                                 real_div = div + 1;
1195                                 clk_mul = host->clk_mul;
1196                         } else {
1197                                 real_div = max_t(int, 1, div << 1);
1198                         }
1199                         goto clock_set;
1200                 }
1201
1202                 /*
1203                  * Check if the Host Controller supports Programmable Clock
1204                  * Mode.
1205                  */
1206                 if (host->clk_mul) {
1207                         for (div = 1; div <= 1024; div++) {
1208                                 if ((host->max_clk * host->clk_mul / div)
1209                                         <= clock)
1210                                         break;
1211                         }
1212                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1213                                 /*
1214                                  * Set Programmable Clock Mode in the Clock
1215                                  * Control register.
1216                                  */
1217                                 clk = SDHCI_PROG_CLOCK_MODE;
1218                                 real_div = div;
1219                                 clk_mul = host->clk_mul;
1220                                 div--;
1221                         } else {
1222                                 /*
1223                                  * Divisor can be too small to reach clock
1224                                  * speed requirement. Then use the base clock.
1225                                  */
1226                                 switch_base_clk = true;
1227                         }
1228                 }
1229
1230                 if (!host->clk_mul || switch_base_clk) {
1231                         /* Version 3.00 divisors must be a multiple of 2. */
1232                         if (host->max_clk <= clock)
1233                                 div = 1;
1234                         else {
1235                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1236                                      div += 2) {
1237                                         if ((host->max_clk / div) <= clock)
1238                                                 break;
1239                                 }
1240                         }
1241                         real_div = div;
1242                         div >>= 1;
1243                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1244                                 && !div && host->max_clk <= 25000000)
1245                                 div = 1;
1246                 }
1247         } else {
1248                 /* Version 2.00 divisors must be a power of 2. */
1249                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1250                         if ((host->max_clk / div) <= clock)
1251                                 break;
1252                 }
1253                 real_div = div;
1254                 div >>= 1;
1255         }
1256
1257 clock_set:
1258         if (real_div)
1259                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1260         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1261         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1262                 << SDHCI_DIVIDER_HI_SHIFT;
1263         clk |= SDHCI_CLOCK_INT_EN;
1264         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1265
1266         /* Wait max 20 ms */
1267         timeout = 20;
1268         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1269                 & SDHCI_CLOCK_INT_STABLE)) {
1270                 if (timeout == 0) {
1271                         pr_err("%s: Internal clock never "
1272                                 "stabilised.\n", mmc_hostname(host->mmc));
1273                         sdhci_dumpregs(host);
1274                         return;
1275                 }
1276                 timeout--;
1277                 mdelay(1);
1278         }
1279
1280         clk |= SDHCI_CLOCK_CARD_EN;
1281         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1282 }
1283 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1284
1285 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1286                             unsigned short vdd)
1287 {
1288         struct mmc_host *mmc = host->mmc;
1289         u8 pwr = 0;
1290
1291         if (!IS_ERR(mmc->supply.vmmc)) {
1292                 spin_unlock_irq(&host->lock);
1293                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1294                 spin_lock_irq(&host->lock);
1295
1296                 if (mode != MMC_POWER_OFF)
1297                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1298                 else
1299                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1300
1301                 return;
1302         }
1303
1304         if (mode != MMC_POWER_OFF) {
1305                 switch (1 << vdd) {
1306                 case MMC_VDD_165_195:
1307                         pwr = SDHCI_POWER_180;
1308                         break;
1309                 case MMC_VDD_29_30:
1310                 case MMC_VDD_30_31:
1311                         pwr = SDHCI_POWER_300;
1312                         break;
1313                 case MMC_VDD_32_33:
1314                 case MMC_VDD_33_34:
1315                         pwr = SDHCI_POWER_330;
1316                         break;
1317                 default:
1318                         WARN(1, "%s: Invalid vdd %#x\n",
1319                              mmc_hostname(host->mmc), vdd);
1320                         break;
1321                 }
1322         }
1323
1324         if (host->pwr == pwr)
1325                 return;
1326
1327         host->pwr = pwr;
1328
1329         if (pwr == 0) {
1330                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1331                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1332                         sdhci_runtime_pm_bus_off(host);
1333                 vdd = 0;
1334         } else {
1335                 /*
1336                  * Spec says that we should clear the power reg before setting
1337                  * a new value. Some controllers don't seem to like this though.
1338                  */
1339                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1340                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1341
1342                 /*
1343                  * At least the Marvell CaFe chip gets confused if we set the
1344                  * voltage and set turn on power at the same time, so set the
1345                  * voltage first.
1346                  */
1347                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1348                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1349
1350                 pwr |= SDHCI_POWER_ON;
1351
1352                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1353
1354                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1355                         sdhci_runtime_pm_bus_on(host);
1356
1357                 /*
1358                  * Some controllers need an extra 10ms delay of 10ms before
1359                  * they can apply clock after applying power
1360                  */
1361                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1362                         mdelay(10);
1363         }
1364 }
1365
1366 /*****************************************************************************\
1367  *                                                                           *
1368  * MMC callbacks                                                             *
1369  *                                                                           *
1370 \*****************************************************************************/
1371
1372 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1373 {
1374         struct sdhci_host *host;
1375         int present;
1376         unsigned long flags;
1377
1378         host = mmc_priv(mmc);
1379
1380         sdhci_runtime_pm_get(host);
1381
1382         /* Firstly check card presence */
1383         present = mmc->ops->get_cd(mmc);
1384
1385         spin_lock_irqsave(&host->lock, flags);
1386
1387         WARN_ON(host->mrq != NULL);
1388
1389 #ifndef SDHCI_USE_LEDS_CLASS
1390         sdhci_activate_led(host);
1391 #endif
1392
1393         /*
1394          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1395          * requests if Auto-CMD12 is enabled.
1396          */
1397         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1398                 if (mrq->stop) {
1399                         mrq->data->stop = NULL;
1400                         mrq->stop = NULL;
1401                 }
1402         }
1403
1404         host->mrq = mrq;
1405
1406         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1407                 host->mrq->cmd->error = -ENOMEDIUM;
1408                 tasklet_schedule(&host->finish_tasklet);
1409         } else {
1410                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1411                         sdhci_send_command(host, mrq->sbc);
1412                 else
1413                         sdhci_send_command(host, mrq->cmd);
1414         }
1415
1416         mmiowb();
1417         spin_unlock_irqrestore(&host->lock, flags);
1418 }
1419
1420 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1421 {
1422         u8 ctrl;
1423
1424         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1425         if (width == MMC_BUS_WIDTH_8) {
1426                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1427                 if (host->version >= SDHCI_SPEC_300)
1428                         ctrl |= SDHCI_CTRL_8BITBUS;
1429         } else {
1430                 if (host->version >= SDHCI_SPEC_300)
1431                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1432                 if (width == MMC_BUS_WIDTH_4)
1433                         ctrl |= SDHCI_CTRL_4BITBUS;
1434                 else
1435                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1436         }
1437         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1438 }
1439 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1440
1441 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1442 {
1443         u16 ctrl_2;
1444
1445         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1446         /* Select Bus Speed Mode for host */
1447         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1448         if ((timing == MMC_TIMING_MMC_HS200) ||
1449             (timing == MMC_TIMING_UHS_SDR104))
1450                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1451         else if (timing == MMC_TIMING_UHS_SDR12)
1452                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1453         else if (timing == MMC_TIMING_UHS_SDR25)
1454                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1455         else if (timing == MMC_TIMING_UHS_SDR50)
1456                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1457         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1458                  (timing == MMC_TIMING_MMC_DDR52))
1459                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1460         else if (timing == MMC_TIMING_MMC_HS400)
1461                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1462         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1463 }
1464 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1465
1466 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1467 {
1468         unsigned long flags;
1469         u8 ctrl;
1470         struct mmc_host *mmc = host->mmc;
1471
1472         spin_lock_irqsave(&host->lock, flags);
1473
1474         if (host->flags & SDHCI_DEVICE_DEAD) {
1475                 spin_unlock_irqrestore(&host->lock, flags);
1476                 if (!IS_ERR(mmc->supply.vmmc) &&
1477                     ios->power_mode == MMC_POWER_OFF)
1478                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1479                 return;
1480         }
1481
1482         /*
1483          * Reset the chip on each power off.
1484          * Should clear out any weird states.
1485          */
1486         if (ios->power_mode == MMC_POWER_OFF) {
1487                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1488                 sdhci_reinit(host);
1489         }
1490
1491         if (host->version >= SDHCI_SPEC_300 &&
1492                 (ios->power_mode == MMC_POWER_UP) &&
1493                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1494                 sdhci_enable_preset_value(host, false);
1495
1496         if (!ios->clock || ios->clock != host->clock) {
1497                 host->ops->set_clock(host, ios->clock);
1498                 host->clock = ios->clock;
1499
1500                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1501                     host->clock) {
1502                         host->timeout_clk = host->mmc->actual_clock ?
1503                                                 host->mmc->actual_clock / 1000 :
1504                                                 host->clock / 1000;
1505                         host->mmc->max_busy_timeout =
1506                                 host->ops->get_max_timeout_count ?
1507                                 host->ops->get_max_timeout_count(host) :
1508                                 1 << 27;
1509                         host->mmc->max_busy_timeout /= host->timeout_clk;
1510                 }
1511         }
1512
1513         sdhci_set_power(host, ios->power_mode, ios->vdd);
1514
1515         if (host->ops->platform_send_init_74_clocks)
1516                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1517
1518         host->ops->set_bus_width(host, ios->bus_width);
1519
1520         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1521
1522         if ((ios->timing == MMC_TIMING_SD_HS ||
1523              ios->timing == MMC_TIMING_MMC_HS)
1524             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1525                 ctrl |= SDHCI_CTRL_HISPD;
1526         else
1527                 ctrl &= ~SDHCI_CTRL_HISPD;
1528
1529         if (host->version >= SDHCI_SPEC_300) {
1530                 u16 clk, ctrl_2;
1531
1532                 /* In case of UHS-I modes, set High Speed Enable */
1533                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1534                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1535                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1536                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1537                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1538                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1539                     (ios->timing == MMC_TIMING_UHS_SDR25))
1540                         ctrl |= SDHCI_CTRL_HISPD;
1541
1542                 if (!host->preset_enabled) {
1543                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1544                         /*
1545                          * We only need to set Driver Strength if the
1546                          * preset value enable is not set.
1547                          */
1548                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1549                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1550                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1551                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1552                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1553                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1554                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1555                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1556                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1557                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1558                         else {
1559                                 pr_warn("%s: invalid driver type, default to "
1560                                         "driver type B\n", mmc_hostname(mmc));
1561                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1562                         }
1563
1564                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1565                 } else {
1566                         /*
1567                          * According to SDHC Spec v3.00, if the Preset Value
1568                          * Enable in the Host Control 2 register is set, we
1569                          * need to reset SD Clock Enable before changing High
1570                          * Speed Enable to avoid generating clock gliches.
1571                          */
1572
1573                         /* Reset SD Clock Enable */
1574                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1575                         clk &= ~SDHCI_CLOCK_CARD_EN;
1576                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1577
1578                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1579
1580                         /* Re-enable SD Clock */
1581                         host->ops->set_clock(host, host->clock);
1582                 }
1583
1584                 /* Reset SD Clock Enable */
1585                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1586                 clk &= ~SDHCI_CLOCK_CARD_EN;
1587                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1588
1589                 host->ops->set_uhs_signaling(host, ios->timing);
1590                 host->timing = ios->timing;
1591
1592                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1593                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1594                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1595                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1596                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1597                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1598                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1599                         u16 preset;
1600
1601                         sdhci_enable_preset_value(host, true);
1602                         preset = sdhci_get_preset_value(host);
1603                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1604                                 >> SDHCI_PRESET_DRV_SHIFT;
1605                 }
1606
1607                 /* Re-enable SD Clock */
1608                 host->ops->set_clock(host, host->clock);
1609         } else
1610                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1611
1612         /*
1613          * Some (ENE) controllers go apeshit on some ios operation,
1614          * signalling timeout and CRC errors even on CMD0. Resetting
1615          * it on each ios seems to solve the problem.
1616          */
1617         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1618                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1619
1620         mmiowb();
1621         spin_unlock_irqrestore(&host->lock, flags);
1622 }
1623
1624 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1625 {
1626         struct sdhci_host *host = mmc_priv(mmc);
1627
1628         sdhci_runtime_pm_get(host);
1629         sdhci_do_set_ios(host, ios);
1630         sdhci_runtime_pm_put(host);
1631 }
1632
1633 static int sdhci_do_get_cd(struct sdhci_host *host)
1634 {
1635         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1636
1637         if (host->flags & SDHCI_DEVICE_DEAD)
1638                 return 0;
1639
1640         /* If nonremovable, assume that the card is always present. */
1641         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1642                 return 1;
1643
1644         /*
1645          * Try slot gpio detect, if defined it take precedence
1646          * over build in controller functionality
1647          */
1648         if (!IS_ERR_VALUE(gpio_cd))
1649                 return !!gpio_cd;
1650
1651         /* If polling, assume that the card is always present. */
1652         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1653                 return 1;
1654
1655         /* Host native card detect */
1656         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1657 }
1658
1659 static int sdhci_get_cd(struct mmc_host *mmc)
1660 {
1661         struct sdhci_host *host = mmc_priv(mmc);
1662         int ret;
1663
1664         sdhci_runtime_pm_get(host);
1665         ret = sdhci_do_get_cd(host);
1666         sdhci_runtime_pm_put(host);
1667         return ret;
1668 }
1669
1670 static int sdhci_check_ro(struct sdhci_host *host)
1671 {
1672         unsigned long flags;
1673         int is_readonly;
1674
1675         spin_lock_irqsave(&host->lock, flags);
1676
1677         if (host->flags & SDHCI_DEVICE_DEAD)
1678                 is_readonly = 0;
1679         else if (host->ops->get_ro)
1680                 is_readonly = host->ops->get_ro(host);
1681         else
1682                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1683                                 & SDHCI_WRITE_PROTECT);
1684
1685         spin_unlock_irqrestore(&host->lock, flags);
1686
1687         /* This quirk needs to be replaced by a callback-function later */
1688         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1689                 !is_readonly : is_readonly;
1690 }
1691
1692 #define SAMPLE_COUNT    5
1693
1694 static int sdhci_do_get_ro(struct sdhci_host *host)
1695 {
1696         int i, ro_count;
1697
1698         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1699                 return sdhci_check_ro(host);
1700
1701         ro_count = 0;
1702         for (i = 0; i < SAMPLE_COUNT; i++) {
1703                 if (sdhci_check_ro(host)) {
1704                         if (++ro_count > SAMPLE_COUNT / 2)
1705                                 return 1;
1706                 }
1707                 msleep(30);
1708         }
1709         return 0;
1710 }
1711
1712 static void sdhci_hw_reset(struct mmc_host *mmc)
1713 {
1714         struct sdhci_host *host = mmc_priv(mmc);
1715
1716         if (host->ops && host->ops->hw_reset)
1717                 host->ops->hw_reset(host);
1718 }
1719
1720 static int sdhci_get_ro(struct mmc_host *mmc)
1721 {
1722         struct sdhci_host *host = mmc_priv(mmc);
1723         int ret;
1724
1725         sdhci_runtime_pm_get(host);
1726         ret = sdhci_do_get_ro(host);
1727         sdhci_runtime_pm_put(host);
1728         return ret;
1729 }
1730
1731 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1732 {
1733         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1734                 if (enable)
1735                         host->ier |= SDHCI_INT_CARD_INT;
1736                 else
1737                         host->ier &= ~SDHCI_INT_CARD_INT;
1738
1739                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1740                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1741                 mmiowb();
1742         }
1743 }
1744
1745 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1746 {
1747         struct sdhci_host *host = mmc_priv(mmc);
1748         unsigned long flags;
1749
1750         sdhci_runtime_pm_get(host);
1751
1752         spin_lock_irqsave(&host->lock, flags);
1753         if (enable)
1754                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1755         else
1756                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1757
1758         sdhci_enable_sdio_irq_nolock(host, enable);
1759         spin_unlock_irqrestore(&host->lock, flags);
1760
1761         sdhci_runtime_pm_put(host);
1762 }
1763
1764 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1765                                                 struct mmc_ios *ios)
1766 {
1767         struct mmc_host *mmc = host->mmc;
1768         u16 ctrl;
1769         int ret;
1770
1771         /*
1772          * Signal Voltage Switching is only applicable for Host Controllers
1773          * v3.00 and above.
1774          */
1775         if (host->version < SDHCI_SPEC_300)
1776                 return 0;
1777
1778         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1779
1780         switch (ios->signal_voltage) {
1781         case MMC_SIGNAL_VOLTAGE_330:
1782                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1783                 ctrl &= ~SDHCI_CTRL_VDD_180;
1784                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1785
1786                 if (!IS_ERR(mmc->supply.vqmmc)) {
1787                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1788                                                     3600000);
1789                         if (ret) {
1790                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1791                                         mmc_hostname(mmc));
1792                                 return -EIO;
1793                         }
1794                 }
1795                 /* Wait for 5ms */
1796                 usleep_range(5000, 5500);
1797
1798                 /* 3.3V regulator output should be stable within 5 ms */
1799                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1800                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1801                         return 0;
1802
1803                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1804                         mmc_hostname(mmc));
1805
1806                 return -EAGAIN;
1807         case MMC_SIGNAL_VOLTAGE_180:
1808                 if (!IS_ERR(mmc->supply.vqmmc)) {
1809                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1810                                         1700000, 1950000);
1811                         if (ret) {
1812                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1813                                         mmc_hostname(mmc));
1814                                 return -EIO;
1815                         }
1816                 }
1817
1818                 /*
1819                  * Enable 1.8V Signal Enable in the Host Control2
1820                  * register
1821                  */
1822                 ctrl |= SDHCI_CTRL_VDD_180;
1823                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1824
1825                 /* Some controller need to do more when switching */
1826                 if (host->ops->voltage_switch)
1827                         host->ops->voltage_switch(host);
1828
1829                 /* 1.8V regulator output should be stable within 5 ms */
1830                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1831                 if (ctrl & SDHCI_CTRL_VDD_180)
1832                         return 0;
1833
1834                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1835                         mmc_hostname(mmc));
1836
1837                 return -EAGAIN;
1838         case MMC_SIGNAL_VOLTAGE_120:
1839                 if (!IS_ERR(mmc->supply.vqmmc)) {
1840                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1841                                                     1300000);
1842                         if (ret) {
1843                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1844                                         mmc_hostname(mmc));
1845                                 return -EIO;
1846                         }
1847                 }
1848                 return 0;
1849         default:
1850                 /* No signal voltage switch required */
1851                 return 0;
1852         }
1853 }
1854
1855 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1856         struct mmc_ios *ios)
1857 {
1858         struct sdhci_host *host = mmc_priv(mmc);
1859         int err;
1860
1861         if (host->version < SDHCI_SPEC_300)
1862                 return 0;
1863         sdhci_runtime_pm_get(host);
1864         err = sdhci_do_start_signal_voltage_switch(host, ios);
1865         sdhci_runtime_pm_put(host);
1866         return err;
1867 }
1868
1869 static int sdhci_card_busy(struct mmc_host *mmc)
1870 {
1871         struct sdhci_host *host = mmc_priv(mmc);
1872         u32 present_state;
1873
1874         sdhci_runtime_pm_get(host);
1875         /* Check whether DAT[0] is 0 */
1876         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1877         sdhci_runtime_pm_put(host);
1878
1879         return !(present_state & SDHCI_DATA_0_LVL_MASK);
1880 }
1881
1882 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1883 {
1884         struct sdhci_host *host = mmc_priv(mmc);
1885         unsigned long flags;
1886
1887         spin_lock_irqsave(&host->lock, flags);
1888         host->flags |= SDHCI_HS400_TUNING;
1889         spin_unlock_irqrestore(&host->lock, flags);
1890
1891         return 0;
1892 }
1893
1894 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1895 {
1896         struct sdhci_host *host = mmc_priv(mmc);
1897         u16 ctrl;
1898         int tuning_loop_counter = MAX_TUNING_LOOP;
1899         int err = 0;
1900         unsigned long flags;
1901         unsigned int tuning_count = 0;
1902         bool hs400_tuning;
1903
1904         sdhci_runtime_pm_get(host);
1905         spin_lock_irqsave(&host->lock, flags);
1906
1907         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1908         host->flags &= ~SDHCI_HS400_TUNING;
1909
1910         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1911                 tuning_count = host->tuning_count;
1912
1913         /*
1914          * The Host Controller needs tuning in case of SDR104 and DDR50
1915          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1916          * the Capabilities register.
1917          * If the Host Controller supports the HS200 mode then the
1918          * tuning function has to be executed.
1919          */
1920         switch (host->timing) {
1921         /* HS400 tuning is done in HS200 mode */
1922         case MMC_TIMING_MMC_HS400:
1923                 err = -EINVAL;
1924                 goto out_unlock;
1925
1926         case MMC_TIMING_MMC_HS200:
1927                 /*
1928                  * Periodic re-tuning for HS400 is not expected to be needed, so
1929                  * disable it here.
1930                  */
1931                 if (hs400_tuning)
1932                         tuning_count = 0;
1933                 break;
1934
1935         case MMC_TIMING_UHS_SDR104:
1936         case MMC_TIMING_UHS_DDR50:
1937                 break;
1938
1939         case MMC_TIMING_UHS_SDR50:
1940                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1941                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1942                         break;
1943                 /* FALLTHROUGH */
1944
1945         default:
1946                 goto out_unlock;
1947         }
1948
1949         if (host->ops->platform_execute_tuning) {
1950                 spin_unlock_irqrestore(&host->lock, flags);
1951                 err = host->ops->platform_execute_tuning(host, opcode);
1952                 sdhci_runtime_pm_put(host);
1953                 return err;
1954         }
1955
1956         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1957         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1958         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1959                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1960         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1961
1962         /*
1963          * As per the Host Controller spec v3.00, tuning command
1964          * generates Buffer Read Ready interrupt, so enable that.
1965          *
1966          * Note: The spec clearly says that when tuning sequence
1967          * is being performed, the controller does not generate
1968          * interrupts other than Buffer Read Ready interrupt. But
1969          * to make sure we don't hit a controller bug, we _only_
1970          * enable Buffer Read Ready interrupt here.
1971          */
1972         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1973         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1974
1975         /*
1976          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1977          * of loops reaches 40 times or a timeout of 150ms occurs.
1978          */
1979         do {
1980                 struct mmc_command cmd = {0};
1981                 struct mmc_request mrq = {NULL};
1982
1983                 cmd.opcode = opcode;
1984                 cmd.arg = 0;
1985                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1986                 cmd.retries = 0;
1987                 cmd.data = NULL;
1988                 cmd.error = 0;
1989
1990                 if (tuning_loop_counter-- == 0)
1991                         break;
1992
1993                 mrq.cmd = &cmd;
1994                 host->mrq = &mrq;
1995
1996                 /*
1997                  * In response to CMD19, the card sends 64 bytes of tuning
1998                  * block to the Host Controller. So we set the block size
1999                  * to 64 here.
2000                  */
2001                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2002                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2003                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2004                                              SDHCI_BLOCK_SIZE);
2005                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2006                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2007                                              SDHCI_BLOCK_SIZE);
2008                 } else {
2009                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2010                                      SDHCI_BLOCK_SIZE);
2011                 }
2012
2013                 /*
2014                  * The tuning block is sent by the card to the host controller.
2015                  * So we set the TRNS_READ bit in the Transfer Mode register.
2016                  * This also takes care of setting DMA Enable and Multi Block
2017                  * Select in the same register to 0.
2018                  */
2019                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2020
2021                 sdhci_send_command(host, &cmd);
2022
2023                 host->cmd = NULL;
2024                 host->mrq = NULL;
2025
2026                 spin_unlock_irqrestore(&host->lock, flags);
2027                 /* Wait for Buffer Read Ready interrupt */
2028                 wait_event_timeout(host->buf_ready_int,
2029                                    (host->tuning_done == 1),
2030                                    msecs_to_jiffies(50));
2031                 spin_lock_irqsave(&host->lock, flags);
2032
2033                 if (!host->tuning_done) {
2034                         pr_info(DRIVER_NAME ": Timeout waiting for "
2035                                 "Buffer Read Ready interrupt during tuning "
2036                                 "procedure, falling back to fixed sampling "
2037                                 "clock\n");
2038                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2039                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2040                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2041                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2042
2043                         sdhci_do_reset(host, SDHCI_RESET_CMD);
2044                         sdhci_do_reset(host, SDHCI_RESET_DATA);
2045
2046                         err = -EIO;
2047
2048                         if (cmd.opcode != MMC_SEND_TUNING_BLOCK_HS200)
2049                                 goto out;
2050
2051                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2052                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2053
2054                         spin_unlock_irqrestore(&host->lock, flags);
2055
2056                         memset(&cmd, 0, sizeof(cmd));
2057                         cmd.opcode = MMC_STOP_TRANSMISSION;
2058                         cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
2059                         cmd.busy_timeout = 50;
2060                         mmc_wait_for_cmd(mmc, &cmd, 0);
2061
2062                         spin_lock_irqsave(&host->lock, flags);
2063
2064                         goto out;
2065                 }
2066
2067                 host->tuning_done = 0;
2068
2069                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2070
2071                 /* eMMC spec does not require a delay between tuning cycles */
2072                 if (opcode == MMC_SEND_TUNING_BLOCK)
2073                         mdelay(1);
2074         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2075
2076         /*
2077          * The Host Driver has exhausted the maximum number of loops allowed,
2078          * so use fixed sampling frequency.
2079          */
2080         if (tuning_loop_counter < 0) {
2081                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2082                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2083         }
2084         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2085                 pr_info(DRIVER_NAME ": Tuning procedure"
2086                         " failed, falling back to fixed sampling"
2087                         " clock\n");
2088                 err = -EIO;
2089         }
2090
2091 out:
2092         if (tuning_count) {
2093                 /*
2094                  * In case tuning fails, host controllers which support
2095                  * re-tuning can try tuning again at a later time, when the
2096                  * re-tuning timer expires.  So for these controllers, we
2097                  * return 0. Since there might be other controllers who do not
2098                  * have this capability, we return error for them.
2099                  */
2100                 err = 0;
2101         }
2102
2103         host->mmc->retune_period = err ? 0 : tuning_count;
2104
2105         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2106         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2107 out_unlock:
2108         spin_unlock_irqrestore(&host->lock, flags);
2109         sdhci_runtime_pm_put(host);
2110
2111         return err;
2112 }
2113
2114 static int sdhci_select_drive_strength(struct mmc_card *card,
2115                                        unsigned int max_dtr, int host_drv,
2116                                        int card_drv, int *drv_type)
2117 {
2118         struct sdhci_host *host = mmc_priv(card->host);
2119
2120         if (!host->ops->select_drive_strength)
2121                 return 0;
2122
2123         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2124                                                 card_drv, drv_type);
2125 }
2126
2127 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2128 {
2129         /* Host Controller v3.00 defines preset value registers */
2130         if (host->version < SDHCI_SPEC_300)
2131                 return;
2132
2133         /*
2134          * We only enable or disable Preset Value if they are not already
2135          * enabled or disabled respectively. Otherwise, we bail out.
2136          */
2137         if (host->preset_enabled != enable) {
2138                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2139
2140                 if (enable)
2141                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2142                 else
2143                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2144
2145                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2146
2147                 if (enable)
2148                         host->flags |= SDHCI_PV_ENABLED;
2149                 else
2150                         host->flags &= ~SDHCI_PV_ENABLED;
2151
2152                 host->preset_enabled = enable;
2153         }
2154 }
2155
2156 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2157                                 int err)
2158 {
2159         struct sdhci_host *host = mmc_priv(mmc);
2160         struct mmc_data *data = mrq->data;
2161
2162         if (host->flags & SDHCI_REQ_USE_DMA) {
2163                 if (data->host_cookie == COOKIE_GIVEN ||
2164                                 data->host_cookie == COOKIE_MAPPED)
2165                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2166                                          data->flags & MMC_DATA_WRITE ?
2167                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2168                 data->host_cookie = COOKIE_UNMAPPED;
2169         }
2170 }
2171
2172 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2173                                        struct mmc_data *data)
2174 {
2175         int sg_count;
2176
2177         if (data->host_cookie == COOKIE_MAPPED) {
2178                 data->host_cookie = COOKIE_GIVEN;
2179                 return data->sg_count;
2180         }
2181
2182         WARN_ON(data->host_cookie == COOKIE_GIVEN);
2183
2184         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2185                                 data->flags & MMC_DATA_WRITE ?
2186                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2187
2188         if (sg_count == 0)
2189                 return -ENOSPC;
2190
2191         data->sg_count = sg_count;
2192         data->host_cookie = COOKIE_MAPPED;
2193
2194         return sg_count;
2195 }
2196
2197 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2198                                bool is_first_req)
2199 {
2200         struct sdhci_host *host = mmc_priv(mmc);
2201
2202         mrq->data->host_cookie = COOKIE_UNMAPPED;
2203
2204         if (host->flags & SDHCI_REQ_USE_DMA)
2205                 sdhci_pre_dma_transfer(host, mrq->data);
2206 }
2207
2208 static void sdhci_card_event(struct mmc_host *mmc)
2209 {
2210         struct sdhci_host *host = mmc_priv(mmc);
2211         unsigned long flags;
2212         int present;
2213
2214         /* First check if client has provided their own card event */
2215         if (host->ops->card_event)
2216                 host->ops->card_event(host);
2217
2218         present = sdhci_do_get_cd(host);
2219
2220         spin_lock_irqsave(&host->lock, flags);
2221
2222         /* Check host->mrq first in case we are runtime suspended */
2223         if (host->mrq && !present) {
2224                 pr_err("%s: Card removed during transfer!\n",
2225                         mmc_hostname(host->mmc));
2226                 pr_err("%s: Resetting controller.\n",
2227                         mmc_hostname(host->mmc));
2228
2229                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2230                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2231
2232                 host->mrq->cmd->error = -ENOMEDIUM;
2233                 tasklet_schedule(&host->finish_tasklet);
2234         }
2235
2236         spin_unlock_irqrestore(&host->lock, flags);
2237 }
2238
2239 static const struct mmc_host_ops sdhci_ops = {
2240         .request        = sdhci_request,
2241         .post_req       = sdhci_post_req,
2242         .pre_req        = sdhci_pre_req,
2243         .set_ios        = sdhci_set_ios,
2244         .get_cd         = sdhci_get_cd,
2245         .get_ro         = sdhci_get_ro,
2246         .hw_reset       = sdhci_hw_reset,
2247         .enable_sdio_irq = sdhci_enable_sdio_irq,
2248         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2249         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2250         .execute_tuning                 = sdhci_execute_tuning,
2251         .select_drive_strength          = sdhci_select_drive_strength,
2252         .card_event                     = sdhci_card_event,
2253         .card_busy      = sdhci_card_busy,
2254 };
2255
2256 /*****************************************************************************\
2257  *                                                                           *
2258  * Tasklets                                                                  *
2259  *                                                                           *
2260 \*****************************************************************************/
2261
2262 static void sdhci_tasklet_finish(unsigned long param)
2263 {
2264         struct sdhci_host *host;
2265         unsigned long flags;
2266         struct mmc_request *mrq;
2267
2268         host = (struct sdhci_host*)param;
2269
2270         spin_lock_irqsave(&host->lock, flags);
2271
2272         /*
2273          * If this tasklet gets rescheduled while running, it will
2274          * be run again afterwards but without any active request.
2275          */
2276         if (!host->mrq) {
2277                 spin_unlock_irqrestore(&host->lock, flags);
2278                 return;
2279         }
2280
2281         del_timer(&host->timer);
2282
2283         mrq = host->mrq;
2284
2285         /*
2286          * The controller needs a reset of internal state machines
2287          * upon error conditions.
2288          */
2289         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2290             ((mrq->cmd && mrq->cmd->error) ||
2291              (mrq->sbc && mrq->sbc->error) ||
2292              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2293                             (mrq->data->stop && mrq->data->stop->error))) ||
2294              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2295
2296                 /* Some controllers need this kick or reset won't work here */
2297                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2298                         /* This is to force an update */
2299                         host->ops->set_clock(host, host->clock);
2300
2301                 /* Spec says we should do both at the same time, but Ricoh
2302                    controllers do not like that. */
2303                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2304                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2305         }
2306
2307         host->mrq = NULL;
2308         host->cmd = NULL;
2309         host->data = NULL;
2310
2311 #ifndef SDHCI_USE_LEDS_CLASS
2312         sdhci_deactivate_led(host);
2313 #endif
2314
2315         mmiowb();
2316         spin_unlock_irqrestore(&host->lock, flags);
2317
2318         mmc_request_done(host->mmc, mrq);
2319         sdhci_runtime_pm_put(host);
2320 }
2321
2322 static void sdhci_timeout_timer(unsigned long data)
2323 {
2324         struct sdhci_host *host;
2325         unsigned long flags;
2326
2327         host = (struct sdhci_host*)data;
2328
2329         spin_lock_irqsave(&host->lock, flags);
2330
2331         if (host->mrq) {
2332                 pr_err("%s: Timeout waiting for hardware "
2333                         "interrupt.\n", mmc_hostname(host->mmc));
2334                 sdhci_dumpregs(host);
2335
2336                 if (host->data) {
2337                         host->data->error = -ETIMEDOUT;
2338                         sdhci_finish_data(host);
2339                 } else {
2340                         if (host->cmd)
2341                                 host->cmd->error = -ETIMEDOUT;
2342                         else
2343                                 host->mrq->cmd->error = -ETIMEDOUT;
2344
2345                         tasklet_schedule(&host->finish_tasklet);
2346                 }
2347         }
2348
2349         mmiowb();
2350         spin_unlock_irqrestore(&host->lock, flags);
2351 }
2352
2353 /*****************************************************************************\
2354  *                                                                           *
2355  * Interrupt handling                                                        *
2356  *                                                                           *
2357 \*****************************************************************************/
2358
2359 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2360 {
2361         BUG_ON(intmask == 0);
2362
2363         if (!host->cmd) {
2364                 pr_err("%s: Got command interrupt 0x%08x even "
2365                         "though no command operation was in progress.\n",
2366                         mmc_hostname(host->mmc), (unsigned)intmask);
2367                 sdhci_dumpregs(host);
2368                 return;
2369         }
2370
2371         if (intmask & SDHCI_INT_TIMEOUT)
2372                 host->cmd->error = -ETIMEDOUT;
2373         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2374                         SDHCI_INT_INDEX))
2375                 host->cmd->error = -EILSEQ;
2376
2377         if (host->cmd->error) {
2378                 tasklet_schedule(&host->finish_tasklet);
2379                 return;
2380         }
2381
2382         /*
2383          * The host can send and interrupt when the busy state has
2384          * ended, allowing us to wait without wasting CPU cycles.
2385          * Unfortunately this is overloaded on the "data complete"
2386          * interrupt, so we need to take some care when handling
2387          * it.
2388          *
2389          * Note: The 1.0 specification is a bit ambiguous about this
2390          *       feature so there might be some problems with older
2391          *       controllers.
2392          */
2393         if (host->cmd->flags & MMC_RSP_BUSY) {
2394                 if (host->cmd->data)
2395                         DBG("Cannot wait for busy signal when also "
2396                                 "doing a data transfer");
2397                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2398                                 && !host->busy_handle) {
2399                         /* Mark that command complete before busy is ended */
2400                         host->busy_handle = 1;
2401                         return;
2402                 }
2403
2404                 /* The controller does not support the end-of-busy IRQ,
2405                  * fall through and take the SDHCI_INT_RESPONSE */
2406         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2407                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2408                 *mask &= ~SDHCI_INT_DATA_END;
2409         }
2410
2411         if (intmask & SDHCI_INT_RESPONSE)
2412                 sdhci_finish_command(host);
2413 }
2414
2415 #ifdef CONFIG_MMC_DEBUG
2416 static void sdhci_adma_show_error(struct sdhci_host *host)
2417 {
2418         const char *name = mmc_hostname(host->mmc);
2419         void *desc = host->adma_table;
2420
2421         sdhci_dumpregs(host);
2422
2423         while (true) {
2424                 struct sdhci_adma2_64_desc *dma_desc = desc;
2425
2426                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2427                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2428                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2429                             le32_to_cpu(dma_desc->addr_lo),
2430                             le16_to_cpu(dma_desc->len),
2431                             le16_to_cpu(dma_desc->cmd));
2432                 else
2433                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2434                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2435                             le16_to_cpu(dma_desc->len),
2436                             le16_to_cpu(dma_desc->cmd));
2437
2438                 desc += host->desc_sz;
2439
2440                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2441                         break;
2442         }
2443 }
2444 #else
2445 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2446 #endif
2447
2448 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2449 {
2450         u32 command;
2451         BUG_ON(intmask == 0);
2452
2453         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2454         if (intmask & SDHCI_INT_DATA_AVAIL) {
2455                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2456                 if (command == MMC_SEND_TUNING_BLOCK ||
2457                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2458                         host->tuning_done = 1;
2459                         wake_up(&host->buf_ready_int);
2460                         return;
2461                 }
2462         }
2463
2464         if (!host->data) {
2465                 /*
2466                  * The "data complete" interrupt is also used to
2467                  * indicate that a busy state has ended. See comment
2468                  * above in sdhci_cmd_irq().
2469                  */
2470                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2471                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2472                                 host->cmd->error = -ETIMEDOUT;
2473                                 tasklet_schedule(&host->finish_tasklet);
2474                                 return;
2475                         }
2476                         if (intmask & SDHCI_INT_DATA_END) {
2477                                 /*
2478                                  * Some cards handle busy-end interrupt
2479                                  * before the command completed, so make
2480                                  * sure we do things in the proper order.
2481                                  */
2482                                 if (host->busy_handle)
2483                                         sdhci_finish_command(host);
2484                                 else
2485                                         host->busy_handle = 1;
2486                                 return;
2487                         }
2488                 }
2489
2490                 pr_err("%s: Got data interrupt 0x%08x even "
2491                         "though no data operation was in progress.\n",
2492                         mmc_hostname(host->mmc), (unsigned)intmask);
2493                 sdhci_dumpregs(host);
2494
2495                 return;
2496         }
2497
2498         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2499                 host->data->error = -ETIMEDOUT;
2500         else if (intmask & SDHCI_INT_DATA_END_BIT)
2501                 host->data->error = -EILSEQ;
2502         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2503                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2504                         != MMC_BUS_TEST_R)
2505                 host->data->error = -EILSEQ;
2506         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2507                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2508                 sdhci_adma_show_error(host);
2509                 host->data->error = -EIO;
2510                 if (host->ops->adma_workaround)
2511                         host->ops->adma_workaround(host, intmask);
2512         }
2513
2514         if (host->data->error)
2515                 sdhci_finish_data(host);
2516         else {
2517                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2518                         sdhci_transfer_pio(host);
2519
2520                 /*
2521                  * We currently don't do anything fancy with DMA
2522                  * boundaries, but as we can't disable the feature
2523                  * we need to at least restart the transfer.
2524                  *
2525                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2526                  * should return a valid address to continue from, but as
2527                  * some controllers are faulty, don't trust them.
2528                  */
2529                 if (intmask & SDHCI_INT_DMA_END) {
2530                         u32 dmastart, dmanow;
2531                         dmastart = sg_dma_address(host->data->sg);
2532                         dmanow = dmastart + host->data->bytes_xfered;
2533                         /*
2534                          * Force update to the next DMA block boundary.
2535                          */
2536                         dmanow = (dmanow &
2537                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2538                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2539                         host->data->bytes_xfered = dmanow - dmastart;
2540                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2541                                 " next 0x%08x\n",
2542                                 mmc_hostname(host->mmc), dmastart,
2543                                 host->data->bytes_xfered, dmanow);
2544                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2545                 }
2546
2547                 if (intmask & SDHCI_INT_DATA_END) {
2548                         if (host->cmd) {
2549                                 /*
2550                                  * Data managed to finish before the
2551                                  * command completed. Make sure we do
2552                                  * things in the proper order.
2553                                  */
2554                                 host->data_early = 1;
2555                         } else {
2556                                 sdhci_finish_data(host);
2557                         }
2558                 }
2559         }
2560 }
2561
2562 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2563 {
2564         irqreturn_t result = IRQ_NONE;
2565         struct sdhci_host *host = dev_id;
2566         u32 intmask, mask, unexpected = 0;
2567         int max_loops = 16;
2568
2569         spin_lock(&host->lock);
2570
2571         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2572                 spin_unlock(&host->lock);
2573                 return IRQ_NONE;
2574         }
2575
2576         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2577         if (!intmask || intmask == 0xffffffff) {
2578                 result = IRQ_NONE;
2579                 goto out;
2580         }
2581
2582         do {
2583                 /* Clear selected interrupts. */
2584                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2585                                   SDHCI_INT_BUS_POWER);
2586                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2587
2588                 DBG("*** %s got interrupt: 0x%08x\n",
2589                         mmc_hostname(host->mmc), intmask);
2590
2591                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2592                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2593                                       SDHCI_CARD_PRESENT;
2594
2595                         /*
2596                          * There is a observation on i.mx esdhc.  INSERT
2597                          * bit will be immediately set again when it gets
2598                          * cleared, if a card is inserted.  We have to mask
2599                          * the irq to prevent interrupt storm which will
2600                          * freeze the system.  And the REMOVE gets the
2601                          * same situation.
2602                          *
2603                          * More testing are needed here to ensure it works
2604                          * for other platforms though.
2605                          */
2606                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2607                                        SDHCI_INT_CARD_REMOVE);
2608                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2609                                                SDHCI_INT_CARD_INSERT;
2610                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2611                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2612
2613                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2614                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2615
2616                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2617                                                        SDHCI_INT_CARD_REMOVE);
2618                         result = IRQ_WAKE_THREAD;
2619                 }
2620
2621                 if (intmask & SDHCI_INT_CMD_MASK)
2622                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2623                                       &intmask);
2624
2625                 if (intmask & SDHCI_INT_DATA_MASK)
2626                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2627
2628                 if (intmask & SDHCI_INT_BUS_POWER)
2629                         pr_err("%s: Card is consuming too much power!\n",
2630                                 mmc_hostname(host->mmc));
2631
2632                 if ((intmask & SDHCI_INT_CARD_INT) &&
2633                     (host->ier & SDHCI_INT_CARD_INT)) {
2634                         sdhci_enable_sdio_irq_nolock(host, false);
2635                         host->thread_isr |= SDHCI_INT_CARD_INT;
2636                         result = IRQ_WAKE_THREAD;
2637                 }
2638
2639                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2640                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2641                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2642                              SDHCI_INT_CARD_INT);
2643
2644                 if (intmask) {
2645                         unexpected |= intmask;
2646                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2647                 }
2648
2649                 if (result == IRQ_NONE)
2650                         result = IRQ_HANDLED;
2651
2652                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2653         } while (intmask && --max_loops);
2654 out:
2655         spin_unlock(&host->lock);
2656
2657         if (unexpected) {
2658                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2659                            mmc_hostname(host->mmc), unexpected);
2660                 sdhci_dumpregs(host);
2661         }
2662
2663         return result;
2664 }
2665
2666 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2667 {
2668         struct sdhci_host *host = dev_id;
2669         unsigned long flags;
2670         u32 isr;
2671
2672         spin_lock_irqsave(&host->lock, flags);
2673         isr = host->thread_isr;
2674         host->thread_isr = 0;
2675         spin_unlock_irqrestore(&host->lock, flags);
2676
2677         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2678                 sdhci_card_event(host->mmc);
2679                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2680         }
2681
2682         if (isr & SDHCI_INT_CARD_INT) {
2683                 sdio_run_irqs(host->mmc);
2684
2685                 spin_lock_irqsave(&host->lock, flags);
2686                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2687                         sdhci_enable_sdio_irq_nolock(host, true);
2688                 spin_unlock_irqrestore(&host->lock, flags);
2689         }
2690
2691         return isr ? IRQ_HANDLED : IRQ_NONE;
2692 }
2693
2694 /*****************************************************************************\
2695  *                                                                           *
2696  * Suspend/resume                                                            *
2697  *                                                                           *
2698 \*****************************************************************************/
2699
2700 #ifdef CONFIG_PM
2701 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2702 {
2703         u8 val;
2704         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2705                         | SDHCI_WAKE_ON_INT;
2706
2707         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2708         val |= mask ;
2709         /* Avoid fake wake up */
2710         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2711                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2712         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2713 }
2714 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2715
2716 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2717 {
2718         u8 val;
2719         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2720                         | SDHCI_WAKE_ON_INT;
2721
2722         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2723         val &= ~mask;
2724         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2725 }
2726
2727 int sdhci_suspend_host(struct sdhci_host *host)
2728 {
2729         sdhci_disable_card_detection(host);
2730
2731         mmc_retune_timer_stop(host->mmc);
2732         mmc_retune_needed(host->mmc);
2733
2734         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2735                 host->ier = 0;
2736                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2737                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2738                 free_irq(host->irq, host);
2739         } else {
2740                 sdhci_enable_irq_wakeups(host);
2741         }
2742         return 0;
2743 }
2744
2745 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2746
2747 int sdhci_resume_host(struct sdhci_host *host)
2748 {
2749         int ret = 0;
2750
2751         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2752                 if (host->ops->enable_dma)
2753                         host->ops->enable_dma(host);
2754         }
2755
2756         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2757             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2758                 /* Card keeps power but host controller does not */
2759                 sdhci_init(host, 0);
2760                 host->pwr = 0;
2761                 host->clock = 0;
2762                 sdhci_do_set_ios(host, &host->mmc->ios);
2763         } else {
2764                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2765                 mmiowb();
2766         }
2767
2768         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2769                 ret = request_threaded_irq(host->irq, sdhci_irq,
2770                                            sdhci_thread_irq, IRQF_SHARED,
2771                                            mmc_hostname(host->mmc), host);
2772                 if (ret)
2773                         return ret;
2774         } else {
2775                 sdhci_disable_irq_wakeups(host);
2776         }
2777
2778         sdhci_enable_card_detection(host);
2779
2780         return ret;
2781 }
2782
2783 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2784
2785 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2786 {
2787         return pm_runtime_get_sync(host->mmc->parent);
2788 }
2789
2790 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2791 {
2792         pm_runtime_mark_last_busy(host->mmc->parent);
2793         return pm_runtime_put_autosuspend(host->mmc->parent);
2794 }
2795
2796 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2797 {
2798         if (host->bus_on)
2799                 return;
2800         host->bus_on = true;
2801         pm_runtime_get_noresume(host->mmc->parent);
2802 }
2803
2804 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2805 {
2806         if (!host->bus_on)
2807                 return;
2808         host->bus_on = false;
2809         pm_runtime_put_noidle(host->mmc->parent);
2810 }
2811
2812 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2813 {
2814         unsigned long flags;
2815
2816         mmc_retune_timer_stop(host->mmc);
2817         mmc_retune_needed(host->mmc);
2818
2819         spin_lock_irqsave(&host->lock, flags);
2820         host->ier &= SDHCI_INT_CARD_INT;
2821         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2822         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2823         spin_unlock_irqrestore(&host->lock, flags);
2824
2825         synchronize_hardirq(host->irq);
2826
2827         spin_lock_irqsave(&host->lock, flags);
2828         host->runtime_suspended = true;
2829         spin_unlock_irqrestore(&host->lock, flags);
2830
2831         return 0;
2832 }
2833 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2834
2835 int sdhci_runtime_resume_host(struct sdhci_host *host)
2836 {
2837         unsigned long flags;
2838         int host_flags = host->flags;
2839
2840         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2841                 if (host->ops->enable_dma)
2842                         host->ops->enable_dma(host);
2843         }
2844
2845         sdhci_init(host, 0);
2846
2847         /* Force clock and power re-program */
2848         host->pwr = 0;
2849         host->clock = 0;
2850         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2851         sdhci_do_set_ios(host, &host->mmc->ios);
2852
2853         if ((host_flags & SDHCI_PV_ENABLED) &&
2854                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2855                 spin_lock_irqsave(&host->lock, flags);
2856                 sdhci_enable_preset_value(host, true);
2857                 spin_unlock_irqrestore(&host->lock, flags);
2858         }
2859
2860         spin_lock_irqsave(&host->lock, flags);
2861
2862         host->runtime_suspended = false;
2863
2864         /* Enable SDIO IRQ */
2865         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2866                 sdhci_enable_sdio_irq_nolock(host, true);
2867
2868         /* Enable Card Detection */
2869         sdhci_enable_card_detection(host);
2870
2871         spin_unlock_irqrestore(&host->lock, flags);
2872
2873         return 0;
2874 }
2875 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2876
2877 #endif /* CONFIG_PM */
2878
2879 /*****************************************************************************\
2880  *                                                                           *
2881  * Device allocation/registration                                            *
2882  *                                                                           *
2883 \*****************************************************************************/
2884
2885 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2886         size_t priv_size)
2887 {
2888         struct mmc_host *mmc;
2889         struct sdhci_host *host;
2890
2891         WARN_ON(dev == NULL);
2892
2893         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2894         if (!mmc)
2895                 return ERR_PTR(-ENOMEM);
2896
2897         host = mmc_priv(mmc);
2898         host->mmc = mmc;
2899         host->mmc_host_ops = sdhci_ops;
2900         mmc->ops = &host->mmc_host_ops;
2901
2902         return host;
2903 }
2904
2905 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2906
2907 int sdhci_add_host(struct sdhci_host *host)
2908 {
2909         struct mmc_host *mmc;
2910         u32 caps[2] = {0, 0};
2911         u32 max_current_caps;
2912         unsigned int ocr_avail;
2913         unsigned int override_timeout_clk;
2914         u32 max_clk;
2915         int ret;
2916
2917         WARN_ON(host == NULL);
2918         if (host == NULL)
2919                 return -EINVAL;
2920
2921         mmc = host->mmc;
2922
2923         if (debug_quirks)
2924                 host->quirks = debug_quirks;
2925         if (debug_quirks2)
2926                 host->quirks2 = debug_quirks2;
2927
2928         override_timeout_clk = host->timeout_clk;
2929
2930         sdhci_do_reset(host, SDHCI_RESET_ALL);
2931
2932         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2933         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2934                                 >> SDHCI_SPEC_VER_SHIFT;
2935         if (host->version > SDHCI_SPEC_300) {
2936                 pr_err("%s: Unknown controller version (%d). "
2937                         "You may experience problems.\n", mmc_hostname(mmc),
2938                         host->version);
2939         }
2940
2941         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2942                 sdhci_readl(host, SDHCI_CAPABILITIES);
2943
2944         if (host->version >= SDHCI_SPEC_300)
2945                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2946                         host->caps1 :
2947                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2948
2949         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2950                 host->flags |= SDHCI_USE_SDMA;
2951         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2952                 DBG("Controller doesn't have SDMA capability\n");
2953         else
2954                 host->flags |= SDHCI_USE_SDMA;
2955
2956         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2957                 (host->flags & SDHCI_USE_SDMA)) {
2958                 DBG("Disabling DMA as it is marked broken\n");
2959                 host->flags &= ~SDHCI_USE_SDMA;
2960         }
2961
2962         if ((host->version >= SDHCI_SPEC_200) &&
2963                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2964                 host->flags |= SDHCI_USE_ADMA;
2965
2966         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2967                 (host->flags & SDHCI_USE_ADMA)) {
2968                 DBG("Disabling ADMA as it is marked broken\n");
2969                 host->flags &= ~SDHCI_USE_ADMA;
2970         }
2971
2972         /*
2973          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2974          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2975          * that during the first call to ->enable_dma().  Similarly
2976          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2977          * implement.
2978          */
2979         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2980                 host->flags |= SDHCI_USE_64_BIT_DMA;
2981
2982         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2983                 if (host->ops->enable_dma) {
2984                         if (host->ops->enable_dma(host)) {
2985                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2986                                         mmc_hostname(mmc));
2987                                 host->flags &=
2988                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2989                         }
2990                 }
2991         }
2992
2993         /* SDMA does not support 64-bit DMA */
2994         if (host->flags & SDHCI_USE_64_BIT_DMA)
2995                 host->flags &= ~SDHCI_USE_SDMA;
2996
2997         if (host->flags & SDHCI_USE_ADMA) {
2998                 /*
2999                  * The DMA descriptor table size is calculated as the maximum
3000                  * number of segments times 2, to allow for an alignment
3001                  * descriptor for each segment, plus 1 for a nop end descriptor,
3002                  * all multipled by the descriptor size.
3003                  */
3004                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3005                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3006                                               SDHCI_ADMA2_64_DESC_SZ;
3007                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3008                 } else {
3009                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3010                                               SDHCI_ADMA2_32_DESC_SZ;
3011                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3012                 }
3013                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3014                                                       host->adma_table_sz,
3015                                                       &host->adma_addr,
3016                                                       GFP_KERNEL);
3017                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3018                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3019                 if (!host->adma_table || !host->align_buffer) {
3020                         if (host->adma_table)
3021                                 dma_free_coherent(mmc_dev(mmc),
3022                                                   host->adma_table_sz,
3023                                                   host->adma_table,
3024                                                   host->adma_addr);
3025                         kfree(host->align_buffer);
3026                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3027                                 mmc_hostname(mmc));
3028                         host->flags &= ~SDHCI_USE_ADMA;
3029                         host->adma_table = NULL;
3030                         host->align_buffer = NULL;
3031                 } else if (host->adma_addr & (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3032                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3033                                 mmc_hostname(mmc));
3034                         host->flags &= ~SDHCI_USE_ADMA;
3035                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3036                                           host->adma_table, host->adma_addr);
3037                         kfree(host->align_buffer);
3038                         host->adma_table = NULL;
3039                         host->align_buffer = NULL;
3040                 }
3041         }
3042
3043         /*
3044          * If we use DMA, then it's up to the caller to set the DMA
3045          * mask, but PIO does not need the hw shim so we set a new
3046          * mask here in that case.
3047          */
3048         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3049                 host->dma_mask = DMA_BIT_MASK(64);
3050                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3051         }
3052
3053         if (host->version >= SDHCI_SPEC_300)
3054                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3055                         >> SDHCI_CLOCK_BASE_SHIFT;
3056         else
3057                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3058                         >> SDHCI_CLOCK_BASE_SHIFT;
3059
3060         host->max_clk *= 1000000;
3061         if (host->max_clk == 0 || host->quirks &
3062                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3063                 if (!host->ops->get_max_clock) {
3064                         pr_err("%s: Hardware doesn't specify base clock "
3065                                "frequency.\n", mmc_hostname(mmc));
3066                         return -ENODEV;
3067                 }
3068                 host->max_clk = host->ops->get_max_clock(host);
3069         }
3070
3071         /*
3072          * In case of Host Controller v3.00, find out whether clock
3073          * multiplier is supported.
3074          */
3075         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3076                         SDHCI_CLOCK_MUL_SHIFT;
3077
3078         /*
3079          * In case the value in Clock Multiplier is 0, then programmable
3080          * clock mode is not supported, otherwise the actual clock
3081          * multiplier is one more than the value of Clock Multiplier
3082          * in the Capabilities Register.
3083          */
3084         if (host->clk_mul)
3085                 host->clk_mul += 1;
3086
3087         /*
3088          * Set host parameters.
3089          */
3090         max_clk = host->max_clk;
3091
3092         if (host->ops->get_min_clock)
3093                 mmc->f_min = host->ops->get_min_clock(host);
3094         else if (host->version >= SDHCI_SPEC_300) {
3095                 if (host->clk_mul) {
3096                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3097                         max_clk = host->max_clk * host->clk_mul;
3098                 } else
3099                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3100         } else
3101                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3102
3103         if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3104                 mmc->f_max = max_clk;
3105
3106         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3107                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3108                                         SDHCI_TIMEOUT_CLK_SHIFT;
3109                 if (host->timeout_clk == 0) {
3110                         if (host->ops->get_timeout_clock) {
3111                                 host->timeout_clk =
3112                                         host->ops->get_timeout_clock(host);
3113                         } else {
3114                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3115                                         mmc_hostname(mmc));
3116                                 return -ENODEV;
3117                         }
3118                 }
3119
3120                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3121                         host->timeout_clk *= 1000;
3122
3123                 if (override_timeout_clk)
3124                         host->timeout_clk = override_timeout_clk;
3125
3126                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3127                         host->ops->get_max_timeout_count(host) : 1 << 27;
3128                 mmc->max_busy_timeout /= host->timeout_clk;
3129         }
3130
3131         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3132         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3133
3134         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3135                 host->flags |= SDHCI_AUTO_CMD12;
3136
3137         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3138         if ((host->version >= SDHCI_SPEC_300) &&
3139             ((host->flags & SDHCI_USE_ADMA) ||
3140              !(host->flags & SDHCI_USE_SDMA)) &&
3141              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3142                 host->flags |= SDHCI_AUTO_CMD23;
3143                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3144         } else {
3145                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3146         }
3147
3148         /*
3149          * A controller may support 8-bit width, but the board itself
3150          * might not have the pins brought out.  Boards that support
3151          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3152          * their platform code before calling sdhci_add_host(), and we
3153          * won't assume 8-bit width for hosts without that CAP.
3154          */
3155         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3156                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3157
3158         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3159                 mmc->caps &= ~MMC_CAP_CMD23;
3160
3161         if (caps[0] & SDHCI_CAN_DO_HISPD)
3162                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3163
3164         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3165             !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3166             IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3167                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3168
3169         /* If there are external regulators, get them */
3170         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3171                 return -EPROBE_DEFER;
3172
3173         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3174         if (!IS_ERR(mmc->supply.vqmmc)) {
3175                 ret = regulator_enable(mmc->supply.vqmmc);
3176                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3177                                                     1950000))
3178                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3179                                         SDHCI_SUPPORT_SDR50 |
3180                                         SDHCI_SUPPORT_DDR50);
3181                 if (ret) {
3182                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3183                                 mmc_hostname(mmc), ret);
3184                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3185                 }
3186         }
3187
3188         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3189                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3190                        SDHCI_SUPPORT_DDR50);
3191
3192         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3193         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3194                        SDHCI_SUPPORT_DDR50))
3195                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3196
3197         /* SDR104 supports also implies SDR50 support */
3198         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3199                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3200                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3201                  * field can be promoted to support HS200.
3202                  */
3203                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3204                         mmc->caps2 |= MMC_CAP2_HS200;
3205         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3206                 mmc->caps |= MMC_CAP_UHS_SDR50;
3207
3208         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3209             (caps[1] & SDHCI_SUPPORT_HS400))
3210                 mmc->caps2 |= MMC_CAP2_HS400;
3211
3212         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3213             (IS_ERR(mmc->supply.vqmmc) ||
3214              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3215                                              1300000)))
3216                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3217
3218         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3219                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3220                 mmc->caps |= MMC_CAP_UHS_DDR50;
3221
3222         /* Does the host need tuning for SDR50? */
3223         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3224                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3225
3226         /* Does the host need tuning for SDR104 / HS200? */
3227         if (mmc->caps2 & MMC_CAP2_HS200)
3228                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3229
3230         /* Driver Type(s) (A, C, D) supported by the host */
3231         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3232                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3233         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3234                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3235         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3236                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3237
3238         /* Initial value for re-tuning timer count */
3239         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3240                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3241
3242         /*
3243          * In case Re-tuning Timer is not disabled, the actual value of
3244          * re-tuning timer will be 2 ^ (n - 1).
3245          */
3246         if (host->tuning_count)
3247                 host->tuning_count = 1 << (host->tuning_count - 1);
3248
3249         /* Re-tuning mode supported by the Host Controller */
3250         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3251                              SDHCI_RETUNING_MODE_SHIFT;
3252
3253         ocr_avail = 0;
3254
3255         /*
3256          * According to SD Host Controller spec v3.00, if the Host System
3257          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3258          * the value is meaningful only if Voltage Support in the Capabilities
3259          * register is set. The actual current value is 4 times the register
3260          * value.
3261          */
3262         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3263         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3264                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3265                 if (curr > 0) {
3266
3267                         /* convert to SDHCI_MAX_CURRENT format */
3268                         curr = curr/1000;  /* convert to mA */
3269                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3270
3271                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3272                         max_current_caps =
3273                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3274                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3275                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3276                 }
3277         }
3278
3279         if (caps[0] & SDHCI_CAN_VDD_330) {
3280                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3281
3282                 mmc->max_current_330 = ((max_current_caps &
3283                                    SDHCI_MAX_CURRENT_330_MASK) >>
3284                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3285                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3286         }
3287         if (caps[0] & SDHCI_CAN_VDD_300) {
3288                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3289
3290                 mmc->max_current_300 = ((max_current_caps &
3291                                    SDHCI_MAX_CURRENT_300_MASK) >>
3292                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3293                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3294         }
3295         if (caps[0] & SDHCI_CAN_VDD_180) {
3296                 ocr_avail |= MMC_VDD_165_195;
3297
3298                 mmc->max_current_180 = ((max_current_caps &
3299                                    SDHCI_MAX_CURRENT_180_MASK) >>
3300                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3301                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3302         }
3303
3304         /* If OCR set by host, use it instead. */
3305         if (host->ocr_mask)
3306                 ocr_avail = host->ocr_mask;
3307
3308         /* If OCR set by external regulators, give it highest prio. */
3309         if (mmc->ocr_avail)
3310                 ocr_avail = mmc->ocr_avail;
3311
3312         mmc->ocr_avail = ocr_avail;
3313         mmc->ocr_avail_sdio = ocr_avail;
3314         if (host->ocr_avail_sdio)
3315                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3316         mmc->ocr_avail_sd = ocr_avail;
3317         if (host->ocr_avail_sd)
3318                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3319         else /* normal SD controllers don't support 1.8V */
3320                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3321         mmc->ocr_avail_mmc = ocr_avail;
3322         if (host->ocr_avail_mmc)
3323                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3324
3325         if (mmc->ocr_avail == 0) {
3326                 pr_err("%s: Hardware doesn't report any "
3327                         "support voltages.\n", mmc_hostname(mmc));
3328                 return -ENODEV;
3329         }
3330
3331         spin_lock_init(&host->lock);
3332
3333         /*
3334          * Maximum number of segments. Depends on if the hardware
3335          * can do scatter/gather or not.
3336          */
3337         if (host->flags & SDHCI_USE_ADMA)
3338                 mmc->max_segs = SDHCI_MAX_SEGS;
3339         else if (host->flags & SDHCI_USE_SDMA)
3340                 mmc->max_segs = 1;
3341         else /* PIO */
3342                 mmc->max_segs = SDHCI_MAX_SEGS;
3343
3344         /*
3345          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3346          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3347          * is less anyway.
3348          */
3349         mmc->max_req_size = 524288;
3350
3351         /*
3352          * Maximum segment size. Could be one segment with the maximum number
3353          * of bytes. When doing hardware scatter/gather, each entry cannot
3354          * be larger than 64 KiB though.
3355          */
3356         if (host->flags & SDHCI_USE_ADMA) {
3357                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3358                         mmc->max_seg_size = 65535;
3359                 else
3360                         mmc->max_seg_size = 65536;
3361         } else {
3362                 mmc->max_seg_size = mmc->max_req_size;
3363         }
3364
3365         /*
3366          * Maximum block size. This varies from controller to controller and
3367          * is specified in the capabilities register.
3368          */
3369         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3370                 mmc->max_blk_size = 2;
3371         } else {
3372                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3373                                 SDHCI_MAX_BLOCK_SHIFT;
3374                 if (mmc->max_blk_size >= 3) {
3375                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3376                                 mmc_hostname(mmc));
3377                         mmc->max_blk_size = 0;
3378                 }
3379         }
3380
3381         mmc->max_blk_size = 512 << mmc->max_blk_size;
3382
3383         /*
3384          * Maximum block count.
3385          */
3386         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3387
3388         /*
3389          * Init tasklets.
3390          */
3391         tasklet_init(&host->finish_tasklet,
3392                 sdhci_tasklet_finish, (unsigned long)host);
3393
3394         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3395
3396         init_waitqueue_head(&host->buf_ready_int);
3397
3398         sdhci_init(host, 0);
3399
3400         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3401                                    IRQF_SHARED, mmc_hostname(mmc), host);
3402         if (ret) {
3403                 pr_err("%s: Failed to request IRQ %d: %d\n",
3404                        mmc_hostname(mmc), host->irq, ret);
3405                 goto untasklet;
3406         }
3407
3408 #ifdef CONFIG_MMC_DEBUG
3409         sdhci_dumpregs(host);
3410 #endif
3411
3412 #ifdef SDHCI_USE_LEDS_CLASS
3413         snprintf(host->led_name, sizeof(host->led_name),
3414                 "%s::", mmc_hostname(mmc));
3415         host->led.name = host->led_name;
3416         host->led.brightness = LED_OFF;
3417         host->led.default_trigger = mmc_hostname(mmc);
3418         host->led.brightness_set = sdhci_led_control;
3419
3420         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3421         if (ret) {
3422                 pr_err("%s: Failed to register LED device: %d\n",
3423                        mmc_hostname(mmc), ret);
3424                 goto reset;
3425         }
3426 #endif
3427
3428         mmiowb();
3429
3430         mmc_add_host(mmc);
3431
3432         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3433                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3434                 (host->flags & SDHCI_USE_ADMA) ?
3435                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3436                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3437
3438         sdhci_enable_card_detection(host);
3439
3440         return 0;
3441
3442 #ifdef SDHCI_USE_LEDS_CLASS
3443 reset:
3444         sdhci_do_reset(host, SDHCI_RESET_ALL);
3445         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3446         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3447         free_irq(host->irq, host);
3448 #endif
3449 untasklet:
3450         tasklet_kill(&host->finish_tasklet);
3451
3452         return ret;
3453 }
3454
3455 EXPORT_SYMBOL_GPL(sdhci_add_host);
3456
3457 void sdhci_remove_host(struct sdhci_host *host, int dead)
3458 {
3459         struct mmc_host *mmc = host->mmc;
3460         unsigned long flags;
3461
3462         if (dead) {
3463                 spin_lock_irqsave(&host->lock, flags);
3464
3465                 host->flags |= SDHCI_DEVICE_DEAD;
3466
3467                 if (host->mrq) {
3468                         pr_err("%s: Controller removed during "
3469                                 " transfer!\n", mmc_hostname(mmc));
3470
3471                         host->mrq->cmd->error = -ENOMEDIUM;
3472                         tasklet_schedule(&host->finish_tasklet);
3473                 }
3474
3475                 spin_unlock_irqrestore(&host->lock, flags);
3476         }
3477
3478         sdhci_disable_card_detection(host);
3479
3480         mmc_remove_host(mmc);
3481
3482 #ifdef SDHCI_USE_LEDS_CLASS
3483         led_classdev_unregister(&host->led);
3484 #endif
3485
3486         if (!dead)
3487                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3488
3489         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3490         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3491         free_irq(host->irq, host);
3492
3493         del_timer_sync(&host->timer);
3494
3495         tasklet_kill(&host->finish_tasklet);
3496
3497         if (!IS_ERR(mmc->supply.vqmmc))
3498                 regulator_disable(mmc->supply.vqmmc);
3499
3500         if (host->adma_table)
3501                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3502                                   host->adma_table, host->adma_addr);
3503         kfree(host->align_buffer);
3504
3505         host->adma_table = NULL;
3506         host->align_buffer = NULL;
3507 }
3508
3509 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3510
3511 void sdhci_free_host(struct sdhci_host *host)
3512 {
3513         mmc_free_host(host->mmc);
3514 }
3515
3516 EXPORT_SYMBOL_GPL(sdhci_free_host);
3517
3518 /*****************************************************************************\
3519  *                                                                           *
3520  * Driver init/exit                                                          *
3521  *                                                                           *
3522 \*****************************************************************************/
3523
3524 static int __init sdhci_drv_init(void)
3525 {
3526         pr_info(DRIVER_NAME
3527                 ": Secure Digital Host Controller Interface driver\n");
3528         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3529
3530         return 0;
3531 }
3532
3533 static void __exit sdhci_drv_exit(void)
3534 {
3535 }
3536
3537 module_init(sdhci_drv_init);
3538 module_exit(sdhci_drv_exit);
3539
3540 module_param(debug_quirks, uint, 0444);
3541 module_param(debug_quirks2, uint, 0444);
3542
3543 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3544 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3545 MODULE_LICENSE("GPL");
3546
3547 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3548 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");