drivers/clk/rockchip/clk.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * based on
   9  *
  10  * samsung/clk.c
  11  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12  * Copyright (c) 2013 Linaro Ltd.
  13  * Author: Thomas Abraham <thomas.ab@samsung.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/slab.h>
  27 #include <linux/clk.h>
  28 #include <linux/clk-provider.h>
  29 #include <linux/mfd/syscon.h>
  30 #include <linux/regmap.h>
  31 #include <linux/reboot.h>
  32 #include "clk.h"
  33
  34 /**
  35  * Register a clock branch.
  36  * Most clock branches have a form like
  37  *
  38  * src1 --|--\
  39  *        |M |--[GATE]-[DIV]-
  40  * src2 --|--/
  41  *
  42  * sometimes without one of those components.
  43  */
  44 static struct clk *rockchip_clk_register_branch(const char *name,
  45                 const char *const *parent_names, u8 num_parents, void __iomem *base,
  46                 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
  47                 u8 div_shift, u8 div_width, u8 div_flags,
  48                 struct clk_div_table *div_table, int gate_offset,
  49                 u8 gate_shift, u8 gate_flags, unsigned long flags,
  50                 spinlock_t *lock)
  51 {
  52         struct clk *clk;
  53         struct clk_mux *mux = NULL;
  54         struct clk_gate *gate = NULL;
  55         struct clk_divider *div = NULL;
  56         const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
  57                              *gate_ops = NULL;
  58
  59         if (num_parents > 1) {
  60                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  61                 if (!mux)
  62                         return ERR_PTR(-ENOMEM);
  63
  64                 mux->reg = base + muxdiv_offset;
  65                 mux->shift = mux_shift;
  66                 mux->mask = BIT(mux_width) - 1;
  67                 mux->flags = mux_flags;
  68                 mux->lock = lock;
  69                 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
  70                                                         : &clk_mux_ops;
  71         }
  72
  73         if (gate_offset >= 0) {
  74                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  75                 if (!gate)
  76                         goto err_gate;
  77
  78                 gate->flags = gate_flags;
  79                 gate->reg = base + gate_offset;
  80                 gate->bit_idx = gate_shift;
  81                 gate->lock = lock;
  82                 gate_ops = &clk_gate_ops;
  83         }
  84
  85         if (div_width > 0) {
  86                 div = kzalloc(sizeof(*div), GFP_KERNEL);
  87                 if (!div)
  88                         goto err_div;
  89
  90                 div->flags = div_flags;
  91                 div->reg = base + muxdiv_offset;
  92                 div->shift = div_shift;
  93                 div->width = div_width;
  94                 div->lock = lock;
  95                 div->table = div_table;
  96                 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
  97                                                 ? &clk_divider_ro_ops
  98                                                 : &clk_divider_ops;
  99         }
 100
 101         clk = clk_register_composite(NULL, name, parent_names, num_parents,
 102                                      mux ? &mux->hw : NULL, mux_ops,
 103                                      div ? &div->hw : NULL, div_ops,
 104                                      gate ? &gate->hw : NULL, gate_ops,
 105                                      flags);
 106
 107         return clk;
 108 err_div:
 109         kfree(gate);
 110 err_gate:
 111         kfree(mux);
 112         return ERR_PTR(-ENOMEM);
 113 }
 114
 115 struct rockchip_clk_frac {
 116         struct notifier_block                   clk_nb;
 117         struct clk_fractional_divider           div;
 118         struct clk_gate                         gate;
 119
 120         struct clk_mux                          mux;
 121         const struct clk_ops                    *mux_ops;
 122         int                                     mux_frac_idx;
 123
 124         bool                                    rate_change_remuxed;
 125         int                                     rate_change_idx;
 126 };
 127
 128 #define to_rockchip_clk_frac_nb(nb) \
 129                         container_of(nb, struct rockchip_clk_frac, clk_nb)
 130
 131 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 132                                          unsigned long event, void *data)
 133 {
 134         struct clk_notifier_data *ndata = data;
 135         struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
 136         struct clk_mux *frac_mux = &frac->mux;
 137         int ret = 0;
 138
 139         pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
 140                  __func__, event, ndata->old_rate, ndata->new_rate);
 141         if (event == PRE_RATE_CHANGE) {
 142                 frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
 143                 if (frac->rate_change_idx != frac->mux_frac_idx) {
 144                         frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
 145                         frac->rate_change_remuxed = 1;
 146                 }
 147         } else if (event == POST_RATE_CHANGE) {
 148                 /*
 149                  * The POST_RATE_CHANGE notifier runs directly after the
 150                  * divider clock is set in clk_change_rate, so we'll have
 151                  * remuxed back to the original parent before clk_change_rate
 152                  * reaches the mux itself.
 153                  */
 154                 if (frac->rate_change_remuxed) {
 155                         frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
 156                         frac->rate_change_remuxed = 0;
 157                 }
 158         }
 159
 160         return notifier_from_errno(ret);
 161 }
 162
 163 static struct clk *rockchip_clk_register_frac_branch(
 164                 struct rockchip_clk_provider *ctx, const char *name,
 165                 const char *const *parent_names, u8 num_parents,
 166                 void __iomem *base, int muxdiv_offset, u8 div_flags,
 167                 int gate_offset, u8 gate_shift, u8 gate_flags,
 168                 unsigned long flags, struct rockchip_clk_branch *child,
 169                 spinlock_t *lock)
 170 {
 171         struct rockchip_clk_frac *frac;
 172         struct clk *clk;
 173         struct clk_gate *gate = NULL;
 174         struct clk_fractional_divider *div = NULL;
 175         const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
 176
 177         if (muxdiv_offset < 0)
 178                 return ERR_PTR(-EINVAL);
 179
 180         if (child && child->branch_type != branch_mux) {
 181                 pr_err("%s: fractional child clock for %s can only be a mux\n",
 182                        __func__, name);
 183                 return ERR_PTR(-EINVAL);
 184         }
 185
 186         frac = kzalloc(sizeof(*frac), GFP_KERNEL);
 187         if (!frac)
 188                 return ERR_PTR(-ENOMEM);
 189
 190         if (gate_offset >= 0) {
 191                 gate = &frac->gate;
 192                 gate->flags = gate_flags;
 193                 gate->reg = base + gate_offset;
 194                 gate->bit_idx = gate_shift;
 195                 gate->lock = lock;
 196                 gate_ops = &clk_gate_ops;
 197         }
 198
 199         div = &frac->div;
 200         div->flags = div_flags;
 201         div->reg = base + muxdiv_offset;
 202         div->mshift = 16;
 203         div->mwidth = 16;
 204         div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
 205         div->nshift = 0;
 206         div->nwidth = 16;
 207         div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 208         div->lock = lock;
 209         div_ops = &clk_fractional_divider_ops;
 210
 211         clk = clk_register_composite(NULL, name, parent_names, num_parents,
 212                                      NULL, NULL,
 213                                      &div->hw, div_ops,
 214                                      gate ? &gate->hw : NULL, gate_ops,
 215                                      flags | CLK_SET_RATE_UNGATE);
 216         if (IS_ERR(clk)) {
 217                 kfree(frac);
 218                 return clk;
 219         }
 220
 221         if (child) {
 222                 struct clk_mux *frac_mux = &frac->mux;
 223                 struct clk_init_data init;
 224                 struct clk *mux_clk;
 225                 int i, ret;
 226
 227                 frac->mux_frac_idx = -1;
 228                 for (i = 0; i < child->num_parents; i++) {
 229                         if (!strcmp(name, child->parent_names[i])) {
 230                                 pr_debug("%s: found fractional parent in mux at pos %d\n",
 231                                          __func__, i);
 232                                 frac->mux_frac_idx = i;
 233                                 break;
 234                         }
 235                 }
 236
 237                 frac->mux_ops = &clk_mux_ops;
 238                 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
 239
 240                 frac_mux->reg = base + child->muxdiv_offset;
 241                 frac_mux->shift = child->mux_shift;
 242                 frac_mux->mask = BIT(child->mux_width) - 1;
 243                 frac_mux->flags = child->mux_flags;
 244                 frac_mux->lock = lock;
 245                 frac_mux->hw.init = &init;
 246
 247                 init.name = child->name;
 248                 init.flags = child->flags | CLK_SET_RATE_PARENT;
 249                 init.ops = frac->mux_ops;
 250                 init.parent_names = child->parent_names;
 251                 init.num_parents = child->num_parents;
 252
 253                 mux_clk = clk_register(NULL, &frac_mux->hw);
 254                 if (IS_ERR(mux_clk))
 255                         return clk;
 256
 257                 rockchip_clk_add_lookup(ctx, mux_clk, child->id);
 258
 259                 /* notifier on the fraction divider to catch rate changes */
 260                 if (frac->mux_frac_idx >= 0) {
 261                         ret = clk_notifier_register(clk, &frac->clk_nb);
 262                         if (ret)
 263                                 pr_err("%s: failed to register clock notifier for %s\n",
 264                                                 __func__, name);
 265                 } else {
 266                         pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
 267                                 __func__, name, child->name);
 268                 }
 269         }
 270
 271         return clk;
 272 }
 273
 274 static struct clk *rockchip_clk_register_factor_branch(const char *name,
 275                 const char *const *parent_names, u8 num_parents,
 276                 void __iomem *base, unsigned int mult, unsigned int div,
 277                 int gate_offset, u8 gate_shift, u8 gate_flags,
 278                 unsigned long flags, spinlock_t *lock)
 279 {
 280         struct clk *clk;
 281         struct clk_gate *gate = NULL;
 282         struct clk_fixed_factor *fix = NULL;
 283
 284         /* without gate, register a simple factor clock */
 285         if (gate_offset == 0) {
 286                 return clk_register_fixed_factor(NULL, name,
 287                                 parent_names[0], flags, mult,
 288                                 div);
 289         }
 290
 291         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 292         if (!gate)
 293                 return ERR_PTR(-ENOMEM);
 294
 295         gate->flags = gate_flags;
 296         gate->reg = base + gate_offset;
 297         gate->bit_idx = gate_shift;
 298         gate->lock = lock;
 299
 300         fix = kzalloc(sizeof(*fix), GFP_KERNEL);
 301         if (!fix) {
 302                 kfree(gate);
 303                 return ERR_PTR(-ENOMEM);
 304         }
 305
 306         fix->mult = mult;
 307         fix->div = div;
 308
 309         clk = clk_register_composite(NULL, name, parent_names, num_parents,
 310                                      NULL, NULL,
 311                                      &fix->hw, &clk_fixed_factor_ops,
 312                                      &gate->hw, &clk_gate_ops, flags);
 313         if (IS_ERR(clk)) {
 314                 kfree(fix);
 315                 kfree(gate);
 316         }
 317
 318         return clk;
 319 }
 320
 321 struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
 322                         void __iomem *base, unsigned long nr_clks)
 323 {
 324         struct rockchip_clk_provider *ctx;
 325         struct clk **clk_table;
 326         int i;
 327
 328         ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
 329         if (!ctx) {
 330                 pr_err("%s: Could not allocate clock provider context\n",
 331                         __func__);
 332                 return ERR_PTR(-ENOMEM);
 333         }
 334
 335         clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
 336         if (!clk_table) {
 337                 pr_err("%s: Could not allocate clock lookup table\n",
 338                         __func__);
 339                 goto err_free;
 340         }
 341
 342         for (i = 0; i < nr_clks; ++i)
 343                 clk_table[i] = ERR_PTR(-ENOENT);
 344
 345         ctx->reg_base = base;
 346         ctx->clk_data.clks = clk_table;
 347         ctx->clk_data.clk_num = nr_clks;
 348         ctx->cru_node = np;
 349         ctx->grf = ERR_PTR(-EPROBE_DEFER);
 350         spin_lock_init(&ctx->lock);
 351         ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
 352                                                    "rockchip,grf");
 353
 354         return ctx;
 355
 356 err_free:
 357         kfree(ctx);
 358         return ERR_PTR(-ENOMEM);
 359 }
 360
 361 void __init rockchip_clk_of_add_provider(struct device_node *np,
 362                                 struct rockchip_clk_provider *ctx)
 363 {
 364         if (of_clk_add_provider(np, of_clk_src_onecell_get,
 365                                 &ctx->clk_data))
 366                 pr_err("%s: could not register clk provider\n", __func__);
 367 }
 368
 369 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx)
 370 {
 371         if (IS_ERR(ctx->grf))
 372                 ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, "rockchip,grf");
 373         return ctx->grf;
 374 }
 375
 376 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
 377                              struct clk *clk, unsigned int id)
 378 {
 379         if (ctx->clk_data.clks && id)
 380                 ctx->clk_data.clks[id] = clk;
 381 }
 382
 383 void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 384                                 struct rockchip_pll_clock *list,
 385                                 unsigned int nr_pll, int grf_lock_offset)
 386 {
 387         struct clk *clk;
 388         int idx;
 389
 390         for (idx = 0; idx < nr_pll; idx++, list++) {
 391                 clk = rockchip_clk_register_pll(ctx, list->type, list->name,
 392                                 list->parent_names, list->num_parents,
 393                                 list->con_offset, grf_lock_offset,
 394                                 list->lock_shift, list->mode_offset,
 395                                 list->mode_shift, list->rate_table,
 396                                 list->flags, list->pll_flags);
 397                 if (IS_ERR(clk)) {
 398                         pr_err("%s: failed to register clock %s\n", __func__,
 399                                 list->name);
 400                         continue;
 401                 }
 402
 403                 rockchip_clk_add_lookup(ctx, clk, list->id);
 404         }
 405 }
 406
 407 void __init rockchip_clk_register_branches(
 408                                       struct rockchip_clk_provider *ctx,
 409                                       struct rockchip_clk_branch *list,
 410                                       unsigned int nr_clk)
 411 {
 412         struct clk *clk = NULL;
 413         unsigned int idx;
 414         unsigned long flags;
 415
 416         for (idx = 0; idx < nr_clk; idx++, list++) {
 417                 flags = list->flags;
 418
 419                 /* catch simple muxes */
 420                 switch (list->branch_type) {
 421                 case branch_mux:
 422                         clk = clk_register_mux(NULL, list->name,
 423                                 list->parent_names, list->num_parents,
 424                                 flags, ctx->reg_base + list->muxdiv_offset,
 425                                 list->mux_shift, list->mux_width,
 426                                 list->mux_flags, &ctx->lock);
 427                         break;
 428                 case branch_muxgrf:
 429                         clk = rockchip_clk_register_muxgrf(list->name,
 430                                 list->parent_names, list->num_parents,
 431                                 flags, ctx->grf, list->muxdiv_offset,
 432                                 list->mux_shift, list->mux_width,
 433                                 list->mux_flags);
 434                         break;
 435                 case branch_divider:
 436                         if (list->div_table)
 437                                 clk = clk_register_divider_table(NULL,
 438                                         list->name, list->parent_names[0],
 439                                         flags, ctx->reg_base + list->muxdiv_offset,
 440                                         list->div_shift, list->div_width,
 441                                         list->div_flags, list->div_table,
 442                                         &ctx->lock);
 443                         else
 444                                 clk = clk_register_divider(NULL, list->name,
 445                                         list->parent_names[0], flags,
 446                                         ctx->reg_base + list->muxdiv_offset,
 447                                         list->div_shift, list->div_width,
 448                                         list->div_flags, &ctx->lock);
 449                         break;
 450                 case branch_fraction_divider:
 451                         clk = rockchip_clk_register_frac_branch(ctx, list->name,
 452                                 list->parent_names, list->num_parents,
 453                                 ctx->reg_base, list->muxdiv_offset, list->div_flags,
 454                                 list->gate_offset, list->gate_shift,
 455                                 list->gate_flags, flags, list->child,
 456                                 &ctx->lock);
 457                         break;
 458                 case branch_gate:
 459                         flags |= CLK_SET_RATE_PARENT;
 460
 461                         clk = clk_register_gate(NULL, list->name,
 462                                 list->parent_names[0], flags,
 463                                 ctx->reg_base + list->gate_offset,
 464                                 list->gate_shift, list->gate_flags, &ctx->lock);
 465                         break;
 466                 case branch_composite:
 467                         clk = rockchip_clk_register_branch(list->name,
 468                                 list->parent_names, list->num_parents,
 469                                 ctx->reg_base, list->muxdiv_offset, list->mux_shift,
 470                                 list->mux_width, list->mux_flags,
 471                                 list->div_shift, list->div_width,
 472                                 list->div_flags, list->div_table,
 473                                 list->gate_offset, list->gate_shift,
 474                                 list->gate_flags, flags, &ctx->lock);
 475                         break;
 476                 case branch_mmc:
 477                         clk = rockchip_clk_register_mmc(
 478                                 list->name,
 479                                 list->parent_names, list->num_parents,
 480                                 ctx->reg_base + list->muxdiv_offset,
 481                                 list->div_shift
 482                         );
 483                         break;
 484                 case branch_inverter:
 485                         clk = rockchip_clk_register_inverter(
 486                                 list->name, list->parent_names,
 487                                 list->num_parents,
 488                                 ctx->reg_base + list->muxdiv_offset,
 489                                 list->div_shift, list->div_flags, &ctx->lock);
 490                         break;
 491                 case branch_factor:
 492                         clk = rockchip_clk_register_factor_branch(
 493                                 list->name, list->parent_names,
 494                                 list->num_parents, ctx->reg_base,
 495                                 list->div_shift, list->div_width,
 496                                 list->gate_offset, list->gate_shift,
 497                                 list->gate_flags, flags, &ctx->lock);
 498                         break;
 499                 case branch_ddrc:
 500                         clk = rockchip_clk_register_ddrclk(
 501                                 list->name, list->flags,
 502                                 list->parent_names, list->num_parents,
 503                                 list->muxdiv_offset, list->mux_shift,
 504                                 list->mux_width, list->div_shift,
 505                                 list->div_width, list->div_flags,
 506                                 ctx->reg_base, &ctx->lock);
 507                         break;
 508                 }
 509
 510                 /* none of the cases above matched */
 511                 if (!clk) {
 512                         pr_err("%s: unknown clock type %d\n",
 513                                __func__, list->branch_type);
 514                         continue;
 515                 }
 516
 517                 if (IS_ERR(clk)) {
 518                         pr_err("%s: failed to register clock %s: %ld\n",
 519                                __func__, list->name, PTR_ERR(clk));
 520                         continue;
 521                 }
 522
 523                 rockchip_clk_add_lookup(ctx, clk, list->id);
 524         }
 525 }
 526
 527 void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
 528                         unsigned int lookup_id,
 529                         const char *name, const char *const *parent_names,
 530                         u8 num_parents,
 531                         const struct rockchip_cpuclk_reg_data *reg_data,
 532                         const struct rockchip_cpuclk_rate_table *rates,
 533                         int nrates)
 534 {
 535         struct clk *clk;
 536
 537         clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
 538                                            reg_data, rates, nrates, ctx->reg_base,
 539                                            &ctx->lock);
 540         if (IS_ERR(clk)) {
 541                 pr_err("%s: failed to register clock %s: %ld\n",
 542                        __func__, name, PTR_ERR(clk));
 543                 return;
 544         }
 545
 546         rockchip_clk_add_lookup(ctx, clk, lookup_id);
 547 }
 548
 549 void __init rockchip_clk_protect_critical(const char *const clocks[],
 550                                           int nclocks)
 551 {
 552         int i;
 553
 554         /* Protect the clocks that needs to stay on */
 555         for (i = 0; i < nclocks; i++) {
 556                 struct clk *clk = __clk_lookup(clocks[i]);
 557
 558                 if (clk)
 559                         clk_prepare_enable(clk);
 560         }
 561 }
 562
 563 static void __iomem *rst_base;
 564 static unsigned int reg_restart;
 565 static void (*cb_restart)(void);
 566 static int rockchip_restart_notify(struct notifier_block *this,
 567                                    unsigned long mode, void *cmd)
 568 {
 569         if (cb_restart)
 570                 cb_restart();
 571
 572         writel(0xfdb9, rst_base + reg_restart);
 573         return NOTIFY_DONE;
 574 }
 575
 576 static struct notifier_block rockchip_restart_handler = {
 577         .notifier_call = rockchip_restart_notify,
 578         .priority = 128,
 579 };
 580
 581 void __init rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
 582                                                unsigned int reg, void (*cb)(void))
 583 {
 584         int ret;
 585
 586         rst_base = ctx->reg_base;
 587         reg_restart = reg;
 588         cb_restart = cb;
 589         ret = register_restart_handler(&rockchip_restart_handler);
 590         if (ret)
 591                 pr_err("%s: cannot register restart handler, %d\n",
 592                        __func__, ret);
 593 }