arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/pinctrl/rockchip.h>
  47
  48 / {
  49         compatible = "rockchip,rk3399";
  50         interrupt-parent = <&gic>;
  51         #address-cells = <2>;
  52         #size-cells = <2>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58                 serial3 = &uart3;
  59         };
  60
  61         cpus {
  62                 #address-cells = <2>;
  63                 #size-cells = <0>;
  64
  65                 cpu-map {
  66                         cluster0 {
  67                                 core0 {
  68                                         cpu = <&cpu_l0>;
  69                                 };
  70                                 core1 {
  71                                         cpu = <&cpu_l1>;
  72                                 };
  73                                 core2 {
  74                                         cpu = <&cpu_l2>;
  75                                 };
  76                                 core3 {
  77                                         cpu = <&cpu_l3>;
  78                                 };
  79                         };
  80
  81                         cluster1 {
  82                                 core0 {
  83                                         cpu = <&cpu_b0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_b1>;
  87                                 };
  88                         };
  89                 };
  90
  91                 cpu_l0: cpu@0 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53", "arm,armv8";
  94                         reg = <0x0 0x0>;
  95                 };
  96
  97                 cpu_l1: cpu@1 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x1>;
 101                 };
 102
 103                 cpu_l2: cpu@2 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53", "arm,armv8";
 106                         reg = <0x0 0x2>;
 107                 };
 108
 109                 cpu_l3: cpu@3 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x3>;
 113                 };
 114
 115                 cpu_b0: cpu@100 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a72", "arm,armv8";
 118                         reg = <0x0 0x100>;
 119                 };
 120
 121                 cpu_b1: cpu@101 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a72", "arm,armv8";
 124                         reg = <0x0 0x101>;
 125                 };
 126         };
 127
 128         timer {
 129                 compatible = "arm,armv8-timer";
 130                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 131                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 134         };
 135
 136         xin24m: xin24m {
 137                 compatible = "fixed-clock";
 138                 #clock-cells = <0>;
 139                 clock-frequency = <24000000>;
 140                 clock-output-names = "xin24m";
 141         };
 142
 143         gic: interrupt-controller@fee00000 {
 144                 compatible = "arm,gic-v3";
 145                 #interrupt-cells = <3>;
 146                 #address-cells = <2>;
 147                 #size-cells = <2>;
 148                 ranges;
 149                 interrupt-controller;
 150
 151                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 152                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 153                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 154                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 155                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 156                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 157                 its: interrupt-controller@fee20000 {
 158                         compatible = "arm,gic-v3-its";
 159                         msi-controller;
 160                         reg = <0x0 0xfee20000 0x0 0x20000>;
 161                 };
 162         };
 163
 164         amba {
 165                 compatible = "arm,amba-bus";
 166                 #address-cells = <2>;
 167                 #size-cells = <2>;
 168                 ranges;
 169
 170                 dmac_bus: dma-controller@ff6d0000 {
 171                         compatible = "arm,pl330", "arm,primecell";
 172                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 173                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 175                         #dma-cells = <1>;
 176                         clocks = <&cru ACLK_DMAC0_PERILP>;
 177                         clock-names = "apb_pclk";
 178                 };
 179
 180                 dmac_peri: dma-controller@ff6e0000 {
 181                         compatible = "arm,pl330", "arm,primecell";
 182                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 183                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 185                         #dma-cells = <1>;
 186                         clocks = <&cru ACLK_DMAC1_PERILP>;
 187                         clock-names = "apb_pclk";
 188                 };
 189         };
 190
 191         uart0: serial@ff180000 {
 192                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 193                 reg = <0x0 0xff180000 0x0 0x100>;
 194                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 195                 clock-names = "baudclk", "apb_pclk";
 196                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 197                 reg-shift = <2>;
 198                 reg-io-width = <4>;
 199                 status = "disabled";
 200         };
 201
 202         uart1: serial@ff190000 {
 203                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 204                 reg = <0x0 0xff190000 0x0 0x100>;
 205                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 206                 clock-names = "baudclk", "apb_pclk";
 207                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 208                 reg-shift = <2>;
 209                 reg-io-width = <4>;
 210                 status = "disabled";
 211         };
 212
 213         uart2: serial@ff1a0000 {
 214                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 215                 reg = <0x0 0xff1a0000 0x0 0x100>;
 216                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 217                 clock-names = "baudclk", "apb_pclk";
 218                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 219                 reg-shift = <2>;
 220                 reg-io-width = <4>;
 221                 status = "disabled";
 222         };
 223
 224         uart3: serial@ff1b0000 {
 225                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 226                 reg = <0x0 0xff1b0000 0x0 0x100>;
 227                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 228                 clock-names = "baudclk", "apb_pclk";
 229                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 230                 reg-shift = <2>;
 231                 reg-io-width = <4>;
 232                 status = "disabled";
 233         };
 234
 235         spi0: spi@ff1c0000 {
 236                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 237                 reg = <0x0 0xff110000 0x0 0x1000>;
 238                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 239                 clock-names = "spiclk", "apb_pclk";
 240                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 241                 pinctrl-names = "default";
 242                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 status = "disabled";
 246         };
 247
 248         spi1: spi@ff1d0000 {
 249                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 250                 reg = <0x0 0xff120000 0x0 0x1000>;
 251                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 252                 clock-names = "spiclk", "apb_pclk";
 253                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 254                 pinctrl-names = "default";
 255                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 status = "disabled";
 259         };
 260
 261         spi2: spi@ff1e0000 {
 262                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 263                 reg = <0x0 0xff130000 0x0 0x1000>;
 264                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 265                 clock-names = "spiclk", "apb_pclk";
 266                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 267                 pinctrl-names = "default";
 268                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 status = "disabled";
 272         };
 273
 274         spi4: spi@ff1f0000 {
 275                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 276                 reg = <0x0 0xff120000 0x0 0x1000>;
 277                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 278                 clock-names = "spiclk", "apb_pclk";
 279                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 280                 pinctrl-names = "default";
 281                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 status = "disabled";
 285         };
 286
 287         spi5: spi@ff200000 {
 288                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 289                 reg = <0x0 0xff130000 0x0 0x1000>;
 290                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 291                 clock-names = "spiclk", "apb_pclk";
 292                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 status = "disabled";
 298         };
 299
 300         pmugrf: syscon@ff320000 {
 301                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 302                 reg = <0x0 0xff320000 0x0 0x1000>;
 303         };
 304
 305         spi3: spi@ff350000 {
 306                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 307                 reg = <0x0 0xff110000 0x0 0x1000>;
 308                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 309                 clock-names = "spiclk", "apb_pclk";
 310                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 status = "disabled";
 316         };
 317
 318         uart4: serial@ff370000 {
 319                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 320                 reg = <0x0 0xff370000 0x0 0x100>;
 321                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 322                 clock-names = "baudclk", "apb_pclk";
 323                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 324                 reg-shift = <2>;
 325                 reg-io-width = <4>;
 326                 status = "disabled";
 327         };
 328
 329         pmucru: pmu-clock-controller@ff750000 {
 330                 compatible = "rockchip,rk3399-pmucru";
 331                 reg = <0x0 0xff750000 0x0 0x1000>;
 332                 rockchip,grf = <&pmugrf>;
 333                 #clock-cells = <1>;
 334                 #reset-cells = <1>;
 335         };
 336
 337         cru: clock-controller@ff760000 {
 338                 compatible = "rockchip,rk3399-cru";
 339                 reg = <0x0 0xff760000 0x0 0x1000>;
 340                 rockchip,grf = <&grf>;
 341                 #clock-cells = <1>;
 342                 #reset-cells = <1>;
 343         };
 344
 345         grf: syscon@ff770000 {
 346                 compatible = "rockchip,rk3399-grf", "syscon";
 347                 reg = <0x0 0xff770000 0x0 0x10000>;
 348         };
 349
 350         spdif: spdif@ff870000 {
 351                 compatible = "rockchip,rk3399-spdif";
 352                 reg = <0x0 0xff870000 0x0 0x1000>;
 353                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 354                 dmas = <&dmac_bus 7>;
 355                 dma-names = "tx";
 356                 clock-names = "hclk", "mclk";
 357                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&spdif_bus>;
 360                 status = "disabled";
 361         };
 362
 363         i2s0: i2s@ff880000 {
 364                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 365                 reg = <0x0 0xff880000 0x0 0x1000>;
 366                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 370                 dma-names = "tx", "rx";
 371                 clock-names = "i2s_hclk", "i2s_clk";
 372                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&i2s0_8ch_bus>;
 375                 status = "disabled";
 376         };
 377
 378         i2s1: i2s@ff890000 {
 379                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 380                 reg = <0x0 0xff890000 0x0 0x1000>;
 381                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 385                 dma-names = "tx", "rx";
 386                 clock-names = "i2s_hclk", "i2s_clk";
 387                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&i2s1_2ch_bus>;
 390                 status = "disabled";
 391         };
 392
 393         i2s2: i2s@ff8a0000 {
 394                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 395                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 396                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 400                 dma-names = "tx", "rx";
 401                 clock-names = "i2s_hclk", "i2s_clk";
 402                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 403                 status = "disabled";
 404         };
 405
 406         pinctrl: pinctrl {
 407                 compatible = "rockchip,rk3399-pinctrl";
 408                 rockchip,grf = <&grf>;
 409                 rockchip,pmu = <&pmugrf>;
 410                 #address-cells = <0x2>;
 411                 #size-cells = <0x2>;
 412                 ranges;
 413
 414                 gpio0: gpio0@ff720000 {
 415                         compatible = "rockchip,gpio-bank";
 416                         reg = <0x0 0xff720000 0x0 0x100>;
 417                         clocks = <&xin24m>;
 418                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 419
 420                         gpio-controller;
 421                         #gpio-cells = <0x2>;
 422
 423                         interrupt-controller;
 424                         #interrupt-cells = <0x2>;
 425                 };
 426
 427                 gpio1: gpio1@ff730000 {
 428                         compatible = "rockchip,gpio-bank";
 429                         reg = <0x0 0xff730000 0x0 0x100>;
 430                         clocks = <&xin24m>;
 431                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 432
 433                         gpio-controller;
 434                         #gpio-cells = <0x2>;
 435
 436                         interrupt-controller;
 437                         #interrupt-cells = <0x2>;
 438                 };
 439
 440                 gpio2: gpio2@ff780000 {
 441                         compatible = "rockchip,gpio-bank";
 442                         reg = <0x0 0xff780000 0x0 0x100>;
 443                         clocks = <&xin24m>;
 444                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 445
 446                         gpio-controller;
 447                         #gpio-cells = <0x2>;
 448
 449                         interrupt-controller;
 450                         #interrupt-cells = <0x2>;
 451                 };
 452
 453                 gpio3: gpio3@ff788000 {
 454                         compatible = "rockchip,gpio-bank";
 455                         reg = <0x0 0xff788000 0x0 0x100>;
 456                         clocks = <&xin24m>;
 457                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 458
 459                         gpio-controller;
 460                         #gpio-cells = <0x2>;
 461
 462                         interrupt-controller;
 463                         #interrupt-cells = <0x2>;
 464                 };
 465
 466                 gpio4: gpio4@ff790000 {
 467                         compatible = "rockchip,gpio-bank";
 468                         reg = <0x0 0xff790000 0x0 0x100>;
 469                         clocks = <&xin24m>;
 470                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 471
 472                         gpio-controller;
 473                         #gpio-cells = <0x2>;
 474
 475                         interrupt-controller;
 476                         #interrupt-cells = <0x2>;
 477                 };
 478
 479                 pcfg_pull_up: pcfg-pull-up {
 480                         bias-pull-up;
 481                 };
 482
 483                 pcfg_pull_down: pcfg-pull-down {
 484                         bias-pull-down;
 485                 };
 486
 487                 pcfg_pull_none: pcfg-pull-none {
 488                         bias-disable;
 489                 };
 490
 491                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 492                         bias-disable;
 493                         drive-strength = <12>;
 494                 };
 495
 496                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 497                         bias-pull-up;
 498                         drive-strength = <8>;
 499                 };
 500
 501                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 502                         bias-pull-down;
 503                         drive-strength = <4>;
 504                 };
 505
 506                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 507                         bias-pull-up;
 508                         drive-strength = <2>;
 509                 };
 510
 511                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 512                         bias-pull-down;
 513                         drive-strength = <12>;
 514                 };
 515
 516                 emmc {
 517                         emmc_pwr: emmc-pwr {
 518                                 rockchip,pins =
 519                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 520                         };
 521                 };
 522
 523                 gmac {
 524                         rgmii_pins: rgmii-pins {
 525                                 rockchip,pins =
 526                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 527                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 528                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 529                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 530                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 531                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 532                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 533                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 534                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 535                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 536                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 537                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 538                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 539                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 540                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 541                         };
 542
 543                         rmii_pins: rmii-pins {
 544                                 rockchip,pins =
 545                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 546                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 547                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 548                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 549                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 550                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 551                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 552                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 553                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 554                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 555                         };
 556                 };
 557
 558                 i2c0 {
 559                         i2c0_xfer: i2c0-xfer {
 560                                 rockchip,pins =
 561                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 562                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 563                         };
 564                 };
 565
 566                 i2c1 {
 567                         i2c1_xfer: i2c1-xfer {
 568                                 rockchip,pins =
 569                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 570                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 571                         };
 572                 };
 573
 574                 i2c2 {
 575                         i2c2_xfer: i2c2-xfer {
 576                                 rockchip,pins =
 577                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 578                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 579                         };
 580                 };
 581
 582                 i2c3 {
 583                         i2c3_xfer: i2c3-xfer {
 584                                 rockchip,pins =
 585                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 586                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 587                         };
 588                 };
 589
 590                 i2c4 {
 591                         i2c4_xfer: i2c4-xfer {
 592                                 rockchip,pins =
 593                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 594                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 595                         };
 596                 };
 597
 598                 i2c5 {
 599                         i2c5_xfer: i2c5-xfer {
 600                                 rockchip,pins =
 601                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 602                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 603                         };
 604                 };
 605
 606                 i2c6 {
 607                         i2c6_xfer: i2c6-xfer {
 608                                 rockchip,pins =
 609                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 610                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 611                         };
 612                 };
 613
 614                 i2c7 {
 615                         i2c7_xfer: i2c7-xfer {
 616                                 rockchip,pins =
 617                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 618                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 619                         };
 620                 };
 621
 622                 i2c8 {
 623                         i2c8_xfer: i2c8-xfer {
 624                                 rockchip,pins =
 625                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 626                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 627                         };
 628                 };
 629
 630                 i2s0 {
 631                         i2s0_8ch_bus: i2s0-8ch-bus {
 632                                 rockchip,pins =
 633                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 634                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 635                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 636                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 637                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 638                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 639                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 640                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 641                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 642                         };
 643                 };
 644
 645                 i2s1 {
 646                         i2s1_2ch_bus: i2s1-2ch-bus {
 647                                 rockchip,pins =
 648                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 649                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 650                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 651                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 652                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 653                         };
 654                 };
 655
 656                 sdio0 {
 657                         sdio0_bus1: sdio0-bus1 {
 658                                 rockchip,pins =
 659                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 660                         };
 661
 662                         sdio0_bus4: sdio0-bus4 {
 663                                 rockchip,pins =
 664                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 665                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 666                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 667                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 668                         };
 669
 670                         sdio0_cmd: sdio0-cmd {
 671                                 rockchip,pins =
 672                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 673                         };
 674
 675                         sdio0_clk: sdio0-clk {
 676                                 rockchip,pins =
 677                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 678                         };
 679
 680                         sdio0_cd: sdio0-cd {
 681                                 rockchip,pins =
 682                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 683                         };
 684
 685                         sdio0_pwr: sdio0-pwr {
 686                                 rockchip,pins =
 687                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
 688                         };
 689
 690                         sdio0_bkpwr: sdio0-bkpwr {
 691                                 rockchip,pins =
 692                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
 693                         };
 694
 695                         sdio0_wp: sdio0-wp {
 696                                 rockchip,pins =
 697                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
 698                         };
 699
 700                         sdio0_int: sdio0-int {
 701                                 rockchip,pins =
 702                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
 703                         };
 704                 };
 705
 706                 sdmmc {
 707                         sdmmc_bus1: sdmmc-bus1 {
 708                                 rockchip,pins =
 709                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 710                         };
 711
 712                         sdmmc_bus4: sdmmc-bus4 {
 713                                 rockchip,pins =
 714                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 715                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 716                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 717                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 718                         };
 719
 720                         sdmmc_clk: sdmmc-clk {
 721                                 rockchip,pins =
 722                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 723                         };
 724
 725                         sdmmc_cmd: sdmmc-cmd {
 726                                 rockchip,pins =
 727                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 728                         };
 729
 730                         sdmmc_cd: sdmcc-cd {
 731                                 rockchip,pins =
 732                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 733                         };
 734
 735                         sdmmc_wp: sdmmc-wp {
 736                                 rockchip,pins =
 737                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 738                         };
 739                 };
 740
 741                 spdif {
 742                         spdif_bus: spdif-bus {
 743                                 rockchip,pins =
 744                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 745                         };
 746                 };
 747
 748                 spi0 {
 749                         spi0_clk: spi0-clk {
 750                                 rockchip,pins =
 751                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 752                         };
 753                         spi0_cs0: spi0-cs0 {
 754                                 rockchip,pins =
 755                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 756                         };
 757                         spi0_cs1: spi0-cs1 {
 758                                 rockchip,pins =
 759                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 760                         };
 761                         spi0_tx: spi0-tx {
 762                                 rockchip,pins =
 763                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 764                         };
 765                         spi0_rx: spi0-rx {
 766                                 rockchip,pins =
 767                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 768                         };
 769                 };
 770
 771                 spi1 {
 772                         spi1_clk: spi1-clk {
 773                                 rockchip,pins =
 774                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 775                         };
 776                         spi1_cs0: spi1-cs0 {
 777                                 rockchip,pins =
 778                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 779                         };
 780                         spi1_rx: spi1-rx {
 781                                 rockchip,pins =
 782                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 783                         };
 784                         spi1_tx: spi1-tx {
 785                                 rockchip,pins =
 786                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 787                         };
 788                 };
 789
 790                 spi2 {
 791                         spi2_clk: spi2-clk {
 792                                 rockchip,pins =
 793                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 794                         };
 795                         spi2_cs0: spi2-cs0 {
 796                                 rockchip,pins =
 797                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 798                         };
 799                         spi2_rx: spi2-rx {
 800                                 rockchip,pins =
 801                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 802                         };
 803                         spi2_tx: spi2-tx {
 804                                 rockchip,pins =
 805                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 806                         };
 807                 };
 808
 809                 spi3 {
 810                         spi3_clk: spi3-clk {
 811                                 rockchip,pins =
 812                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
 813                         };
 814                         spi3_cs0: spi3-cs0 {
 815                                 rockchip,pins =
 816                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
 817                         };
 818                         spi3_rx: spi3-rx {
 819                                 rockchip,pins =
 820                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
 821                         };
 822                         spi3_tx: spi3-tx {
 823                                 rockchip,pins =
 824                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
 825                         };
 826                 };
 827
 828                 spi4 {
 829                         spi4_clk: spi4-clk {
 830                                 rockchip,pins =
 831                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
 832                         };
 833                         spi4_cs0: spi4-cs0 {
 834                                 rockchip,pins =
 835                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
 836                         };
 837                         spi4_rx: spi4-rx {
 838                                 rockchip,pins =
 839                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
 840                         };
 841                         spi4_tx: spi4-tx {
 842                                 rockchip,pins =
 843                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
 844                         };
 845                 };
 846
 847                 spi5 {
 848                         spi5_clk: spi5-clk {
 849                                 rockchip,pins =
 850                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
 851                         };
 852                         spi5_cs0: spi5-cs0 {
 853                                 rockchip,pins =
 854                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
 855                         };
 856                         spi5_rx: spi5-rx {
 857                                 rockchip,pins =
 858                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
 859                         };
 860                         spi5_tx: spi5-tx {
 861                                 rockchip,pins =
 862                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 863                         };
 864                 };
 865
 866                 uart0 {
 867                         uart0_xfer: uart0-xfer {
 868                                 rockchip,pins =
 869                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
 870                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 871                         };
 872
 873                         uart0_cts: uart0-cts {
 874                                 rockchip,pins =
 875                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 876                         };
 877
 878                         uart0_rts: uart0-rts {
 879                                 rockchip,pins =
 880                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 881                         };
 882                 };
 883
 884                 uart1 {
 885                         uart1_xfer: uart1-xfer {
 886                                 rockchip,pins =
 887                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
 888                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
 889                         };
 890                 };
 891
 892                 uart2a {
 893                         uart2a_xfer: uart2a-xfer {
 894                                 rockchip,pins =
 895                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
 896                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
 897                         };
 898                 };
 899
 900                 uart2b {
 901                         uart2b_xfer: uart2b-xfer {
 902                                 rockchip,pins =
 903                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
 904                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
 905                         };
 906                 };
 907
 908                 uart2c {
 909                         uart2c_xfer: uart2c-xfer {
 910                                 rockchip,pins =
 911                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
 912                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
 913                         };
 914                 };
 915
 916                 uart3 {
 917                         uart3_xfer: uart3-xfer {
 918                                 rockchip,pins =
 919                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
 920                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
 921                         };
 922
 923                         uart3_cts: uart3-cts {
 924                                 rockchip,pins =
 925                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
 926                         };
 927
 928                         uart3_rts: uart3-rts {
 929                                 rockchip,pins =
 930                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
 931                         };
 932                 };
 933
 934                 uart4 {
 935                         uart4_xfer: uart4-xfer {
 936                                 rockchip,pins =
 937                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
 938                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 939                         };
 940                 };
 941
 942                 uarthdcp {
 943                         uarthdcp_xfer: uarthdcp-xfer {
 944                                 rockchip,pins =
 945                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
 946                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
 947                         };
 948                 };
 949
 950                 pwm0 {
 951                         pwm0_pin: pwm0-pin {
 952                                 rockchip,pins =
 953                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
 954                         };
 955
 956                         vop0_pwm_pin: vop0-pwm-pin {
 957                                 rockchip,pins =
 958                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
 959                         };
 960                 };
 961
 962                 pwm1 {
 963                         pwm1_pin: pwm1-pin {
 964                                 rockchip,pins =
 965                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
 966                         };
 967
 968                         vop1_pwm_pin: vop1-pwm-pin {
 969                                 rockchip,pins =
 970                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
 971                         };
 972                 };
 973         };
 974 };