arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&cpu_sleep>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 124                 };
 125
 126                 cpu_l1: cpu@1 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x1>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         cpu-idle-states = <&cpu_sleep>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         operating-points-v2 = <&cluster0_opp>;
 145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 146                 };
 147
 148                 cpu_l3: cpu@3 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a53", "arm,armv8";
 151                         reg = <0x0 0x3>;
 152                         enable-method = "psci";
 153                         clocks = <&cru ARMCLKL>;
 154                         cpu-idle-states = <&cpu_sleep>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 157                 };
 158
 159                 cpu_b0: cpu@100 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a72", "arm,armv8";
 162                         reg = <0x0 0x100>;
 163                         enable-method = "psci";
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <436>;
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&cpu_sleep>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 170                 };
 171
 172                 cpu_b1: cpu@101 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a72", "arm,armv8";
 175                         reg = <0x0 0x101>;
 176                         enable-method = "psci";
 177                         clocks = <&cru ARMCLKB>;
 178                         cpu-idle-states = <&cpu_sleep>;
 179                         operating-points-v2 = <&cluster1_opp>;
 180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 181                 };
 182
 183                 idle-states {
 184                         entry-method = "psci";
 185                         cpu_sleep: cpu-sleep-0 {
 186                                 compatible = "arm,idle-state";
 187                                 local-timer-stop;
 188                                 arm,psci-suspend-param = <0x0010000>;
 189                                 entry-latency-us = <350>;
 190                                 exit-latency-us = <600>;
 191                                 min-residency-us = <1150>;
 192                         };
 193                 };
 194
 195                 /include/ "rk3399-sched-energy.dtsi"
 196
 197         };
 198
 199         cluster0_opp: opp_table0 {
 200                 compatible = "operating-points-v2";
 201                 opp-shared;
 202
 203                 opp@408000000 {
 204                         opp-hz = /bits/ 64 <408000000>;
 205                         opp-microvolt = <800000>;
 206                         clock-latency-ns = <40000>;
 207                 };
 208                 opp@600000000 {
 209                         opp-hz = /bits/ 64 <600000000>;
 210                         opp-microvolt = <800000>;
 211                 };
 212                 opp@816000000 {
 213                         opp-hz = /bits/ 64 <816000000>;
 214                         opp-microvolt = <800000>;
 215                 };
 216                 opp@1008000000 {
 217                         opp-hz = /bits/ 64 <1008000000>;
 218                         opp-microvolt = <875000>;
 219                 };
 220                 opp@1200000000 {
 221                         opp-hz = /bits/ 64 <1200000000>;
 222                         opp-microvolt = <925000>;
 223                 };
 224                 opp@1416000000 {
 225                         opp-hz = /bits/ 64 <1416000000>;
 226                         opp-microvolt = <1025000>;
 227                 };
 228         };
 229
 230         cluster1_opp: opp_table1 {
 231                 compatible = "operating-points-v2";
 232                 opp-shared;
 233
 234                 opp@408000000 {
 235                         opp-hz = /bits/ 64 <408000000>;
 236                         opp-microvolt = <800000>;
 237                         clock-latency-ns = <40000>;
 238                 };
 239                 opp@600000000 {
 240                         opp-hz = /bits/ 64 <600000000>;
 241                         opp-microvolt = <800000>;
 242                 };
 243                 opp@816000000 {
 244                         opp-hz = /bits/ 64 <816000000>;
 245                         opp-microvolt = <800000>;
 246                 };
 247                 opp@1008000000 {
 248                         opp-hz = /bits/ 64 <1008000000>;
 249                         opp-microvolt = <850000>;
 250                 };
 251                 opp@1200000000 {
 252                         opp-hz = /bits/ 64 <1200000000>;
 253                         opp-microvolt = <925000>;
 254                 };
 255         };
 256
 257         cpu_avs: cpu-avs {
 258                 cluster0-avs {
 259                         cluster-id = <0>;
 260                         min-volt = <800000>; /* uV */
 261                         min-freq = <408000>; /* KHz */
 262                         leakage-adjust-volt = <
 263                         /*  mA        mA         uV */
 264                             0         254        0
 265                         >;
 266                         nvmem-cells = <&cpul_leakage>;
 267                         nvmem-cell-names = "cpu_leakage";
 268                 };
 269                 cluster1-avs {
 270                         cluster-id = <1>;
 271                         min-volt = <800000>; /* uV */
 272                         min-freq = <408000>; /* KHz */
 273                         leakage-adjust-volt = <
 274                         /*  mA        mA         uV */
 275                             0         254        0
 276                         >;
 277                         nvmem-cells = <&cpub_leakage>;
 278                         nvmem-cell-names = "cpu_leakage";
 279                 };
 280         };
 281
 282         timer {
 283                 compatible = "arm,armv8-timer";
 284                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 285                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 286                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 287                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 288         };
 289
 290         pmu_a53 {
 291                 compatible = "arm,cortex-a53-pmu";
 292                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 293         };
 294
 295         pmu_a72 {
 296                 compatible = "arm,cortex-a72-pmu";
 297                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 298         };
 299
 300         xin24m: xin24m {
 301                 compatible = "fixed-clock";
 302                 #clock-cells = <0>;
 303                 clock-frequency = <24000000>;
 304                 clock-output-names = "xin24m";
 305         };
 306
 307         amba {
 308                 compatible = "arm,amba-bus";
 309                 #address-cells = <2>;
 310                 #size-cells = <2>;
 311                 ranges;
 312
 313                 dmac_bus: dma-controller@ff6d0000 {
 314                         compatible = "arm,pl330", "arm,primecell";
 315                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 316                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 317                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 318                         #dma-cells = <1>;
 319                         clocks = <&cru ACLK_DMAC0_PERILP>;
 320                         clock-names = "apb_pclk";
 321                         peripherals-req-type-burst;
 322                 };
 323
 324                 dmac_peri: dma-controller@ff6e0000 {
 325                         compatible = "arm,pl330", "arm,primecell";
 326                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 327                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 328                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 329                         #dma-cells = <1>;
 330                         clocks = <&cru ACLK_DMAC1_PERILP>;
 331                         clock-names = "apb_pclk";
 332                         peripherals-req-type-burst;
 333                 };
 334         };
 335
 336         gmac: eth@fe300000 {
 337                 compatible = "rockchip,rk3399-gmac";
 338                 reg = <0x0 0xfe300000 0x0 0x10000>;
 339                 rockchip,grf = <&grf>;
 340                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 341                 interrupt-names = "macirq";
 342                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 343                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 344                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 345                          <&cru PCLK_GMAC>;
 346                 clock-names = "stmmaceth", "mac_clk_rx",
 347                               "mac_clk_tx", "clk_mac_ref",
 348                               "clk_mac_refout", "aclk_mac",
 349                               "pclk_mac";
 350                 resets = <&cru SRST_A_GMAC>;
 351                 reset-names = "stmmaceth";
 352                 power-domains = <&power RK3399_PD_GMAC>;
 353                 status = "disabled";
 354         };
 355
 356         sdio0: dwmmc@fe310000 {
 357                 compatible = "rockchip,rk3399-dw-mshc",
 358                              "rockchip,rk3288-dw-mshc";
 359                 reg = <0x0 0xfe310000 0x0 0x4000>;
 360                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 361                 clock-freq-min-max = <400000 150000000>;
 362                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 363                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 364                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 365                 fifo-depth = <0x100>;
 366                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 367                 status = "disabled";
 368         };
 369
 370         sdmmc: dwmmc@fe320000 {
 371                 compatible = "rockchip,rk3399-dw-mshc",
 372                              "rockchip,rk3288-dw-mshc";
 373                 reg = <0x0 0xfe320000 0x0 0x4000>;
 374                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 375                 clock-freq-min-max = <400000 150000000>;
 376                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 377                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 378                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 379                 fifo-depth = <0x100>;
 380                 power-domains = <&power RK3399_PD_SD>;
 381                 status = "disabled";
 382         };
 383
 384         sdhci: sdhci@fe330000 {
 385                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 386                 reg = <0x0 0xfe330000 0x0 0x10000>;
 387                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 388                 arasan,soc-ctl-syscon = <&grf>;
 389                 assigned-clocks = <&cru SCLK_EMMC>;
 390                 assigned-clock-rates = <200000000>;
 391                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 392                 clock-names = "clk_xin", "clk_ahb";
 393                 clock-output-names = "emmc_cardclock";
 394                 #clock-cells = <0>;
 395                 phys = <&emmc_phy>;
 396                 phy-names = "phy_arasan";
 397                 power-domains = <&power RK3399_PD_EMMC>;
 398                 status = "disabled";
 399         };
 400
 401         usb_host0_ehci: usb@fe380000 {
 402                 compatible = "generic-ehci";
 403                 reg = <0x0 0xfe380000 0x0 0x20000>;
 404                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 405                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 406                          <&cru SCLK_USBPHY0_480M_SRC>;
 407                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 408                 phys = <&u2phy0_host>;
 409                 phy-names = "usb";
 410                 power-domains = <&power RK3399_PD_PERIHP>;
 411                 status = "disabled";
 412         };
 413
 414         usb_host0_ohci: usb@fe3a0000 {
 415                 compatible = "generic-ohci";
 416                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 417                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 418                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 419                          <&cru SCLK_USBPHY0_480M_SRC>;
 420                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 421                 phys = <&u2phy0_host>;
 422                 phy-names = "usb";
 423                 power-domains = <&power RK3399_PD_PERIHP>;
 424                 status = "disabled";
 425         };
 426
 427         usb_host1_ehci: usb@fe3c0000 {
 428                 compatible = "generic-ehci";
 429                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 430                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 431                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 432                          <&cru SCLK_USBPHY1_480M_SRC>;
 433                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 434                 phys = <&u2phy1_host>;
 435                 phy-names = "usb";
 436                 power-domains = <&power RK3399_PD_PERIHP>;
 437                 status = "disabled";
 438         };
 439
 440         usb_host1_ohci: usb@fe3e0000 {
 441                 compatible = "generic-ohci";
 442                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 443                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 444                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 445                          <&cru SCLK_USBPHY1_480M_SRC>;
 446                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 447                 phys = <&u2phy1_host>;
 448                 phy-names = "usb";
 449                 power-domains = <&power RK3399_PD_PERIHP>;
 450                 status = "disabled";
 451         };
 452
 453         usbdrd3_0: usb@fe800000 {
 454                 compatible = "rockchip,rk3399-dwc3";
 455                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 456                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 457                 clock-names = "ref_clk", "suspend_clk",
 458                               "bus_clk", "grf_clk";
 459                 power-domains = <&power RK3399_PD_USB3>;
 460                 resets = <&cru SRST_A_USB3_OTG0>;
 461                 reset-names = "usb3-otg";
 462                 #address-cells = <2>;
 463                 #size-cells = <2>;
 464                 ranges;
 465                 status = "disabled";
 466                 usbdrd_dwc3_0: dwc3@fe800000 {
 467                         compatible = "snps,dwc3";
 468                         reg = <0x0 0xfe800000 0x0 0x100000>;
 469                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 470                         dr_mode = "otg";
 471                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 472                         phy-names = "usb2-phy", "usb3-phy";
 473                         phy_type = "utmi_wide";
 474                         snps,dis_enblslpm_quirk;
 475                         snps,dis-u2-freeclk-exists-quirk;
 476                         snps,dis_u2_susphy_quirk;
 477                         snps,dis-del-phy-power-chg-quirk;
 478                         snps,xhci-slow-suspend-quirk;
 479                         status = "disabled";
 480                 };
 481         };
 482
 483         usbdrd3_1: usb@fe900000 {
 484                 compatible = "rockchip,rk3399-dwc3";
 485                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 486                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 487                 clock-names = "ref_clk", "suspend_clk",
 488                               "bus_clk", "grf_clk";
 489                 power-domains = <&power RK3399_PD_USB3>;
 490                 resets = <&cru SRST_A_USB3_OTG1>;
 491                 reset-names = "usb3-otg";
 492                 #address-cells = <2>;
 493                 #size-cells = <2>;
 494                 ranges;
 495                 status = "disabled";
 496                 usbdrd_dwc3_1: dwc3@fe900000 {
 497                         compatible = "snps,dwc3";
 498                         reg = <0x0 0xfe900000 0x0 0x100000>;
 499                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 500                         dr_mode = "host";
 501                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 502                         phy-names = "usb2-phy", "usb3-phy";
 503                         phy_type = "utmi_wide";
 504                         snps,dis_enblslpm_quirk;
 505                         snps,dis-u2-freeclk-exists-quirk;
 506                         snps,dis_u2_susphy_quirk;
 507                         snps,dis-del-phy-power-chg-quirk;
 508                         snps,xhci-slow-suspend-quirk;
 509                         status = "disabled";
 510                 };
 511         };
 512
 513         gic: interrupt-controller@fee00000 {
 514                 compatible = "arm,gic-v3";
 515                 #interrupt-cells = <4>;
 516                 #address-cells = <2>;
 517                 #size-cells = <2>;
 518                 ranges;
 519                 interrupt-controller;
 520
 521                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 522                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 523                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 524                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 525                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 526                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 527                 its: interrupt-controller@fee20000 {
 528                         compatible = "arm,gic-v3-its";
 529                         msi-controller;
 530                         reg = <0x0 0xfee20000 0x0 0x20000>;
 531                 };
 532
 533                 ppi-partitions {
 534                         part0: interrupt-partition-0 {
 535                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 536                         };
 537
 538                         part1: interrupt-partition-1 {
 539                                 affinity = <&cpu_b0 &cpu_b1>;
 540                         };
 541                 };
 542         };
 543
 544         saradc: saradc@ff100000 {
 545                 compatible = "rockchip,rk3399-saradc";
 546                 reg = <0x0 0xff100000 0x0 0x100>;
 547                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 548                 #io-channel-cells = <1>;
 549                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 550                 clock-names = "saradc", "apb_pclk";
 551                 status = "disabled";
 552         };
 553
 554         i2c0: i2c@ff3c0000 {
 555                 compatible = "rockchip,rk3399-i2c";
 556                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 557                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 558                 clock-names = "i2c", "pclk";
 559                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&i2c0_xfer>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 status = "disabled";
 565         };
 566
 567         i2c1: i2c@ff110000 {
 568                 compatible = "rockchip,rk3399-i2c";
 569                 reg = <0x0 0xff110000 0x0 0x1000>;
 570                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 571                 clock-names = "i2c", "pclk";
 572                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&i2c1_xfer>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 status = "disabled";
 578         };
 579
 580         i2c2: i2c@ff120000 {
 581                 compatible = "rockchip,rk3399-i2c";
 582                 reg = <0x0 0xff120000 0x0 0x1000>;
 583                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 584                 clock-names = "i2c", "pclk";
 585                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&i2c2_xfer>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 status = "disabled";
 591         };
 592
 593         i2c3: i2c@ff130000 {
 594                 compatible = "rockchip,rk3399-i2c";
 595                 reg = <0x0 0xff130000 0x0 0x1000>;
 596                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 597                 clock-names = "i2c", "pclk";
 598                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&i2c3_xfer>;
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 status = "disabled";
 604         };
 605
 606         i2c5: i2c@ff140000 {
 607                 compatible = "rockchip,rk3399-i2c";
 608                 reg = <0x0 0xff140000 0x0 0x1000>;
 609                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 610                 clock-names = "i2c", "pclk";
 611                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 612                 pinctrl-names = "default";
 613                 pinctrl-0 = <&i2c5_xfer>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 status = "disabled";
 617         };
 618
 619         i2c6: i2c@ff150000 {
 620                 compatible = "rockchip,rk3399-i2c";
 621                 reg = <0x0 0xff150000 0x0 0x1000>;
 622                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 623                 clock-names = "i2c", "pclk";
 624                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&i2c6_xfer>;
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 status = "disabled";
 630         };
 631
 632         i2c7: i2c@ff160000 {
 633                 compatible = "rockchip,rk3399-i2c";
 634                 reg = <0x0 0xff160000 0x0 0x1000>;
 635                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 636                 clock-names = "i2c", "pclk";
 637                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&i2c7_xfer>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 status = "disabled";
 643         };
 644
 645         uart0: serial@ff180000 {
 646                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 647                 reg = <0x0 0xff180000 0x0 0x100>;
 648                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 649                 clock-names = "baudclk", "apb_pclk";
 650                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 651                 reg-shift = <2>;
 652                 reg-io-width = <4>;
 653                 pinctrl-names = "default";
 654                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 655                 status = "disabled";
 656         };
 657
 658         uart1: serial@ff190000 {
 659                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 660                 reg = <0x0 0xff190000 0x0 0x100>;
 661                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 662                 clock-names = "baudclk", "apb_pclk";
 663                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 664                 reg-shift = <2>;
 665                 reg-io-width = <4>;
 666                 pinctrl-names = "default";
 667                 pinctrl-0 = <&uart1_xfer>;
 668                 status = "disabled";
 669         };
 670
 671         uart2: serial@ff1a0000 {
 672                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 673                 reg = <0x0 0xff1a0000 0x0 0x100>;
 674                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 675                 clock-names = "baudclk", "apb_pclk";
 676                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 677                 reg-shift = <2>;
 678                 reg-io-width = <4>;
 679                 pinctrl-names = "default";
 680                 pinctrl-0 = <&uart2c_xfer>;
 681                 status = "disabled";
 682         };
 683
 684         uart3: serial@ff1b0000 {
 685                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 686                 reg = <0x0 0xff1b0000 0x0 0x100>;
 687                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 688                 clock-names = "baudclk", "apb_pclk";
 689                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 690                 reg-shift = <2>;
 691                 reg-io-width = <4>;
 692                 pinctrl-names = "default";
 693                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 694                 status = "disabled";
 695         };
 696
 697         spi0: spi@ff1c0000 {
 698                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 699                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 700                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 701                 clock-names = "spiclk", "apb_pclk";
 702                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 703                 pinctrl-names = "default";
 704                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 705                 #address-cells = <1>;
 706                 #size-cells = <0>;
 707                 status = "disabled";
 708         };
 709
 710         spi1: spi@ff1d0000 {
 711                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 712                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 713                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 714                 clock-names = "spiclk", "apb_pclk";
 715                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 716                 pinctrl-names = "default";
 717                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 718                 #address-cells = <1>;
 719                 #size-cells = <0>;
 720                 status = "disabled";
 721         };
 722
 723         spi2: spi@ff1e0000 {
 724                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 725                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 726                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 727                 clock-names = "spiclk", "apb_pclk";
 728                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 729                 pinctrl-names = "default";
 730                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 731                 #address-cells = <1>;
 732                 #size-cells = <0>;
 733                 status = "disabled";
 734         };
 735
 736         spi4: spi@ff1f0000 {
 737                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 738                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 739                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 740                 clock-names = "spiclk", "apb_pclk";
 741                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 742                 pinctrl-names = "default";
 743                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 744                 #address-cells = <1>;
 745                 #size-cells = <0>;
 746                 status = "disabled";
 747         };
 748
 749         spi5: spi@ff200000 {
 750                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 751                 reg = <0x0 0xff200000 0x0 0x1000>;
 752                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 753                 clock-names = "spiclk", "apb_pclk";
 754                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 757                 #address-cells = <1>;
 758                 #size-cells = <0>;
 759                 status = "disabled";
 760         };
 761
 762         thermal-zones {
 763                 soc_thermal: soc-thermal {
 764                         polling-delay-passive = <20>; /* milliseconds */
 765                         polling-delay = <1000>; /* milliseconds */
 766                         sustainable-power = <1000>; /* milliwatts */
 767
 768                         thermal-sensors = <&tsadc 0>;
 769
 770                         trips {
 771                                 threshold: trip-point@0 {
 772                                         temperature = <70000>; /* millicelsius */
 773                                         hysteresis = <2000>; /* millicelsius */
 774                                         type = "passive";
 775                                 };
 776                                 target: trip-point@1 {
 777                                         temperature = <85000>; /* millicelsius */
 778                                         hysteresis = <2000>; /* millicelsius */
 779                                         type = "passive";
 780                                 };
 781                                 soc_crit: soc-crit {
 782                                         temperature = <95000>; /* millicelsius */
 783                                         hysteresis = <2000>; /* millicelsius */
 784                                         type = "critical";
 785                                 };
 786                         };
 787
 788                         cooling-maps {
 789                                 map0 {
 790                                         trip = <&target>;
 791                                         cooling-device =
 792                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 793                                         contribution = <4096>;
 794                                 };
 795                                 map1 {
 796                                         trip = <&target>;
 797                                         cooling-device =
 798                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 799                                         contribution = <1024>;
 800                                 };
 801                                 map2 {
 802                                         trip = <&target>;
 803                                         cooling-device =
 804                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 805                                         contribution = <4096>;
 806                                 };
 807                         };
 808                 };
 809
 810                 gpu_thermal: gpu-thermal {
 811                         polling-delay-passive = <100>; /* milliseconds */
 812                         polling-delay = <1000>; /* milliseconds */
 813
 814                         thermal-sensors = <&tsadc 1>;
 815                 };
 816         };
 817
 818         tsadc: tsadc@ff260000 {
 819                 compatible = "rockchip,rk3399-tsadc";
 820                 reg = <0x0 0xff260000 0x0 0x100>;
 821                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 822                 rockchip,grf = <&grf>;
 823                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 824                 clock-names = "tsadc", "apb_pclk";
 825                 assigned-clocks = <&cru SCLK_TSADC>;
 826                 assigned-clock-rates = <750000>;
 827                 resets = <&cru SRST_TSADC>;
 828                 reset-names = "tsadc-apb";
 829                 pinctrl-names = "init", "default", "sleep";
 830                 pinctrl-0 = <&otp_gpio>;
 831                 pinctrl-1 = <&otp_out>;
 832                 pinctrl-2 = <&otp_gpio>;
 833                 #thermal-sensor-cells = <1>;
 834                 rockchip,hw-tshut-temp = <95000>;
 835                 status = "disabled";
 836         };
 837
 838         qos_emmc: qos@ffa58000 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa58000 0x0 0x20>;
 841         };
 842
 843         qos_gmac: qos@ffa5c000 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa5c000 0x0 0x20>;
 846         };
 847
 848         qos_pcie: qos@ffa60080 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa60080 0x0 0x20>;
 851         };
 852
 853         qos_usb_host0: qos@ffa60100 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa60100 0x0 0x20>;
 856         };
 857
 858         qos_usb_host1: qos@ffa60180 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa60180 0x0 0x20>;
 861         };
 862
 863         qos_usb_otg0: qos@ffa70000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa70000 0x0 0x20>;
 866         };
 867
 868         qos_usb_otg1: qos@ffa70080 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffa70080 0x0 0x20>;
 871         };
 872
 873         qos_sd: qos@ffa74000 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffa74000 0x0 0x20>;
 876         };
 877
 878         qos_sdioaudio: qos@ffa76000 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffa76000 0x0 0x20>;
 881         };
 882
 883         qos_hdcp: qos@ffa90000 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffa90000 0x0 0x20>;
 886         };
 887
 888         qos_iep: qos@ffa98000 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffa98000 0x0 0x20>;
 891         };
 892
 893         qos_isp0_m0: qos@ffaa0000 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffaa0000 0x0 0x20>;
 896         };
 897
 898         qos_isp0_m1: qos@ffaa0080 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffaa0080 0x0 0x20>;
 901         };
 902
 903         qos_isp1_m0: qos@ffaa8000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffaa8000 0x0 0x20>;
 906         };
 907
 908         qos_isp1_m1: qos@ffaa8080 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffaa8080 0x0 0x20>;
 911         };
 912
 913         qos_rga_r: qos@ffab0000 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffab0000 0x0 0x20>;
 916         };
 917
 918         qos_rga_w: qos@ffab0080 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffab0080 0x0 0x20>;
 921         };
 922
 923         qos_video_m0: qos@ffab8000 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffab8000 0x0 0x20>;
 926         };
 927
 928         qos_video_m1_r: qos@ffac0000 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffac0000 0x0 0x20>;
 931         };
 932
 933         qos_video_m1_w: qos@ffac0080 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffac0080 0x0 0x20>;
 936         };
 937
 938         qos_vop_big_r: qos@ffac8000 {
 939                 compatible = "syscon";
 940                 reg = <0x0 0xffac8000 0x0 0x20>;
 941         };
 942
 943         qos_vop_big_w: qos@ffac8080 {
 944                 compatible = "syscon";
 945                 reg = <0x0 0xffac8080 0x0 0x20>;
 946         };
 947
 948         qos_vop_little: qos@ffad0000 {
 949                 compatible = "syscon";
 950                 reg = <0x0 0xffad0000 0x0 0x20>;
 951         };
 952
 953         qos_perihp: qos@ffad8080 {
 954                 compatible = "syscon";
 955                 reg = <0x0 0xffad8080 0x0 0x20>;
 956         };
 957
 958         qos_gpu: qos@ffae0000 {
 959                 compatible = "syscon";
 960                 reg = <0x0 0xffae0000 0x0 0x20>;
 961         };
 962
 963         pmu: power-management@ff310000 {
 964                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 965                 reg = <0x0 0xff310000 0x0 0x1000>;
 966
 967                 /*
 968                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 969                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 970                  * Some of the power domains are grouped together for every
 971                  * voltage domain.
 972                  * The detail contents as below.
 973                  */
 974                 power: power-controller {
 975                         compatible = "rockchip,rk3399-power-controller";
 976                         #power-domain-cells = <1>;
 977                         #address-cells = <1>;
 978                         #size-cells = <0>;
 979
 980                         /* These power domains are grouped by VD_CENTER */
 981                         pd_iep@RK3399_PD_IEP {
 982                                 reg = <RK3399_PD_IEP>;
 983                                 clocks = <&cru ACLK_IEP>,
 984                                          <&cru HCLK_IEP>;
 985                                 pm_qos = <&qos_iep>;
 986                         };
 987                         pd_rga@RK3399_PD_RGA {
 988                                 reg = <RK3399_PD_RGA>;
 989                                 clocks = <&cru ACLK_RGA>,
 990                                          <&cru HCLK_RGA>;
 991                                 pm_qos = <&qos_rga_r>,
 992                                          <&qos_rga_w>;
 993                         };
 994                         pd_vcodec@RK3399_PD_VCODEC {
 995                                 reg = <RK3399_PD_VCODEC>;
 996                                 clocks = <&cru ACLK_VCODEC>,
 997                                          <&cru HCLK_VCODEC>;
 998                                 pm_qos = <&qos_video_m0>;
 999                         };
1000                         pd_vdu@RK3399_PD_VDU {
1001                                 reg = <RK3399_PD_VDU>;
1002                                 clocks = <&cru ACLK_VDU>,
1003                                          <&cru HCLK_VDU>;
1004                                 pm_qos = <&qos_video_m1_r>,
1005                                          <&qos_video_m1_w>;
1006                         };
1007
1008                         /* These power domains are grouped by VD_GPU */
1009                         pd_gpu@RK3399_PD_GPU {
1010                                 reg = <RK3399_PD_GPU>;
1011                                 clocks = <&cru ACLK_GPU>;
1012                                 pm_qos = <&qos_gpu>;
1013                         };
1014
1015                         /* These power domains are grouped by VD_LOGIC */
1016                         pd_edp@RK3399_PD_EDP {
1017                                 reg = <RK3399_PD_EDP>;
1018                                 clocks = <&cru PCLK_EDP_CTRL>;
1019                         };
1020                         pd_emmc@RK3399_PD_EMMC {
1021                                 reg = <RK3399_PD_EMMC>;
1022                                 clocks = <&cru ACLK_EMMC>;
1023                                 pm_qos = <&qos_emmc>;
1024                         };
1025                         pd_gmac@RK3399_PD_GMAC {
1026                                 reg = <RK3399_PD_GMAC>;
1027                                 clocks = <&cru ACLK_GMAC>;
1028                                 pm_qos = <&qos_gmac>;
1029                         };
1030                         pd_perihp@RK3399_PD_PERIHP {
1031                                 reg = <RK3399_PD_PERIHP>;
1032                                 #address-cells = <1>;
1033                                 #size-cells = <0>;
1034                                 clocks = <&cru ACLK_PERIHP>;
1035                                 pm_qos = <&qos_perihp>,
1036                                          <&qos_pcie>,
1037                                          <&qos_usb_host0>,
1038                                          <&qos_usb_host1>;
1039
1040                                 pd_sd@RK3399_PD_SD {
1041                                         reg = <RK3399_PD_SD>;
1042                                         clocks = <&cru HCLK_SDMMC>,
1043                                                  <&cru SCLK_SDMMC>;
1044                                         pm_qos = <&qos_sd>;
1045                                 };
1046                         };
1047                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1048                                 reg = <RK3399_PD_SDIOAUDIO>;
1049                                 clocks = <&cru HCLK_SDIO>;
1050                                 pm_qos = <&qos_sdioaudio>;
1051                         };
1052                         pd_usb3@RK3399_PD_USB3 {
1053                                 reg = <RK3399_PD_USB3>;
1054                                 clocks = <&cru ACLK_USB3>;
1055                                 pm_qos = <&qos_usb_otg0>,
1056                                          <&qos_usb_otg1>;
1057                         };
1058                         pd_vio@RK3399_PD_VIO {
1059                                 reg = <RK3399_PD_VIO>;
1060                                 #address-cells = <1>;
1061                                 #size-cells = <0>;
1062
1063                                 pd_hdcp@RK3399_PD_HDCP {
1064                                         reg = <RK3399_PD_HDCP>;
1065                                         clocks = <&cru ACLK_HDCP>,
1066                                                  <&cru HCLK_HDCP>,
1067                                                  <&cru PCLK_HDCP>;
1068                                         pm_qos = <&qos_hdcp>;
1069                                 };
1070                                 pd_isp0@RK3399_PD_ISP0 {
1071                                         reg = <RK3399_PD_ISP0>;
1072                                         clocks = <&cru ACLK_ISP0>,
1073                                                  <&cru HCLK_ISP0>;
1074                                         pm_qos = <&qos_isp0_m0>,
1075                                                  <&qos_isp0_m1>;
1076                                 };
1077                                 pd_isp1@RK3399_PD_ISP1 {
1078                                         reg = <RK3399_PD_ISP1>;
1079                                         clocks = <&cru ACLK_ISP1>,
1080                                                  <&cru HCLK_ISP1>;
1081                                         pm_qos = <&qos_isp1_m0>,
1082                                                  <&qos_isp1_m1>;
1083                                 };
1084                                 pd_vo@RK3399_PD_VO {
1085                                         reg = <RK3399_PD_VO>;
1086                                         #address-cells = <1>;
1087                                         #size-cells = <0>;
1088
1089                                         pd_vopb@RK3399_PD_VOPB {
1090                                                 reg = <RK3399_PD_VOPB>;
1091                                                 clocks = <&cru ACLK_VOP0>,
1092                                                          <&cru HCLK_VOP0>;
1093                                                 pm_qos = <&qos_vop_big_r>,
1094                                                          <&qos_vop_big_w>;
1095                                         };
1096                                         pd_vopl@RK3399_PD_VOPL {
1097                                                 reg = <RK3399_PD_VOPL>;
1098                                                 clocks = <&cru ACLK_VOP1>,
1099                                                          <&cru HCLK_VOP1>;
1100                                                 pm_qos = <&qos_vop_little>;
1101                                         };
1102                                 };
1103                         };
1104                 };
1105         };
1106
1107         pmugrf: syscon@ff320000 {
1108                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1109                 reg = <0x0 0xff320000 0x0 0x1000>;
1110
1111                 reboot-mode {
1112                         compatible = "syscon-reboot-mode";
1113                         offset = <0x300>;
1114                         mode-bootloader = <BOOT_LOADER>;
1115                         mode-charge = <BOOT_CHARGING>;
1116                         mode-fastboot = <BOOT_FASTBOOT>;
1117                         mode-loader = <BOOT_LOADER>;
1118                         mode-normal = <BOOT_NORMAL>;
1119                         mode-recovery = <BOOT_RECOVERY>;
1120                         mode-ums = <BOOT_UMS>;
1121                 };
1122         };
1123
1124         spi3: spi@ff350000 {
1125                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1126                 reg = <0x0 0xff350000 0x0 0x1000>;
1127                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1128                 clock-names = "spiclk", "apb_pclk";
1129                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1130                 pinctrl-names = "default";
1131                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1132                 #address-cells = <1>;
1133                 #size-cells = <0>;
1134                 status = "disabled";
1135         };
1136
1137         uart4: serial@ff370000 {
1138                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1139                 reg = <0x0 0xff370000 0x0 0x100>;
1140                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1141                 clock-names = "baudclk", "apb_pclk";
1142                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1143                 reg-shift = <2>;
1144                 reg-io-width = <4>;
1145                 pinctrl-names = "default";
1146                 pinctrl-0 = <&uart4_xfer>;
1147                 status = "disabled";
1148         };
1149
1150         i2c4: i2c@ff3d0000 {
1151                 compatible = "rockchip,rk3399-i2c";
1152                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1153                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1154                 clock-names = "i2c", "pclk";
1155                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1156                 pinctrl-names = "default";
1157                 pinctrl-0 = <&i2c4_xfer>;
1158                 #address-cells = <1>;
1159                 #size-cells = <0>;
1160                 status = "disabled";
1161         };
1162
1163         i2c8: i2c@ff3e0000 {
1164                 compatible = "rockchip,rk3399-i2c";
1165                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1166                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1167                 clock-names = "i2c", "pclk";
1168                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1169                 pinctrl-names = "default";
1170                 pinctrl-0 = <&i2c8_xfer>;
1171                 #address-cells = <1>;
1172                 #size-cells = <0>;
1173                 status = "disabled";
1174         };
1175
1176         pcie_phy: phy@e220 {
1177                 compatible = "rockchip,rk3399-pcie-phy";
1178                 #phy-cells = <0>;
1179                 rockchip,grf = <&grf>;
1180                 clocks = <&cru SCLK_PCIEPHY_REF>;
1181                 clock-names = "refclk";
1182                 resets = <&cru SRST_PCIEPHY>;
1183                 reset-names = "phy";
1184                 status = "disabled";
1185         };
1186
1187         pcie0: pcie@f8000000 {
1188                 compatible = "rockchip,rk3399-pcie";
1189                 #address-cells = <3>;
1190                 #size-cells = <2>;
1191                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1192                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1193                 clock-names = "aclk", "aclk-perf",
1194                               "hclk", "pm";
1195                 bus-range = <0x0 0x1>;
1196                 msi-map = <0x0 &its 0x0 0x1000>;
1197                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1198                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1199                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1200                 interrupt-names = "sys", "legacy", "client";
1201                 #interrupt-cells = <1>;
1202                 interrupt-map-mask = <0 0 0 7>;
1203                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1204                                 <0 0 0 2 &pcie0_intc 1>,
1205                                 <0 0 0 3 &pcie0_intc 2>,
1206                                 <0 0 0 4 &pcie0_intc 3>;
1207                 phys = <&pcie_phy>;
1208                 phy-names = "pcie-phy";
1209                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1210                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1211                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1212                       <0x0 0xfd000000 0x0 0x1000000>;
1213                 reg-names = "axi-base", "apb-base";
1214                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1215                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1216                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1217                 status = "disabled";
1218                 pcie0_intc: interrupt-controller {
1219                         interrupt-controller;
1220                         #address-cells = <0>;
1221                         #interrupt-cells = <1>;
1222                 };
1223         };
1224
1225         pwm0: pwm@ff420000 {
1226                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1227                 reg = <0x0 0xff420000 0x0 0x10>;
1228                 #pwm-cells = <3>;
1229                 pinctrl-names = "default";
1230                 pinctrl-0 = <&pwm0_pin>;
1231                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1232                 clock-names = "pwm";
1233                 status = "disabled";
1234         };
1235
1236         pwm1: pwm@ff420010 {
1237                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1238                 reg = <0x0 0xff420010 0x0 0x10>;
1239                 #pwm-cells = <3>;
1240                 pinctrl-names = "default";
1241                 pinctrl-0 = <&pwm1_pin>;
1242                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1243                 clock-names = "pwm";
1244                 status = "disabled";
1245         };
1246
1247         pwm2: pwm@ff420020 {
1248                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1249                 reg = <0x0 0xff420020 0x0 0x10>;
1250                 #pwm-cells = <3>;
1251                 pinctrl-names = "default";
1252                 pinctrl-0 = <&pwm2_pin>;
1253                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1254                 clock-names = "pwm";
1255                 status = "disabled";
1256         };
1257
1258         pwm3: pwm@ff420030 {
1259                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1260                 reg = <0x0 0xff420030 0x0 0x10>;
1261                 #pwm-cells = <3>;
1262                 pinctrl-names = "default";
1263                 pinctrl-0 = <&pwm3a_pin>;
1264                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1265                 clock-names = "pwm";
1266                 status = "disabled";
1267         };
1268
1269         dfi: dfi@ff630000 {
1270                 reg = <0x00 0xff630000 0x00 0x4000>;
1271                 compatible = "rockchip,rk3399-dfi";
1272                 rockchip,pmu = <&pmugrf>;
1273                 clocks = <&cru PCLK_DDR_MON>;
1274                 clock-names = "pclk_ddr_mon";
1275                 status = "disabled";
1276         };
1277
1278         dmc: dmc {
1279                 compatible = "rockchip,rk3399-dmc";
1280                 devfreq-events = <&dfi>;
1281                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1282                 clocks = <&cru SCLK_DDRCLK>;
1283                 clock-names = "dmc_clk";
1284                 ddr_timing = <&ddr_timing>;
1285                 operating-points-v2 = <&dmc_opp_table>;
1286                 status = "disabled";
1287         };
1288
1289         dmc_opp_table: dmc_opp_table {
1290                 compatible = "operating-points-v2";
1291
1292                 opp00 {
1293                         opp-hz = /bits/ 64 <666000000>;
1294                         opp-microvolt = <900000>;
1295                 };
1296         };
1297
1298         rga: rga@ff680000 {
1299                 compatible = "rockchip,rk3399-rga";
1300                 reg = <0x0 0xff680000 0x0 0x10000>;
1301                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1302                 interrupt-names = "rga";
1303                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1304                 clock-names = "aclk", "hclk", "sclk";
1305                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1306                 reset-names = "core", "axi", "ahb";
1307                 power-domains = <&power RK3399_PD_RGA>;
1308                 status = "disabled";
1309         };
1310
1311         efuse0: efuse@ff690000 {
1312                 compatible = "rockchip,rk3399-efuse";
1313                 reg = <0x0 0xff690000 0x0 0x80>;
1314                 #address-cells = <1>;
1315                 #size-cells = <1>;
1316                 clocks = <&cru PCLK_EFUSE1024NS>;
1317                 clock-names = "pclk_efuse";
1318
1319                 /* Data cells */
1320                 cpul_leakage: cpul-leakage {
1321                         reg = <0x1a 0x1>;
1322                 };
1323                 cpub_leakage: cpub-leakage {
1324                         reg = <0x17 0x1>;
1325                 };
1326                 gpu_leakage: gpu-leakage {
1327                         reg = <0x18 0x1>;
1328                 };
1329                 center_leakage: center-leakage {
1330                         reg = <0x19 0x1>;
1331                 };
1332                 logic_leakage: logic-leakage {
1333                         reg = <0x1b 0x1>;
1334                 };
1335                 wafer_info: wafer-info {
1336                         reg = <0x1c 0x1>;
1337                 };
1338         };
1339
1340         pmucru: pmu-clock-controller@ff750000 {
1341                 compatible = "rockchip,rk3399-pmucru";
1342                 reg = <0x0 0xff750000 0x0 0x1000>;
1343                 #clock-cells = <1>;
1344                 #reset-cells = <1>;
1345                 assigned-clocks = <&pmucru PLL_PPLL>;
1346                 assigned-clock-rates = <676000000>;
1347         };
1348
1349         cru: clock-controller@ff760000 {
1350                 compatible = "rockchip,rk3399-cru";
1351                 reg = <0x0 0xff760000 0x0 0x1000>;
1352                 #clock-cells = <1>;
1353                 #reset-cells = <1>;
1354                 assigned-clocks =
1355                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1356                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1357                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1358                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1359                         <&cru PLL_NPLL>,
1360                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1361                         <&cru PCLK_PERIHP>,
1362                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1363                         <&cru PCLK_PERILP0>,
1364                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1365                 assigned-clock-rates =
1366                          <400000000>,  <200000000>,
1367                          <400000000>,  <200000000>,
1368                          <816000000>, <816000000>,
1369                          <594000000>,  <800000000>,
1370                         <1000000000>,
1371                          <150000000>,   <75000000>,
1372                           <37500000>,
1373                          <100000000>,  <100000000>,
1374                           <50000000>,
1375                          <100000000>,   <50000000>;
1376         };
1377
1378         grf: syscon@ff770000 {
1379                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1380                 reg = <0x0 0xff770000 0x0 0x10000>;
1381                 #address-cells = <1>;
1382                 #size-cells = <1>;
1383
1384                 emmc_phy: phy@f780 {
1385                         compatible = "rockchip,rk3399-emmc-phy";
1386                         reg = <0xf780 0x24>;
1387                         clocks = <&sdhci>;
1388                         clock-names = "emmcclk";
1389                         #phy-cells = <0>;
1390                         status = "disabled";
1391                 };
1392
1393                 u2phy0: usb2-phy@e450 {
1394                         compatible = "rockchip,rk3399-usb2phy";
1395                         reg = <0xe450 0x10>;
1396                         clocks = <&cru SCLK_USB2PHY0_REF>;
1397                         clock-names = "phyclk";
1398                         #clock-cells = <0>;
1399                         clock-output-names = "clk_usbphy0_480m";
1400                         status = "disabled";
1401
1402                         u2phy0_otg: otg-port {
1403                                 #phy-cells = <0>;
1404                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1405                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1406                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1407                                 interrupt-names = "otg-bvalid", "otg-id",
1408                                                   "linestate";
1409                                 status = "disabled";
1410                         };
1411
1412                         u2phy0_host: host-port {
1413                                 #phy-cells = <0>;
1414                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1415                                 interrupt-names = "linestate";
1416                                 status = "disabled";
1417                         };
1418                 };
1419
1420                 u2phy1: usb2-phy@e460 {
1421                         compatible = "rockchip,rk3399-usb2phy";
1422                         reg = <0xe460 0x10>;
1423                         clocks = <&cru SCLK_USB2PHY1_REF>;
1424                         clock-names = "phyclk";
1425                         #clock-cells = <0>;
1426                         clock-output-names = "clk_usbphy1_480m";
1427                         status = "disabled";
1428
1429                         u2phy1_otg: otg-port {
1430                                 #phy-cells = <0>;
1431                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1432                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1433                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1434                                 interrupt-names = "otg-bvalid", "otg-id",
1435                                                   "linestate";
1436                                 status = "disabled";
1437                         };
1438
1439                         u2phy1_host: host-port {
1440                                 #phy-cells = <0>;
1441                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1442                                 interrupt-names = "linestate";
1443                                 status = "disabled";
1444                         };
1445                 };
1446         };
1447
1448         tcphy0: phy@ff7c0000 {
1449                 compatible = "rockchip,rk3399-typec-phy";
1450                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1451                 rockchip,grf = <&grf>;
1452                 #phy-cells = <1>;
1453                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1454                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1455                 clock-names = "tcpdcore", "tcpdphy-ref";
1456                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1457                 assigned-clock-rates = <50000000>;
1458                 resets = <&cru SRST_UPHY0>,
1459                          <&cru SRST_UPHY0_PIPE_L00>,
1460                          <&cru SRST_P_UPHY0_TCPHY>;
1461                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1462                 rockchip,typec-conn-dir = <0xe580 0 16>;
1463                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1464                 rockchip,usb3-host-disable = <0x2434 0 16>;
1465                 rockchip,usb3-host-port = <0x2434 12 28>;
1466                 rockchip,external-psm = <0xe588 14 30>;
1467                 rockchip,pipe-status = <0xe5c0 0 0>;
1468                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1469                 status = "disabled";
1470
1471                 tcphy0_dp: dp-port {
1472                         #phy-cells = <0>;
1473                 };
1474
1475                 tcphy0_usb3: usb3-port {
1476                         #phy-cells = <0>;
1477                 };
1478         };
1479
1480         tcphy1: phy@ff800000 {
1481                 compatible = "rockchip,rk3399-typec-phy";
1482                 reg = <0x0 0xff800000 0x0 0x40000>;
1483                 rockchip,grf = <&grf>;
1484                 #phy-cells = <1>;
1485                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1486                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1487                 clock-names = "tcpdcore", "tcpdphy-ref";
1488                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1489                 assigned-clock-rates = <50000000>;
1490                 resets = <&cru SRST_UPHY1>,
1491                          <&cru SRST_UPHY1_PIPE_L00>,
1492                          <&cru SRST_P_UPHY1_TCPHY>;
1493                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1494                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1495                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1496                 rockchip,usb3-host-disable = <0x2444 0 16>;
1497                 rockchip,usb3-host-port = <0x2444 12 28>;
1498                 rockchip,external-psm = <0xe594 14 30>;
1499                 rockchip,pipe-status = <0xe5c0 16 16>;
1500                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1501                 status = "disabled";
1502
1503                 tcphy1_dp: dp-port {
1504                         #phy-cells = <0>;
1505                 };
1506
1507                 tcphy1_usb3: usb3-port {
1508                         #phy-cells = <0>;
1509                 };
1510         };
1511
1512         watchdog@ff848000 {
1513                 compatible = "snps,dw-wdt";
1514                 reg = <0x0 0xff848000 0x0 0x100>;
1515                 clocks = <&cru PCLK_WDT>;
1516                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1517         };
1518
1519         rktimer: rktimer@ff850000 {
1520                 compatible = "rockchip,rk3399-timer";
1521                 reg = <0x0 0xff850000 0x0 0x1000>;
1522                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1523                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1524                 clock-names = "pclk", "timer";
1525         };
1526
1527         spdif: spdif@ff870000 {
1528                 compatible = "rockchip,rk3399-spdif";
1529                 reg = <0x0 0xff870000 0x0 0x1000>;
1530                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1531                 dmas = <&dmac_bus 7>;
1532                 dma-names = "tx";
1533                 clock-names = "mclk", "hclk";
1534                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1535                 pinctrl-names = "default";
1536                 pinctrl-0 = <&spdif_bus>;
1537                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1538                 status = "disabled";
1539         };
1540
1541         i2s0: i2s@ff880000 {
1542                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1543                 reg = <0x0 0xff880000 0x0 0x1000>;
1544                 rockchip,grf = <&grf>;
1545                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1546                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1547                 dma-names = "tx", "rx";
1548                 clock-names = "i2s_clk", "i2s_hclk";
1549                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1550                 pinctrl-names = "default";
1551                 pinctrl-0 = <&i2s0_8ch_bus>;
1552                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1553                 status = "disabled";
1554         };
1555
1556         i2s1: i2s@ff890000 {
1557                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1558                 reg = <0x0 0xff890000 0x0 0x1000>;
1559                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1560                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1561                 dma-names = "tx", "rx";
1562                 clock-names = "i2s_clk", "i2s_hclk";
1563                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1564                 pinctrl-names = "default";
1565                 pinctrl-0 = <&i2s1_2ch_bus>;
1566                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1567                 status = "disabled";
1568         };
1569
1570         i2s2: i2s@ff8a0000 {
1571                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1572                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1573                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1574                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1575                 dma-names = "tx", "rx";
1576                 clock-names = "i2s_clk", "i2s_hclk";
1577                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1578                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1579                 status = "disabled";
1580         };
1581
1582         gpu: gpu@ff9a0000 {
1583                 compatible = "arm,malit860",
1584                              "arm,malit86x",
1585                              "arm,malit8xx",
1586                              "arm,mali-midgard";
1587
1588                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1589
1590                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1591                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1592                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1593                 interrupt-names = "GPU", "JOB", "MMU";
1594
1595                 clocks = <&cru ACLK_GPU>;
1596                 clock-names = "clk_mali";
1597                 #cooling-cells = <2>; /* min followed by max */
1598                 operating-points-v2 = <&gpu_opp_table>;
1599                 power-domains = <&power RK3399_PD_GPU>;
1600                 power-off-delay-ms = <200>;
1601                 status = "disabled";
1602
1603                 gpu_power_model: power_model {
1604                         compatible = "arm,mali-simple-power-model";
1605                         voltage = <900>;
1606                         frequency = <500>;
1607                         static-power = <300>;
1608                         dynamic-power = <396>;
1609                         ts = <32000 4700 (-80) 2>;
1610                         thermal-zone = "gpu-thermal";
1611                 };
1612         };
1613
1614         gpu_opp_table: gpu_opp_table {
1615                 compatible = "operating-points-v2";
1616                 opp-shared;
1617
1618                 opp@200000000 {
1619                         opp-hz = /bits/ 64 <200000000>;
1620                         opp-microvolt = <900000>;
1621                 };
1622                 opp@300000000 {
1623                         opp-hz = /bits/ 64 <300000000>;
1624                         opp-microvolt = <900000>;
1625                 };
1626                 opp@400000000 {
1627                         opp-hz = /bits/ 64 <400000000>;
1628                         opp-microvolt = <900000>;
1629                 };
1630
1631         };
1632
1633         vopl: vop@ff8f0000 {
1634                 compatible = "rockchip,rk3399-vop-lit";
1635                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1636                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1637                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1638                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1639                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1640                 reset-names = "axi", "ahb", "dclk";
1641                 power-domains = <&power RK3399_PD_VOPL>;
1642                 iommus = <&vopl_mmu>;
1643                 status = "disabled";
1644
1645                 vopl_out: port {
1646                         #address-cells = <1>;
1647                         #size-cells = <0>;
1648
1649                         vopl_out_mipi: endpoint@0 {
1650                                 reg = <0>;
1651                                 remote-endpoint = <&mipi_in_vopl>;
1652                         };
1653
1654                         vopl_out_edp: endpoint@1 {
1655                                 reg = <1>;
1656                                 remote-endpoint = <&edp_in_vopl>;
1657                         };
1658
1659                         vopl_out_hdmi: endpoint@2 {
1660                                 reg = <2>;
1661                                 remote-endpoint = <&hdmi_in_vopl>;
1662                         };
1663                 };
1664         };
1665
1666         vop1_pwm: voppwm@ff8f01a0 {
1667                 compatible = "rockchip,vop-pwm";
1668                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1669                 #pwm-cells = <3>;
1670                 pinctrl-names = "default";
1671                 pinctrl-0 = <&vop1_pwm_pin>;
1672                 clocks = <&cru SCLK_VOP1_PWM>;
1673                 clock-names = "pwm";
1674                 status = "disabled";
1675         };
1676
1677         vopl_mmu: iommu@ff8f3f00 {
1678                 compatible = "rockchip,iommu";
1679                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1680                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1681                 interrupt-names = "vopl_mmu";
1682                 #iommu-cells = <0>;
1683                 status = "disabled";
1684         };
1685
1686         vopb: vop@ff900000 {
1687                 compatible = "rockchip,rk3399-vop-big";
1688                 reg = <0x0 0xff900000 0x0 0x3efc>;
1689                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1690                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1691                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1692                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1693                 reset-names = "axi", "ahb", "dclk";
1694                 power-domains = <&power RK3399_PD_VOPB>;
1695                 iommus = <&vopb_mmu>;
1696                 status = "disabled";
1697
1698                 vopb_out: port {
1699                         #address-cells = <1>;
1700                         #size-cells = <0>;
1701
1702                         vopb_out_edp: endpoint@0 {
1703                                 reg = <0>;
1704                                 remote-endpoint = <&edp_in_vopb>;
1705                         };
1706
1707                         vopb_out_mipi: endpoint@1 {
1708                                 reg = <1>;
1709                                 remote-endpoint = <&mipi_in_vopb>;
1710                         };
1711
1712                         vopb_out_hdmi: endpoint@2 {
1713                                 reg = <2>;
1714                                 remote-endpoint = <&hdmi_in_vopb>;
1715                         };
1716                 };
1717         };
1718
1719         vop0_pwm: voppwm@ff9001a0 {
1720                 compatible = "rockchip,vop-pwm";
1721                 reg = <0x0 0xff9001a0 0x0 0x10>;
1722                 #pwm-cells = <3>;
1723                 pinctrl-names = "default";
1724                 pinctrl-0 = <&vop0_pwm_pin>;
1725                 clocks = <&cru SCLK_VOP0_PWM>;
1726                 clock-names = "pwm";
1727                 status = "disabled";
1728         };
1729
1730         vopb_mmu: iommu@ff903f00 {
1731                 compatible = "rockchip,iommu";
1732                 reg = <0x0 0xff903f00 0x0 0x100>;
1733                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1734                 interrupt-names = "vopb_mmu";
1735                 #iommu-cells = <0>;
1736                 status = "disabled";
1737         };
1738
1739         hdmi: hdmi@ff940000 {
1740                 compatible = "rockchip,rk3399-dw-hdmi";
1741                 reg = <0x0 0xff940000 0x0 0x20000>;
1742                 reg-io-width = <4>;
1743                 rockchip,grf = <&grf>;
1744                 power-domains = <&power RK3399_PD_HDCP>;
1745                 pinctrl-names = "default";
1746                 pinctrl-0 = <&hdmi_i2c_xfer>;
1747                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1748                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1749                 clock-names = "iahb", "isfr", "vpll", "grf";
1750                 status = "disabled";
1751
1752                 ports {
1753                         hdmi_in: port {
1754                                 #address-cells = <1>;
1755                                 #size-cells = <0>;
1756                                 hdmi_in_vopb: endpoint@0 {
1757                                         reg = <0>;
1758                                         remote-endpoint = <&vopb_out_hdmi>;
1759                                 };
1760                                 hdmi_in_vopl: endpoint@1 {
1761                                         reg = <1>;
1762                                         remote-endpoint = <&vopl_out_hdmi>;
1763                                 };
1764                         };
1765                 };
1766         };
1767
1768         mipi_dsi: mipi@ff960000 {
1769                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1770                 reg = <0x0 0xff960000 0x0 0x8000>;
1771                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1772                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1773                          <&cru SCLK_DPHY_TX0_CFG>;
1774                 clock-names = "ref", "pclk", "phy_cfg";
1775                 power-domains = <&power RK3399_PD_VIO>;
1776                 rockchip,grf = <&grf>;
1777                 #address-cells = <1>;
1778                 #size-cells = <0>;
1779                 status = "disabled";
1780
1781                 ports {
1782                         #address-cells = <1>;
1783                         #size-cells = <0>;
1784                         reg = <1>;
1785
1786                         mipi_in: port {
1787                                 #address-cells = <1>;
1788                                 #size-cells = <0>;
1789
1790                                 mipi_in_vopb: endpoint@0 {
1791                                         reg = <0>;
1792                                         remote-endpoint = <&vopb_out_mipi>;
1793                                 };
1794                                 mipi_in_vopl: endpoint@1 {
1795                                         reg = <1>;
1796                                         remote-endpoint = <&vopl_out_mipi>;
1797                                 };
1798                         };
1799                 };
1800         };
1801
1802         edp: edp@ff970000 {
1803                 compatible = "rockchip,rk3399-edp";
1804                 reg = <0x0 0xff970000 0x0 0x8000>;
1805                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1806                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1807                 clock-names = "dp", "pclk";
1808                 power-domains = <&power RK3399_PD_EDP>;
1809                 resets = <&cru SRST_P_EDP_CTRL>;
1810                 reset-names = "dp";
1811                 rockchip,grf = <&grf>;
1812                 status = "disabled";
1813                 pinctrl-names = "default";
1814                 pinctrl-0 = <&edp_hpd>;
1815
1816                 ports {
1817                         #address-cells = <1>;
1818                         #size-cells = <0>;
1819
1820                         edp_in: port@0 {
1821                                 reg = <0>;
1822                                 #address-cells = <1>;
1823                                 #size-cells = <0>;
1824
1825                                 edp_in_vopb: endpoint@0 {
1826                                         reg = <0>;
1827                                         remote-endpoint = <&vopb_out_edp>;
1828                                 };
1829
1830                                 edp_in_vopl: endpoint@1 {
1831                                         reg = <1>;
1832                                         remote-endpoint = <&vopl_out_edp>;
1833                                 };
1834                         };
1835                 };
1836         };
1837
1838         display_subsystem: display-subsystem {
1839                 compatible = "rockchip,display-subsystem";
1840                 ports = <&vopl_out>, <&vopb_out>;
1841                 status = "disabled";
1842         };
1843
1844         pinctrl: pinctrl {
1845                 compatible = "rockchip,rk3399-pinctrl";
1846                 rockchip,grf = <&grf>;
1847                 rockchip,pmu = <&pmugrf>;
1848                 #address-cells = <0x2>;
1849                 #size-cells = <0x2>;
1850                 ranges;
1851
1852                 gpio0: gpio0@ff720000 {
1853                         compatible = "rockchip,gpio-bank";
1854                         reg = <0x0 0xff720000 0x0 0x100>;
1855                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1856                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1857
1858                         gpio-controller;
1859                         #gpio-cells = <0x2>;
1860
1861                         interrupt-controller;
1862                         #interrupt-cells = <0x2>;
1863                 };
1864
1865                 gpio1: gpio1@ff730000 {
1866                         compatible = "rockchip,gpio-bank";
1867                         reg = <0x0 0xff730000 0x0 0x100>;
1868                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1869                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1870
1871                         gpio-controller;
1872                         #gpio-cells = <0x2>;
1873
1874                         interrupt-controller;
1875                         #interrupt-cells = <0x2>;
1876                 };
1877
1878                 gpio2: gpio2@ff780000 {
1879                         compatible = "rockchip,gpio-bank";
1880                         reg = <0x0 0xff780000 0x0 0x100>;
1881                         clocks = <&cru PCLK_GPIO2>;
1882                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1883
1884                         gpio-controller;
1885                         #gpio-cells = <0x2>;
1886
1887                         interrupt-controller;
1888                         #interrupt-cells = <0x2>;
1889                 };
1890
1891                 gpio3: gpio3@ff788000 {
1892                         compatible = "rockchip,gpio-bank";
1893                         reg = <0x0 0xff788000 0x0 0x100>;
1894                         clocks = <&cru PCLK_GPIO3>;
1895                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1896
1897                         gpio-controller;
1898                         #gpio-cells = <0x2>;
1899
1900                         interrupt-controller;
1901                         #interrupt-cells = <0x2>;
1902                 };
1903
1904                 gpio4: gpio4@ff790000 {
1905                         compatible = "rockchip,gpio-bank";
1906                         reg = <0x0 0xff790000 0x0 0x100>;
1907                         clocks = <&cru PCLK_GPIO4>;
1908                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1909
1910                         gpio-controller;
1911                         #gpio-cells = <0x2>;
1912
1913                         interrupt-controller;
1914                         #interrupt-cells = <0x2>;
1915                 };
1916
1917                 pcfg_pull_up: pcfg-pull-up {
1918                         bias-pull-up;
1919                 };
1920
1921                 pcfg_pull_down: pcfg-pull-down {
1922                         bias-pull-down;
1923                 };
1924
1925                 pcfg_pull_none: pcfg-pull-none {
1926                         bias-disable;
1927                 };
1928
1929                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1930                         bias-pull-up;
1931                         drive-strength = <20>;
1932                 };
1933
1934                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1935                         bias-disable;
1936                         drive-strength = <20>;
1937                 };
1938
1939                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1940                         bias-disable;
1941                         drive-strength = <18>;
1942                 };
1943
1944                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1945                         bias-disable;
1946                         drive-strength = <12>;
1947                 };
1948
1949                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1950                         bias-pull-up;
1951                         drive-strength = <8>;
1952                 };
1953
1954                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1955                         bias-pull-down;
1956                         drive-strength = <4>;
1957                 };
1958
1959                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1960                         bias-pull-up;
1961                         drive-strength = <2>;
1962                 };
1963
1964                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1965                         bias-pull-down;
1966                         drive-strength = <12>;
1967                 };
1968
1969                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1970                         bias-disable;
1971                         drive-strength = <13>;
1972                 };
1973
1974                 pcfg_output_high: pcfg-output-high {
1975                         output-high;
1976                 };
1977
1978                 pcfg_output_low: pcfg-output-low {
1979                         output-low;
1980                 };
1981
1982                 pcfg_input: pcfg-input {
1983                         input-enable;
1984                 };
1985
1986                 emmc {
1987                         emmc_pwr: emmc-pwr {
1988                                 rockchip,pins =
1989                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1990                         };
1991                 };
1992
1993                 gmac {
1994                         rgmii_pins: rgmii-pins {
1995                                 rockchip,pins =
1996                                         /* mac_txclk */
1997                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1998                                         /* mac_rxclk */
1999                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2000                                         /* mac_mdio */
2001                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2002                                         /* mac_txen */
2003                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2004                                         /* mac_clk */
2005                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2006                                         /* mac_rxdv */
2007                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2008                                         /* mac_mdc */
2009                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2010                                         /* mac_rxd1 */
2011                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2012                                         /* mac_rxd0 */
2013                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2014                                         /* mac_txd1 */
2015                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2016                                         /* mac_txd0 */
2017                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2018                                         /* mac_rxd3 */
2019                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2020                                         /* mac_rxd2 */
2021                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2022                                         /* mac_txd3 */
2023                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2024                                         /* mac_txd2 */
2025                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2026                         };
2027
2028                         rmii_pins: rmii-pins {
2029                                 rockchip,pins =
2030                                         /* mac_mdio */
2031                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2032                                         /* mac_txen */
2033                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2034                                         /* mac_clk */
2035                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2036                                         /* mac_rxer */
2037                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2038                                         /* mac_rxdv */
2039                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2040                                         /* mac_mdc */
2041                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2042                                         /* mac_rxd1 */
2043                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2044                                         /* mac_rxd0 */
2045                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2046                                         /* mac_txd1 */
2047                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2048                                         /* mac_txd0 */
2049                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2050                         };
2051                 };
2052
2053                 i2c0 {
2054                         i2c0_xfer: i2c0-xfer {
2055                                 rockchip,pins =
2056                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2057                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2058                         };
2059                 };
2060
2061                 i2c1 {
2062                         i2c1_xfer: i2c1-xfer {
2063                                 rockchip,pins =
2064                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2065                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2066                         };
2067                 };
2068
2069                 i2c2 {
2070                         i2c2_xfer: i2c2-xfer {
2071                                 rockchip,pins =
2072                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2073                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2074                         };
2075                 };
2076
2077                 i2c3 {
2078                         i2c3_xfer: i2c3-xfer {
2079                                 rockchip,pins =
2080                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2081                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2082                         };
2083
2084                         i2c3_gpio: i2c3_gpio {
2085                                 rockchip,pins =
2086                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2087                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2088                         };
2089
2090                 };
2091
2092                 i2c4 {
2093                         i2c4_xfer: i2c4-xfer {
2094                                 rockchip,pins =
2095                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2096                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2097                         };
2098                 };
2099
2100                 i2c5 {
2101                         i2c5_xfer: i2c5-xfer {
2102                                 rockchip,pins =
2103                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2104                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2105                         };
2106                 };
2107
2108                 i2c6 {
2109                         i2c6_xfer: i2c6-xfer {
2110                                 rockchip,pins =
2111                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2112                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2113                         };
2114                 };
2115
2116                 i2c7 {
2117                         i2c7_xfer: i2c7-xfer {
2118                                 rockchip,pins =
2119                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2120                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2121                         };
2122                 };
2123
2124                 i2c8 {
2125                         i2c8_xfer: i2c8-xfer {
2126                                 rockchip,pins =
2127                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2128                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2129                         };
2130                 };
2131
2132                 i2s0 {
2133                         i2s0_8ch_bus: i2s0-8ch-bus {
2134                                 rockchip,pins =
2135                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2136                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2137                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2138                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2139                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2140                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2141                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2142                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2143                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2144                         };
2145                 };
2146
2147                 i2s1 {
2148                         i2s1_2ch_bus: i2s1-2ch-bus {
2149                                 rockchip,pins =
2150                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2151                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2152                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2153                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2154                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2155                         };
2156                 };
2157
2158                 sdio0 {
2159                         sdio0_bus1: sdio0-bus1 {
2160                                 rockchip,pins =
2161                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2162                         };
2163
2164                         sdio0_bus4: sdio0-bus4 {
2165                                 rockchip,pins =
2166                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2167                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2168                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2169                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2170                         };
2171
2172                         sdio0_cmd: sdio0-cmd {
2173                                 rockchip,pins =
2174                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2175                         };
2176
2177                         sdio0_clk: sdio0-clk {
2178                                 rockchip,pins =
2179                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2180                         };
2181
2182                         sdio0_cd: sdio0-cd {
2183                                 rockchip,pins =
2184                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2185                         };
2186
2187                         sdio0_pwr: sdio0-pwr {
2188                                 rockchip,pins =
2189                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2190                         };
2191
2192                         sdio0_bkpwr: sdio0-bkpwr {
2193                                 rockchip,pins =
2194                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2195                         };
2196
2197                         sdio0_wp: sdio0-wp {
2198                                 rockchip,pins =
2199                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2200                         };
2201
2202                         sdio0_int: sdio0-int {
2203                                 rockchip,pins =
2204                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2205                         };
2206                 };
2207
2208                 sdmmc {
2209                         sdmmc_bus1: sdmmc-bus1 {
2210                                 rockchip,pins =
2211                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2212                         };
2213
2214                         sdmmc_bus4: sdmmc-bus4 {
2215                                 rockchip,pins =
2216                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2217                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2218                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2219                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2220                         };
2221
2222                         sdmmc_clk: sdmmc-clk {
2223                                 rockchip,pins =
2224                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2225                         };
2226
2227                         sdmmc_cmd: sdmmc-cmd {
2228                                 rockchip,pins =
2229                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2230                         };
2231
2232                         sdmmc_cd: sdmcc-cd {
2233                                 rockchip,pins =
2234                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2235                         };
2236
2237                         sdmmc_wp: sdmmc-wp {
2238                                 rockchip,pins =
2239                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2240                         };
2241                 };
2242
2243                 spdif {
2244                         spdif_bus: spdif-bus {
2245                                 rockchip,pins =
2246                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2247                         };
2248
2249                         spdif_bus_1: spdif-bus-1 {
2250                                 rockchip,pins =
2251                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2252                         };
2253                 };
2254
2255                 spi0 {
2256                         spi0_clk: spi0-clk {
2257                                 rockchip,pins =
2258                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2259                         };
2260                         spi0_cs0: spi0-cs0 {
2261                                 rockchip,pins =
2262                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2263                         };
2264                         spi0_cs1: spi0-cs1 {
2265                                 rockchip,pins =
2266                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2267                         };
2268                         spi0_tx: spi0-tx {
2269                                 rockchip,pins =
2270                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2271                         };
2272                         spi0_rx: spi0-rx {
2273                                 rockchip,pins =
2274                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2275                         };
2276                 };
2277
2278                 spi1 {
2279                         spi1_clk: spi1-clk {
2280                                 rockchip,pins =
2281                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2282                         };
2283                         spi1_cs0: spi1-cs0 {
2284                                 rockchip,pins =
2285                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2286                         };
2287                         spi1_rx: spi1-rx {
2288                                 rockchip,pins =
2289                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2290                         };
2291                         spi1_tx: spi1-tx {
2292                                 rockchip,pins =
2293                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2294                         };
2295                 };
2296
2297                 spi2 {
2298                         spi2_clk: spi2-clk {
2299                                 rockchip,pins =
2300                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2301                         };
2302                         spi2_cs0: spi2-cs0 {
2303                                 rockchip,pins =
2304                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2305                         };
2306                         spi2_rx: spi2-rx {
2307                                 rockchip,pins =
2308                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2309                         };
2310                         spi2_tx: spi2-tx {
2311                                 rockchip,pins =
2312                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2313                         };
2314                 };
2315
2316                 spi3 {
2317                         spi3_clk: spi3-clk {
2318                                 rockchip,pins =
2319                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2320                         };
2321                         spi3_cs0: spi3-cs0 {
2322                                 rockchip,pins =
2323                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2324                         };
2325                         spi3_rx: spi3-rx {
2326                                 rockchip,pins =
2327                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2328                         };
2329                         spi3_tx: spi3-tx {
2330                                 rockchip,pins =
2331                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2332                         };
2333                 };
2334
2335                 spi4 {
2336                         spi4_clk: spi4-clk {
2337                                 rockchip,pins =
2338                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2339                         };
2340                         spi4_cs0: spi4-cs0 {
2341                                 rockchip,pins =
2342                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2343                         };
2344                         spi4_rx: spi4-rx {
2345                                 rockchip,pins =
2346                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2347                         };
2348                         spi4_tx: spi4-tx {
2349                                 rockchip,pins =
2350                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2351                         };
2352                 };
2353
2354                 spi5 {
2355                         spi5_clk: spi5-clk {
2356                                 rockchip,pins =
2357                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2358                         };
2359                         spi5_cs0: spi5-cs0 {
2360                                 rockchip,pins =
2361                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2362                         };
2363                         spi5_rx: spi5-rx {
2364                                 rockchip,pins =
2365                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2366                         };
2367                         spi5_tx: spi5-tx {
2368                                 rockchip,pins =
2369                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2370                         };
2371                 };
2372
2373                 tsadc {
2374                         otp_gpio: otp-gpio {
2375                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2376                         };
2377
2378                         otp_out: otp-out {
2379                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2380                         };
2381                 };
2382
2383                 uart0 {
2384                         uart0_xfer: uart0-xfer {
2385                                 rockchip,pins =
2386                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2387                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2388                         };
2389
2390                         uart0_cts: uart0-cts {
2391                                 rockchip,pins =
2392                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2393                         };
2394
2395                         uart0_rts: uart0-rts {
2396                                 rockchip,pins =
2397                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2398                         };
2399                 };
2400
2401                 uart1 {
2402                         uart1_xfer: uart1-xfer {
2403                                 rockchip,pins =
2404                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2405                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2406                         };
2407                 };
2408
2409                 uart2a {
2410                         uart2a_xfer: uart2a-xfer {
2411                                 rockchip,pins =
2412                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2413                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2414                         };
2415                 };
2416
2417                 uart2b {
2418                         uart2b_xfer: uart2b-xfer {
2419                                 rockchip,pins =
2420                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2421                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2422                         };
2423                 };
2424
2425                 uart2c {
2426                         uart2c_xfer: uart2c-xfer {
2427                                 rockchip,pins =
2428                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2429                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2430                         };
2431                 };
2432
2433                 uart3 {
2434                         uart3_xfer: uart3-xfer {
2435                                 rockchip,pins =
2436                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2437                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2438                         };
2439
2440                         uart3_cts: uart3-cts {
2441                                 rockchip,pins =
2442                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2443                         };
2444
2445                         uart3_rts: uart3-rts {
2446                                 rockchip,pins =
2447                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2448                         };
2449                 };
2450
2451                 uart4 {
2452                         uart4_xfer: uart4-xfer {
2453                                 rockchip,pins =
2454                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2455                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2456                         };
2457                 };
2458
2459                 uarthdcp {
2460                         uarthdcp_xfer: uarthdcp-xfer {
2461                                 rockchip,pins =
2462                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2463                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2464                         };
2465                 };
2466
2467                 pwm0 {
2468                         pwm0_pin: pwm0-pin {
2469                                 rockchip,pins =
2470                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2471                         };
2472
2473                         vop0_pwm_pin: vop0-pwm-pin {
2474                                 rockchip,pins =
2475                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2476                         };
2477                 };
2478
2479                 pwm1 {
2480                         pwm1_pin: pwm1-pin {
2481                                 rockchip,pins =
2482                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2483                         };
2484
2485                         vop1_pwm_pin: vop1-pwm-pin {
2486                                 rockchip,pins =
2487                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2488                         };
2489                 };
2490
2491                 pwm2 {
2492                         pwm2_pin: pwm2-pin {
2493                                 rockchip,pins =
2494                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2495                         };
2496                 };
2497
2498                 pwm3a {
2499                         pwm3a_pin: pwm3a-pin {
2500                                 rockchip,pins =
2501                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2502                         };
2503                 };
2504
2505                 pwm3b {
2506                         pwm3b_pin: pwm3b-pin {
2507                                 rockchip,pins =
2508                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2509                         };
2510                 };
2511
2512                 edp {
2513                         edp_hpd: edp-hpd {
2514                                 rockchip,pins =
2515                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2516                         };
2517                 };
2518
2519                 hdmi {
2520                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2521                                 rockchip,pins =
2522                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2523                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2524                         };
2525
2526                         hdmi_cec: hdmi-cec {
2527                                 rockchip,pins =
2528                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2529                         };
2530                 };
2531
2532                 pcie {
2533                         pcie_clkreqn: pci-clkreqn {
2534                                 rockchip,pins =
2535                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2536                         };
2537
2538                         pcie_clkreqnb: pci-clkreqnb {
2539                                 rockchip,pins =
2540                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2541                         };
2542                 };
2543         };
2544 };