arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48
  49 / {
  50         compatible = "rockchip,rk3368";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 serial0 = &uart0;
  63                 serial1 = &uart1;
  64                 serial2 = &uart2;
  65                 serial3 = &uart3;
  66                 serial4 = &uart4;
  67                 spi0 = &spi0;
  68                 spi1 = &spi1;
  69                 spi2 = &spi2;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu-map {
  77                         cluster0 {
  78                                 core0 {
  79                                         cpu = <&cpu_b0>;
  80                                 };
  81                                 core1 {
  82                                         cpu = <&cpu_b1>;
  83                                 };
  84                                 core2 {
  85                                         cpu = <&cpu_b2>;
  86                                 };
  87                                 core3 {
  88                                         cpu = <&cpu_b3>;
  89                                 };
  90                         };
  91
  92                         cluster1 {
  93                                 core0 {
  94                                         cpu = <&cpu_l0>;
  95                                 };
  96                                 core1 {
  97                                         cpu = <&cpu_l1>;
  98                                 };
  99                                 core2 {
 100                                         cpu = <&cpu_l2>;
 101                                 };
 102                                 core3 {
 103                                         cpu = <&cpu_l3>;
 104                                 };
 105                         };
 106                 };
 107
 108                 idle-states {
 109                         entry-method = "psci";
 110
 111                         cpu_sleep: cpu-sleep-0 {
 112                                 compatible = "arm,idle-state";
 113                                 arm,psci-suspend-param = <0x1010000>;
 114                                 entry-latency-us = <0x3fffffff>;
 115                                 exit-latency-us = <0x40000000>;
 116                                 min-residency-us = <0xffffffff>;
 117                         };
 118                 };
 119
 120                 cpu_l0: cpu@0 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x0>;
 124                         cpu-idle-states = <&cpu_sleep>;
 125                         enable-method = "psci";
 126                 };
 127
 128                 cpu_l1: cpu@1 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x1>;
 132                         cpu-idle-states = <&cpu_sleep>;
 133                         enable-method = "psci";
 134                 };
 135
 136                 cpu_l2: cpu@2 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x2>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                 };
 143
 144                 cpu_l3: cpu@3 {
 145                         device_type = "cpu";
 146                         compatible = "arm,cortex-a53", "arm,armv8";
 147                         reg = <0x0 0x3>;
 148                         cpu-idle-states = <&cpu_sleep>;
 149                         enable-method = "psci";
 150                 };
 151
 152                 cpu_b0: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a53", "arm,armv8";
 155                         reg = <0x0 0x100>;
 156                         cpu-idle-states = <&cpu_sleep>;
 157                         enable-method = "psci";
 158                 };
 159
 160                 cpu_b1: cpu@101 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a53", "arm,armv8";
 163                         reg = <0x0 0x101>;
 164                         cpu-idle-states = <&cpu_sleep>;
 165                         enable-method = "psci";
 166                 };
 167
 168                 cpu_b2: cpu@102 {
 169                         device_type = "cpu";
 170                         compatible = "arm,cortex-a53", "arm,armv8";
 171                         reg = <0x0 0x102>;
 172                         cpu-idle-states = <&cpu_sleep>;
 173                         enable-method = "psci";
 174                 };
 175
 176                 cpu_b3: cpu@103 {
 177                         device_type = "cpu";
 178                         compatible = "arm,cortex-a53", "arm,armv8";
 179                         reg = <0x0 0x103>;
 180                         cpu-idle-states = <&cpu_sleep>;
 181                         enable-method = "psci";
 182                 };
 183         };
 184
 185         arm-pmu {
 186                 compatible = "arm,armv8-pmuv3";
 187                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 195                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 196                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 197                                      <&cpu_b2>, <&cpu_b3>;
 198         };
 199
 200         psci {
 201                 compatible = "arm,psci-0.2";
 202                 method = "smc";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv8-timer";
 207                 interrupts = <GIC_PPI 13
 208                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 209                              <GIC_PPI 14
 210                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 11
 212                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 10
 214                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 215         };
 216
 217         xin24m: oscillator {
 218                 compatible = "fixed-clock";
 219                 clock-frequency = <24000000>;
 220                 clock-output-names = "xin24m";
 221                 #clock-cells = <0>;
 222         };
 223
 224         sdmmc: dwmmc@ff0c0000 {
 225                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 226                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 227                 clock-freq-min-max = <400000 150000000>;
 228                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 229                 clock-names = "biu", "ciu";
 230                 fifo-depth = <0x100>;
 231                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 232                 status = "disabled";
 233         };
 234
 235         sdio0: dwmmc@ff0d0000 {
 236                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 237                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 238                 clock-freq-min-max = <400000 150000000>;
 239                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 240                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 241                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 242                 fifo-depth = <0x100>;
 243                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 244                 status = "disabled";
 245         };
 246
 247         emmc: dwmmc@ff0f0000 {
 248                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 249                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 250                 clock-freq-min-max = <400000 150000000>;
 251                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 252                 clock-names = "biu", "ciu";
 253                 fifo-depth = <0x100>;
 254                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 255                 status = "disabled";
 256         };
 257
 258         saradc: saradc@ff100000 {
 259                 compatible = "rockchip,saradc";
 260                 reg = <0x0 0xff100000 0x0 0x100>;
 261                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 262                 #io-channel-cells = <1>;
 263                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 264                 clock-names = "saradc", "apb_pclk";
 265                 status = "disabled";
 266         };
 267
 268         spi0: spi@ff110000 {
 269                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 270                 reg = <0x0 0xff110000 0x0 0x1000>;
 271                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 272                 clock-names = "spiclk", "apb_pclk";
 273                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 status = "disabled";
 279         };
 280
 281         spi1: spi@ff120000 {
 282                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 283                 reg = <0x0 0xff120000 0x0 0x1000>;
 284                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 285                 clock-names = "spiclk", "apb_pclk";
 286                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291                 status = "disabled";
 292         };
 293
 294         spi2: spi@ff130000 {
 295                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 296                 reg = <0x0 0xff130000 0x0 0x1000>;
 297                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 298                 clock-names = "spiclk", "apb_pclk";
 299                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 300                 pinctrl-names = "default";
 301                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 status = "disabled";
 305         };
 306
 307         i2c1: i2c@ff140000 {
 308                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 309                 reg = <0x0 0xff140000 0x0 0x1000>;
 310                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313                 clock-names = "i2c";
 314                 clocks = <&cru PCLK_I2C1>;
 315                 pinctrl-names = "default";
 316                 pinctrl-0 = <&i2c1_xfer>;
 317                 status = "disabled";
 318         };
 319
 320         i2c3: i2c@ff150000 {
 321                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 322                 reg = <0x0 0xff150000 0x0 0x1000>;
 323                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 clock-names = "i2c";
 327                 clocks = <&cru PCLK_I2C3>;
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&i2c3_xfer>;
 330                 status = "disabled";
 331         };
 332
 333         i2c4: i2c@ff160000 {
 334                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 335                 reg = <0x0 0xff160000 0x0 0x1000>;
 336                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 clock-names = "i2c";
 340                 clocks = <&cru PCLK_I2C4>;
 341                 pinctrl-names = "default";
 342                 pinctrl-0 = <&i2c4_xfer>;
 343                 status = "disabled";
 344         };
 345
 346         i2c5: i2c@ff170000 {
 347                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 348                 reg = <0x0 0xff170000 0x0 0x1000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 clock-names = "i2c";
 353                 clocks = <&cru PCLK_I2C5>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&i2c5_xfer>;
 356                 status = "disabled";
 357         };
 358
 359         uart0: serial@ff180000 {
 360                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 361                 reg = <0x0 0xff180000 0x0 0x100>;
 362                 clock-frequency = <24000000>;
 363                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 364                 clock-names = "baudclk", "apb_pclk";
 365                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 366                 reg-shift = <2>;
 367                 reg-io-width = <4>;
 368                 status = "disabled";
 369         };
 370
 371         uart1: serial@ff190000 {
 372                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 373                 reg = <0x0 0xff190000 0x0 0x100>;
 374                 clock-frequency = <24000000>;
 375                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 376                 clock-names = "baudclk", "apb_pclk";
 377                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 378                 reg-shift = <2>;
 379                 reg-io-width = <4>;
 380                 status = "disabled";
 381         };
 382
 383         uart3: serial@ff1b0000 {
 384                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 385                 reg = <0x0 0xff1b0000 0x0 0x100>;
 386                 clock-frequency = <24000000>;
 387                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 388                 clock-names = "baudclk", "apb_pclk";
 389                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 status = "disabled";
 393         };
 394
 395         uart4: serial@ff1c0000 {
 396                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 397                 reg = <0x0 0xff1c0000 0x0 0x100>;
 398                 clock-frequency = <24000000>;
 399                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 400                 clock-names = "baudclk", "apb_pclk";
 401                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 402                 reg-shift = <2>;
 403                 reg-io-width = <4>;
 404                 status = "disabled";
 405         };
 406
 407         gmac: ethernet@ff290000 {
 408                 compatible = "rockchip,rk3368-gmac";
 409                 reg = <0x0 0xff290000 0x0 0x10000>;
 410                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 411                 interrupt-names = "macirq";
 412                 rockchip,grf = <&grf>;
 413                 clocks = <&cru SCLK_MAC>,
 414                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 415                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 416                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 417                 clock-names = "stmmaceth",
 418                         "mac_clk_rx", "mac_clk_tx",
 419                         "clk_mac_ref", "clk_mac_refout",
 420                         "aclk_mac", "pclk_mac";
 421                 status = "disabled";
 422         };
 423
 424         usb_host0_ehci: usb@ff500000 {
 425                 compatible = "generic-ehci";
 426                 reg = <0x0 0xff500000 0x0 0x100>;
 427                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&cru HCLK_HOST0>;
 429                 clock-names = "usbhost";
 430                 status = "disabled";
 431         };
 432
 433         usb_otg: usb@ff580000 {
 434                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 435                                 "snps,dwc2";
 436                 reg = <0x0 0xff580000 0x0 0x40000>;
 437                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 438                 clocks = <&cru HCLK_OTG0>;
 439                 clock-names = "otg";
 440                 dr_mode = "otg";
 441                 g-np-tx-fifo-size = <16>;
 442                 g-rx-fifo-size = <275>;
 443                 g-tx-fifo-size = <256 128 128 64 64 32>;
 444                 g-use-dma;
 445                 status = "disabled";
 446         };
 447
 448         i2c0: i2c@ff650000 {
 449                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 450                 reg = <0x0 0xff650000 0x0 0x1000>;
 451                 clocks = <&cru PCLK_I2C0>;
 452                 clock-names = "i2c";
 453                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&i2c0_xfer>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 status = "disabled";
 459         };
 460
 461         i2c2: i2c@ff660000 {
 462                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 463                 reg = <0x0 0xff660000 0x0 0x1000>;
 464                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 clock-names = "i2c";
 468                 clocks = <&cru PCLK_I2C2>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&i2c2_xfer>;
 471                 status = "disabled";
 472         };
 473
 474         pwm0: pwm@ff680000 {
 475                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 476                 reg = <0x0 0xff680000 0x0 0x10>;
 477                 #pwm-cells = <3>;
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&pwm0_pin>;
 480                 clocks = <&cru PCLK_PWM1>;
 481                 clock-names = "pwm";
 482                 status = "disabled";
 483         };
 484
 485         pwm1: pwm@ff680010 {
 486                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 487                 reg = <0x0 0xff680010 0x0 0x10>;
 488                 #pwm-cells = <3>;
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&pwm1_pin>;
 491                 clocks = <&cru PCLK_PWM1>;
 492                 clock-names = "pwm";
 493                 status = "disabled";
 494         };
 495
 496         pwm2: pwm@ff680020 {
 497                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 498                 reg = <0x0 0xff680020 0x0 0x10>;
 499                 #pwm-cells = <3>;
 500                 clocks = <&cru PCLK_PWM1>;
 501                 clock-names = "pwm";
 502                 status = "disabled";
 503         };
 504
 505         pwm3: pwm@ff680030 {
 506                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 507                 reg = <0x0 0xff680030 0x0 0x10>;
 508                 #pwm-cells = <3>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&pwm3_pin>;
 511                 clocks = <&cru PCLK_PWM1>;
 512                 clock-names = "pwm";
 513                 status = "disabled";
 514         };
 515
 516         uart2: serial@ff690000 {
 517                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 518                 reg = <0x0 0xff690000 0x0 0x100>;
 519                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 520                 clock-names = "baudclk", "apb_pclk";
 521                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&uart2_xfer>;
 524                 reg-shift = <2>;
 525                 reg-io-width = <4>;
 526                 status = "disabled";
 527         };
 528
 529         pmugrf: syscon@ff738000 {
 530                 compatible = "rockchip,rk3368-pmugrf", "syscon";
 531                 reg = <0x0 0xff738000 0x0 0x1000>;
 532         };
 533
 534         cru: clock-controller@ff760000 {
 535                 compatible = "rockchip,rk3368-cru";
 536                 reg = <0x0 0xff760000 0x0 0x1000>;
 537                 rockchip,grf = <&grf>;
 538                 #clock-cells = <1>;
 539                 #reset-cells = <1>;
 540         };
 541
 542         grf: syscon@ff770000 {
 543                 compatible = "rockchip,rk3368-grf", "syscon";
 544                 reg = <0x0 0xff770000 0x0 0x1000>;
 545         };
 546
 547         wdt: watchdog@ff800000 {
 548                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 549                 reg = <0x0 0xff800000 0x0 0x100>;
 550                 clocks = <&cru PCLK_WDT>;
 551                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 552                 status = "disabled";
 553         };
 554
 555         gic: interrupt-controller@ffb71000 {
 556                 compatible = "arm,gic-400";
 557                 interrupt-controller;
 558                 #interrupt-cells = <3>;
 559                 #address-cells = <0>;
 560
 561                 reg = <0x0 0xffb71000 0x0 0x1000>,
 562                       <0x0 0xffb72000 0x0 0x1000>,
 563                       <0x0 0xffb74000 0x0 0x2000>,
 564                       <0x0 0xffb76000 0x0 0x2000>;
 565                 interrupts = <GIC_PPI 9
 566                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 567         };
 568
 569         pinctrl: pinctrl {
 570                 compatible = "rockchip,rk3368-pinctrl";
 571                 rockchip,grf = <&grf>;
 572                 rockchip,pmu = <&pmugrf>;
 573                 #address-cells = <0x2>;
 574                 #size-cells = <0x2>;
 575                 ranges;
 576
 577                 gpio0: gpio0@ff750000 {
 578                         compatible = "rockchip,gpio-bank";
 579                         reg = <0x0 0xff750000 0x0 0x100>;
 580                         clocks = <&cru PCLK_GPIO0>;
 581                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 582
 583                         gpio-controller;
 584                         #gpio-cells = <0x2>;
 585
 586                         interrupt-controller;
 587                         #interrupt-cells = <0x2>;
 588                 };
 589
 590                 gpio1: gpio1@ff780000 {
 591                         compatible = "rockchip,gpio-bank";
 592                         reg = <0x0 0xff780000 0x0 0x100>;
 593                         clocks = <&cru PCLK_GPIO1>;
 594                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 595
 596                         gpio-controller;
 597                         #gpio-cells = <0x2>;
 598
 599                         interrupt-controller;
 600                         #interrupt-cells = <0x2>;
 601                 };
 602
 603                 gpio2: gpio2@ff790000 {
 604                         compatible = "rockchip,gpio-bank";
 605                         reg = <0x0 0xff790000 0x0 0x100>;
 606                         clocks = <&cru PCLK_GPIO2>;
 607                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 608
 609                         gpio-controller;
 610                         #gpio-cells = <0x2>;
 611
 612                         interrupt-controller;
 613                         #interrupt-cells = <0x2>;
 614                 };
 615
 616                 gpio3: gpio3@ff7a0000 {
 617                         compatible = "rockchip,gpio-bank";
 618                         reg = <0x0 0xff7a0000 0x0 0x100>;
 619                         clocks = <&cru PCLK_GPIO3>;
 620                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 621
 622                         gpio-controller;
 623                         #gpio-cells = <0x2>;
 624
 625                         interrupt-controller;
 626                         #interrupt-cells = <0x2>;
 627                 };
 628
 629                 pcfg_pull_up: pcfg-pull-up {
 630                         bias-pull-up;
 631                 };
 632
 633                 pcfg_pull_down: pcfg-pull-down {
 634                         bias-pull-down;
 635                 };
 636
 637                 pcfg_pull_none: pcfg-pull-none {
 638                         bias-disable;
 639                 };
 640
 641                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 642                         bias-disable;
 643                         drive-strength = <12>;
 644                 };
 645
 646                 emmc {
 647                         emmc_clk: emmc-clk {
 648                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 649                         };
 650
 651                         emmc_cmd: emmc-cmd {
 652                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 653                         };
 654
 655                         emmc_pwr: emmc-pwr {
 656                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 657                         };
 658
 659                         emmc_bus1: emmc-bus1 {
 660                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 661                         };
 662
 663                         emmc_bus4: emmc-bus4 {
 664                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 665                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 666                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 667                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 668                         };
 669
 670                         emmc_bus8: emmc-bus8 {
 671                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 672                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 673                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 674                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
 675                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
 676                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
 677                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
 678                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
 679                         };
 680                 };
 681
 682                 gmac {
 683                         rgmii_pins: rgmii-pins {
 684                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 685                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 686                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 687                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 688                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 689                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
 690                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
 691                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
 692                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 693                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 694                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 695                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
 696                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
 697                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
 698                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
 699                         };
 700
 701                         rmii_pins: rmii-pins {
 702                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 703                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 704                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 705                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 706                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 707                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 708                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 709                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 710                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
 711                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
 712                         };
 713                 };
 714
 715                 i2c0 {
 716                         i2c0_xfer: i2c0-xfer {
 717                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 718                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 719                         };
 720                 };
 721
 722                 i2c1 {
 723                         i2c1_xfer: i2c1-xfer {
 724                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
 725                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
 726                         };
 727                 };
 728
 729                 i2c2 {
 730                         i2c2_xfer: i2c2-xfer {
 731                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
 732                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
 733                         };
 734                 };
 735
 736                 i2c3 {
 737                         i2c3_xfer: i2c3-xfer {
 738                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
 739                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
 740                         };
 741                 };
 742
 743                 i2c4 {
 744                         i2c4_xfer: i2c4-xfer {
 745                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
 746                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
 747                         };
 748                 };
 749
 750                 i2c5 {
 751                         i2c5_xfer: i2c5-xfer {
 752                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
 753                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
 754                         };
 755                 };
 756
 757                 sdio0 {
 758                         sdio0_bus1: sdio0-bus1 {
 759                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
 760                         };
 761
 762                         sdio0_bus4: sdio0-bus4 {
 763                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
 764                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
 765                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
 766                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
 767                         };
 768
 769                         sdio0_cmd: sdio0-cmd {
 770                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
 771                         };
 772
 773                         sdio0_clk: sdio0-clk {
 774                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
 775                         };
 776
 777                         sdio0_cd: sdio0-cd {
 778                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
 779                         };
 780
 781                         sdio0_wp: sdio0-wp {
 782                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
 783                         };
 784
 785                         sdio0_pwr: sdio0-pwr {
 786                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
 787                         };
 788
 789                         sdio0_bkpwr: sdio0-bkpwr {
 790                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
 791                         };
 792
 793                         sdio0_int: sdio0-int {
 794                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
 795                         };
 796                 };
 797
 798                 sdmmc {
 799                         sdmmc_clk: sdmmc-clk {
 800                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
 801                         };
 802
 803                         sdmmc_cmd: sdmmc-cmd {
 804                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
 805                         };
 806
 807                         sdmmc_cd: sdmcc-cd {
 808                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
 809                         };
 810
 811                         sdmmc_bus1: sdmmc-bus1 {
 812                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
 813                         };
 814
 815                         sdmmc_bus4: sdmmc-bus4 {
 816                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
 817                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
 818                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
 819                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
 820                         };
 821                 };
 822
 823                 spi0 {
 824                         spi0_clk: spi0-clk {
 825                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
 826                         };
 827                         spi0_cs0: spi0-cs0 {
 828                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
 829                         };
 830                         spi0_cs1: spi0-cs1 {
 831                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
 832                         };
 833                         spi0_tx: spi0-tx {
 834                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
 835                         };
 836                         spi0_rx: spi0-rx {
 837                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
 838                         };
 839                 };
 840
 841                 spi1 {
 842                         spi1_clk: spi1-clk {
 843                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
 844                         };
 845                         spi1_cs0: spi1-cs0 {
 846                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
 847                         };
 848                         spi1_cs1: spi1-cs1 {
 849                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
 850                         };
 851                         spi1_rx: spi1-rx {
 852                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
 853                         };
 854                         spi1_tx: spi1-tx {
 855                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
 856                         };
 857                 };
 858
 859                 spi2 {
 860                         spi2_clk: spi2-clk {
 861                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
 862                         };
 863                         spi2_cs0: spi2-cs0 {
 864                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
 865                         };
 866                         spi2_rx: spi2-rx {
 867                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
 868                         };
 869                         spi2_tx: spi2-tx {
 870                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
 871                         };
 872                 };
 873
 874                 uart0 {
 875                         uart0_xfer: uart0-xfer {
 876                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
 877                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
 878                         };
 879
 880                         uart0_cts: uart0-cts {
 881                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
 882                         };
 883
 884                         uart0_rts: uart0-rts {
 885                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
 886                         };
 887                 };
 888
 889                 uart1 {
 890                         uart1_xfer: uart1-xfer {
 891                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
 892                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
 893                         };
 894
 895                         uart1_cts: uart1-cts {
 896                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
 897                         };
 898
 899                         uart1_rts: uart1-rts {
 900                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
 901                         };
 902                 };
 903
 904                 uart2 {
 905                         uart2_xfer: uart2-xfer {
 906                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
 907                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
 908                         };
 909                         /* no rts / cts for uart2 */
 910                 };
 911
 912                 uart3 {
 913                         uart3_xfer: uart3-xfer {
 914                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
 915                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
 916                         };
 917
 918                         uart3_cts: uart3-cts {
 919                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
 920                         };
 921
 922                         uart3_rts: uart3-rts {
 923                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
 924                         };
 925                 };
 926
 927                 uart4 {
 928                         uart4_xfer: uart4-xfer {
 929                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
 930                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
 931                         };
 932
 933                         uart4_cts: uart4-cts {
 934                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
 935                         };
 936
 937                         uart4_rts: uart4-rts {
 938                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
 939                         };
 940                 };
 941
 942                 pwm0 {
 943                         pwm0_pin: pwm0-pin {
 944                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
 945                         };
 946
 947                         vop_pwm_pin: vop-pwm {
 948                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
 949                         };
 950                 };
 951
 952                 pwm1 {
 953                         pwm1_pin: pwm1-pin {
 954                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
 955                         };
 956                 };
 957
 958                 pwm3 {
 959                         pwm3_pin: pwm3-pin {
 960                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
 961                         };
 962                 };
 963         };
 964
 965         iep_mmu {
 966                 dbgname = "iep";
 967                 compatible = "rockchip,iep_mmu";
 968                 reg = <0x0 0xff900800 0x0 0x100>;
 969                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 970                 interrupt-names = "iep_mmu";
 971         };
 972
 973         vip_mmu {
 974                 dbgname = "vip";
 975                 compatible = "rockchip,vip_mmu";
 976                 reg = <0x0 0xff950800 0x0 0x100>;
 977                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 978                 interrupt-names = "vip_mmu";
 979         };
 980
 981         vop_mmu {
 982                 dbgname = "vop";
 983                 compatible = "rockchip,vopb_mmu";
 984                 reg = <0x0 0xff930300 0x0 0x100>;
 985                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 986                 interrupt-names = "vop_mmu";
 987         };
 988
 989         isp_mmu {
 990                 dbgname = "isp_mmu";
 991                 compatible = "rockchip,isp_mmu";
 992                 reg = <0x0 0xff914000 0x0 0x100>,
 993                       <0x0 0xff915000 0x0 0x100>;
 994                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 995                 interrupt-names = "isp_mmu";
 996         };
 997
 998         hdcp_mmu {
 999                  dbgname = "hdcp_mmu";
1000                  compatible = "rockchip,hdcp_mmu";
1001                  reg = <0x0 0xff940000 0x0 0x100>;
1002                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1003                  interrupt-names = "hdcp_mmu";
1004         };
1005
1006         hevc_mmu {
1007                 dbgname = "hevc";
1008                 compatible = "rockchip,hevc_mmu";
1009                 reg = <0x0 0xff9a0440 0x0 0x40>,
1010                       <0x0 0xff9a0480 0x0 0x40>;
1011                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1012                 interrupt-names = "hevc_mmu";
1013         };
1014
1015         vpu_mmu {
1016                 dbgname = "vpu";
1017                 compatible = "rockchip,vpu_mmu";
1018                 reg = <0x0 0xff9a0800 0x0 0x100>;
1019                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1020                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1021                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1022         };
1023 };