arm64: dts: rk3368: add iommu configs for 4.4

Change-Id: Id74b740fc38c21e138e10b8f0ab8d474c921c8ca
Signed-off-by: Simon <xxm@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 521026de1f6404199ecaf14a433d70bb680dc352..343f3fd9017bd1d87b8c3813a4d214e81def2f24 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -961,4 +961,63 @@
                        };
                };
        };
+
+       iep_mmu {
+               dbgname = "iep";
+               compatible = "rockchip,iep_mmu";
+               reg = <0x0 0xff900800 0x0 0x100>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "iep_mmu";
+       };
+
+       vip_mmu {
+               dbgname = "vip";
+               compatible = "rockchip,vip_mmu";
+               reg = <0x0 0xff950800 0x0 0x100>;
+               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vip_mmu";
+       };
+
+       vop_mmu {
+               dbgname = "vop";
+               compatible = "rockchip,vopb_mmu";
+               reg = <0x0 0xff930300 0x0 0x100>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vop_mmu";
+       };
+
+       isp_mmu {
+               dbgname = "isp_mmu";
+               compatible = "rockchip,isp_mmu";
+               reg = <0x0 0xff914000 0x0 0x100>,
+                     <0x0 0xff915000 0x0 0x100>;
+               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "isp_mmu";
+       };
+
+       hdcp_mmu {
+                dbgname = "hdcp_mmu";
+                compatible = "rockchip,hdcp_mmu";
+                reg = <0x0 0xff940000 0x0 0x100>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "hdcp_mmu";
+       };
+
+       hevc_mmu {
+               dbgname = "hevc";
+               compatible = "rockchip,hevc_mmu";
+               reg = <0x0 0xff9a0440 0x0 0x40>,
+                     <0x0 0xff9a0480 0x0 0x40>;
+               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "hevc_mmu";
+       };
+
+       vpu_mmu {
+               dbgname = "vpu";
+               compatible = "rockchip,vpu_mmu";
+               reg = <0x0 0xff9a0800 0x0 0x100>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vepu_mmu", "vdpu_mmu";
+       };
 };