arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135
 136                         #cooling-cells = <2>; /* min followed by max */
 137                 };
 138
 139                 cpu_l1: cpu@1 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x1>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         operating-points-v2 = <&cluster0_opp>;
 147                 };
 148
 149                 cpu_l2: cpu@2 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a53", "arm,armv8";
 152                         reg = <0x0 0x2>;
 153                         cpu-idle-states = <&cpu_sleep>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         operating-points-v2 = <&cluster0_opp>;
 157                 };
 158
 159                 cpu_l3: cpu@3 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a53", "arm,armv8";
 162                         reg = <0x0 0x3>;
 163                         cpu-idle-states = <&cpu_sleep>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKL>;
 166                         operating-points-v2 = <&cluster0_opp>;
 167                 };
 168
 169                 cpu_b0: cpu@100 {
 170                         device_type = "cpu";
 171                         compatible = "arm,cortex-a53", "arm,armv8";
 172                         reg = <0x0 0x100>;
 173                         cpu-idle-states = <&cpu_sleep>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         operating-points-v2 = <&cluster1_opp>;
 177
 178                         #cooling-cells = <2>; /* min followed by max */
 179                 };
 180
 181                 cpu_b1: cpu@101 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a53", "arm,armv8";
 184                         reg = <0x0 0x101>;
 185                         cpu-idle-states = <&cpu_sleep>;
 186                         enable-method = "psci";
 187                         clocks = <&cru ARMCLKB>;
 188                         operating-points-v2 = <&cluster1_opp>;
 189                 };
 190
 191                 cpu_b2: cpu@102 {
 192                         device_type = "cpu";
 193                         compatible = "arm,cortex-a53", "arm,armv8";
 194                         reg = <0x0 0x102>;
 195                         cpu-idle-states = <&cpu_sleep>;
 196                         enable-method = "psci";
 197                         clocks = <&cru ARMCLKB>;
 198                         operating-points-v2 = <&cluster1_opp>;
 199                 };
 200
 201                 cpu_b3: cpu@103 {
 202                         device_type = "cpu";
 203                         compatible = "arm,cortex-a53", "arm,armv8";
 204                         reg = <0x0 0x103>;
 205                         cpu-idle-states = <&cpu_sleep>;
 206                         enable-method = "psci";
 207                         clocks = <&cru ARMCLKB>;
 208                         operating-points-v2 = <&cluster1_opp>;
 209                 };
 210         };
 211
 212         cluster0_opp: opp_table0 {
 213                 compatible = "operating-points-v2";
 214                 opp-shared;
 215
 216                 opp@216000000 {
 217                         opp-hz = /bits/ 64 <216000000>;
 218                         opp-microvolt = <950000 950000 1350000>;
 219                         clock-latency-ns = <40000>;
 220                         opp-suspend;
 221                 };
 222                 opp@408000000 {
 223                         opp-hz = /bits/ 64 <408000000>;
 224                         opp-microvolt = <950000 950000 1350000>;
 225                         clock-latency-ns = <40000>;
 226                 };
 227                 opp@600000000 {
 228                         opp-hz = /bits/ 64 <600000000>;
 229                         opp-microvolt = <950000 950000 1350000>;
 230                         clock-latency-ns = <40000>;
 231                 };
 232                 opp@816000000 {
 233                         opp-hz = /bits/ 64 <816000000>;
 234                         opp-microvolt = <1025000 1025000 1350000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@1008000000 {
 238                         opp-hz = /bits/ 64 <1008000000>;
 239                         opp-microvolt = <1125000 1125000 1350000>;
 240                         clock-latency-ns = <40000>;
 241                 };
 242                 opp@1200000000 {
 243                         opp-hz = /bits/ 64 <1200000000>;
 244                         opp-microvolt = <1225000 1225000 1350000>;
 245                         clock-latency-ns = <40000>;
 246                 };
 247         };
 248
 249         cluster1_opp: opp_table1 {
 250                 compatible = "operating-points-v2";
 251                 opp-shared;
 252
 253                 opp@216000000 {
 254                         opp-hz = /bits/ 64 <216000000>;
 255                         opp-microvolt = <950000 950000 1350000>;
 256                         clock-latency-ns = <40000>;
 257                         opp-suspend;
 258                 };
 259                 opp@408000000 {
 260                         opp-hz = /bits/ 64 <408000000>;
 261                         opp-microvolt = <950000 950000 1350000>;
 262                         clock-latency-ns = <40000>;
 263                 };
 264                 opp@600000000 {
 265                         opp-hz = /bits/ 64 <600000000>;
 266                         opp-microvolt = <950000 950000 1350000>;
 267                         clock-latency-ns = <40000>;
 268                 };
 269                 opp@816000000 {
 270                         opp-hz = /bits/ 64 <816000000>;
 271                         opp-microvolt = <975000 975000 1350000>;
 272                         clock-latency-ns = <40000>;
 273                 };
 274                 opp@1008000000 {
 275                         opp-hz = /bits/ 64 <1008000000>;
 276                         opp-microvolt = <1050000 1050000 1350000>;
 277                         clock-latency-ns = <40000>;
 278                 };
 279                 opp@1200000000 {
 280                         opp-hz = /bits/ 64 <1200000000>;
 281                         opp-microvolt = <1150000 1150000 1350000>;
 282                         clock-latency-ns = <40000>;
 283                 };
 284                 opp@1296000000 {
 285                         opp-hz = /bits/ 64 <1296000000>;
 286                         opp-microvolt = <1225000 1225000 1350000>;
 287                         clock-latency-ns = <40000>;
 288                 };
 289                 opp@1416000000 {
 290                         opp-hz = /bits/ 64 <1416000000>;
 291                         opp-microvolt = <1300000 1300000 1350000>;
 292                         clock-latency-ns = <40000>;
 293                 };
 294                 opp@1512000000 {
 295                         opp-hz = /bits/ 64 <1512000000>;
 296                         opp-microvolt = <1350000 1350000 1350000>;
 297                         clock-latency-ns = <40000>;
 298                 };
 299         };
 300
 301         cpu_avs: cpu-avs {
 302                 cluster0-avs {
 303                         cluster-id = <0>;
 304                         min-volt = <950000>; /* uV */
 305                         min-freq = <216000>; /* KHz */
 306                         leakage-adjust-volt = <
 307                         /*  mA        mA         uV */
 308                             0         254        0
 309                         >;
 310                         nvmem-cells = <&cpu_leakage>;
 311                         nvmem-cell-names = "cpu_leakage";
 312                 };
 313                 cluster1-avs {
 314                         cluster-id = <1>;
 315                         min-volt = <950000>; /* uV */
 316                         min-freq = <216000>; /* KHz */
 317                         leakage-adjust-volt = <
 318                         /*  mA        mA         uV */
 319                             0         254        0
 320                         >;
 321                         nvmem-cells = <&cpu_leakage>;
 322                         nvmem-cell-names = "cpu_leakage";
 323                 };
 324         };
 325
 326         arm-pmu {
 327                 compatible = "arm,armv8-pmuv3";
 328                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 336                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 337                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 338                                      <&cpu_b2>, <&cpu_b3>;
 339         };
 340
 341         amba {
 342                 compatible = "arm,amba-bus";
 343                 #address-cells = <2>;
 344                 #size-cells = <2>;
 345                 ranges;
 346
 347                 dmac_peri: dma-controller@ff250000 {
 348                         compatible = "arm,pl330", "arm,primecell";
 349                         reg = <0x0 0xff250000 0x0 0x4000>;
 350                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 352                         #dma-cells = <1>;
 353                         clocks = <&cru ACLK_DMAC_PERI>;
 354                         clock-names = "apb_pclk";
 355                         arm,pl330-broken-no-flushp;
 356                         peripherals-req-type-burst;
 357                 };
 358
 359                 dmac_bus: dma-controller@ff600000 {
 360                         compatible = "arm,pl330", "arm,primecell";
 361                         reg = <0x0 0xff600000 0x0 0x4000>;
 362                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 364                         #dma-cells = <1>;
 365                         clocks = <&cru ACLK_DMAC_BUS>;
 366                         clock-names = "apb_pclk";
 367                         arm,pl330-broken-no-flushp;
 368                         peripherals-req-type-burst;
 369                 };
 370         };
 371
 372         psci {
 373                 compatible = "arm,psci-0.2";
 374                 method = "smc";
 375         };
 376
 377         timer {
 378                 compatible = "arm,armv8-timer";
 379                 interrupts = <GIC_PPI 13
 380                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 381                              <GIC_PPI 14
 382                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 383                              <GIC_PPI 11
 384                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 385                              <GIC_PPI 10
 386                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 387         };
 388
 389         xin24m: oscillator {
 390                 compatible = "fixed-clock";
 391                 clock-frequency = <24000000>;
 392                 clock-output-names = "xin24m";
 393                 #clock-cells = <0>;
 394         };
 395
 396         sdmmc: rksdmmc@ff0c0000 {
 397                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 398                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 399                 clock-freq-min-max = <400000 150000000>;
 400                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 401                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 402                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 403                 fifo-depth = <0x100>;
 404                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 405                 status = "disabled";
 406         };
 407
 408         sdio0: dwmmc@ff0d0000 {
 409                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 410                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 411                 clock-freq-min-max = <400000 150000000>;
 412                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 413                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 414                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 415                 fifo-depth = <0x100>;
 416                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 417                 status = "disabled";
 418         };
 419
 420         emmc: rksdmmc@ff0f0000 {
 421                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 422                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 423                 clock-freq-min-max = <400000 150000000>;
 424                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 425                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 426                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 427                 fifo-depth = <0x100>;
 428                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 429                 status = "disabled";
 430         };
 431
 432         saradc: saradc@ff100000 {
 433                 compatible = "rockchip,saradc";
 434                 reg = <0x0 0xff100000 0x0 0x100>;
 435                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 436                 #io-channel-cells = <1>;
 437                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 438                 clock-names = "saradc", "apb_pclk";
 439                 resets = <&cru SRST_SARADC>;
 440                 reset-names = "saradc-apb";
 441                 status = "disabled";
 442         };
 443
 444         spi0: spi@ff110000 {
 445                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 446                 reg = <0x0 0xff110000 0x0 0x1000>;
 447                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 448                 clock-names = "spiclk", "apb_pclk";
 449                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 452                 #address-cells = <1>;
 453                 #size-cells = <0>;
 454                 status = "disabled";
 455         };
 456
 457         spi1: spi@ff120000 {
 458                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 459                 reg = <0x0 0xff120000 0x0 0x1000>;
 460                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 461                 clock-names = "spiclk", "apb_pclk";
 462                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 status = "disabled";
 468         };
 469
 470         spi2: spi@ff130000 {
 471                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 472                 reg = <0x0 0xff130000 0x0 0x1000>;
 473                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 474                 clock-names = "spiclk", "apb_pclk";
 475                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 status = "disabled";
 481         };
 482
 483         i2c0: i2c@ff650000 {
 484                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 485                 reg = <0x0 0xff650000 0x0 0x1000>;
 486                 clocks = <&cru PCLK_I2C0>;
 487                 clock-names = "i2c";
 488                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&i2c0_xfer>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 status = "disabled";
 494         };
 495
 496         i2c2: i2c@ff140000 {
 497                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 498                 reg = <0x0 0xff140000 0x0 0x1000>;
 499                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 500                 #address-cells = <1>;
 501                 #size-cells = <0>;
 502                 clock-names = "i2c";
 503                 clocks = <&cru PCLK_I2C2>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&i2c2_xfer>;
 506                 status = "disabled";
 507         };
 508
 509         i2c3: i2c@ff150000 {
 510                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 511                 reg = <0x0 0xff150000 0x0 0x1000>;
 512                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515                 clock-names = "i2c";
 516                 clocks = <&cru PCLK_I2C3>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&i2c3_xfer>;
 519                 status = "disabled";
 520         };
 521
 522         i2c4: i2c@ff160000 {
 523                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 524                 reg = <0x0 0xff160000 0x0 0x1000>;
 525                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 clock-names = "i2c";
 529                 clocks = <&cru PCLK_I2C4>;
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&i2c4_xfer>;
 532                 status = "disabled";
 533         };
 534
 535         i2c5: i2c@ff170000 {
 536                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 537                 reg = <0x0 0xff170000 0x0 0x1000>;
 538                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 clock-names = "i2c";
 542                 clocks = <&cru PCLK_I2C5>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&i2c5_xfer>;
 545                 status = "disabled";
 546         };
 547
 548         uart0: serial@ff180000 {
 549                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 550                 reg = <0x0 0xff180000 0x0 0x100>;
 551                 clock-frequency = <24000000>;
 552                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 553                 clock-names = "baudclk", "apb_pclk";
 554                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 555                 reg-shift = <2>;
 556                 reg-io-width = <4>;
 557                 status = "disabled";
 558         };
 559
 560         uart1: serial@ff190000 {
 561                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 562                 reg = <0x0 0xff190000 0x0 0x100>;
 563                 clock-frequency = <24000000>;
 564                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 565                 clock-names = "baudclk", "apb_pclk";
 566                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 567                 reg-shift = <2>;
 568                 reg-io-width = <4>;
 569                 status = "disabled";
 570         };
 571
 572         uart3: serial@ff1b0000 {
 573                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 574                 reg = <0x0 0xff1b0000 0x0 0x100>;
 575                 clock-frequency = <24000000>;
 576                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 577                 clock-names = "baudclk", "apb_pclk";
 578                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 579                 reg-shift = <2>;
 580                 reg-io-width = <4>;
 581                 status = "disabled";
 582         };
 583
 584         uart4: serial@ff1c0000 {
 585                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 586                 reg = <0x0 0xff1c0000 0x0 0x100>;
 587                 clock-frequency = <24000000>;
 588                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 589                 clock-names = "baudclk", "apb_pclk";
 590                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 591                 reg-shift = <2>;
 592                 reg-io-width = <4>;
 593                 status = "disabled";
 594         };
 595
 596         thermal-zones {
 597                 cpu {
 598                         polling-delay-passive = <100>; /* milliseconds */
 599                         polling-delay = <5000>; /* milliseconds */
 600
 601                         thermal-sensors = <&tsadc 0>;
 602
 603                         trips {
 604                                 cpu_alert0: cpu_alert0 {
 605                                         temperature = <75000>; /* millicelsius */
 606                                         hysteresis = <2000>; /* millicelsius */
 607                                         type = "passive";
 608                                 };
 609                                 cpu_alert1: cpu_alert1 {
 610                                         temperature = <80000>; /* millicelsius */
 611                                         hysteresis = <2000>; /* millicelsius */
 612                                         type = "passive";
 613                                 };
 614                                 cpu_crit: cpu_crit {
 615                                         temperature = <95000>; /* millicelsius */
 616                                         hysteresis = <2000>; /* millicelsius */
 617                                         type = "critical";
 618                                 };
 619                         };
 620
 621                         cooling-maps {
 622                                 map0 {
 623                                         trip = <&cpu_alert0>;
 624                                         cooling-device =
 625                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 626                                 };
 627                                 map1 {
 628                                         trip = <&cpu_alert1>;
 629                                         cooling-device =
 630                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 631                                 };
 632                         };
 633                 };
 634
 635                 gpu {
 636                         polling-delay-passive = <100>; /* milliseconds */
 637                         polling-delay = <5000>; /* milliseconds */
 638
 639                         thermal-sensors = <&tsadc 1>;
 640
 641                         trips {
 642                                 gpu_alert0: gpu_alert0 {
 643                                         temperature = <80000>; /* millicelsius */
 644                                         hysteresis = <2000>; /* millicelsius */
 645                                         type = "passive";
 646                                 };
 647                                 gpu_crit: gpu_crit {
 648                                         temperature = <115000>; /* millicelsius */
 649                                         hysteresis = <2000>; /* millicelsius */
 650                                         type = "critical";
 651                                 };
 652                         };
 653
 654                         cooling-maps {
 655                                 map0 {
 656                                         trip = <&gpu_alert0>;
 657                                         cooling-device =
 658                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 659                                 };
 660                         };
 661                 };
 662         };
 663
 664         tsadc: tsadc@ff280000 {
 665                 compatible = "rockchip,rk3368-tsadc";
 666                 reg = <0x0 0xff280000 0x0 0x100>;
 667                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 669                 clock-names = "tsadc", "apb_pclk";
 670                 resets = <&cru SRST_TSADC>;
 671                 reset-names = "tsadc-apb";
 672                 pinctrl-names = "init", "default", "sleep";
 673                 pinctrl-0 = <&otp_gpio>;
 674                 pinctrl-1 = <&otp_out>;
 675                 pinctrl-2 = <&otp_gpio>;
 676                 #thermal-sensor-cells = <1>;
 677                 rockchip,hw-tshut-temp = <95000>;
 678                 status = "disabled";
 679         };
 680
 681         gmac: ethernet@ff290000 {
 682                 compatible = "rockchip,rk3368-gmac";
 683                 reg = <0x0 0xff290000 0x0 0x10000>;
 684                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 685                 interrupt-names = "macirq";
 686                 rockchip,grf = <&grf>;
 687                 clocks = <&cru SCLK_MAC>,
 688                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 689                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 690                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 691                 clock-names = "stmmaceth",
 692                         "mac_clk_rx", "mac_clk_tx",
 693                         "clk_mac_ref", "clk_mac_refout",
 694                         "aclk_mac", "pclk_mac";
 695                 status = "disabled";
 696         };
 697
 698         nandc0: nandc@ff400000 {
 699                 compatible = "rockchip,rk-nandc";
 700                 reg = <0x0 0xff400000 0x0 0x4000>;
 701                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 702                 nandc_id = <0>;
 703                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 704                 clock-names = "clk_nandc", "hclk_nandc";
 705                 status = "disabled";
 706         };
 707
 708         usb_host0_ehci: usb@ff500000 {
 709                 compatible = "generic-ehci";
 710                 reg = <0x0 0xff500000 0x0 0x20000>;
 711                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 713                 clock-names = "usbhost", "utmi";
 714                 phys = <&u2phy_host>;
 715                 phy-names = "usb";
 716                 status = "disabled";
 717         };
 718
 719         usb_host0_ohci: usb@ff520000 {
 720                 compatible = "generic-ohci";
 721                 reg = <0x0 0xff520000 0x0 0x20000>;
 722                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 723                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 724                 clock-names = "usbhost", "utmi";
 725                 phys = <&u2phy_host>;
 726                 phy-names = "usb";
 727                 status = "disabled";
 728         };
 729
 730         usb_otg: usb@ff580000 {
 731                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 732                                 "snps,dwc2";
 733                 reg = <0x0 0xff580000 0x0 0x40000>;
 734                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 735                 clocks = <&cru HCLK_OTG0>;
 736                 clock-names = "otg";
 737                 dr_mode = "otg";
 738                 g-np-tx-fifo-size = <16>;
 739                 g-rx-fifo-size = <275>;
 740                 g-tx-fifo-size = <256 128 128 64 64 32>;
 741                 g-use-dma;
 742                 status = "disabled";
 743         };
 744
 745         ddrpctl: syscon@ff610000 {
 746                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 747                 reg = <0x0 0xff610000 0x0 0x400>;
 748         };
 749
 750         i2c1: i2c@ff660000 {
 751                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 752                 reg = <0x0 0xff660000 0x0 0x1000>;
 753                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 754                 #address-cells = <1>;
 755                 #size-cells = <0>;
 756                 clock-names = "i2c";
 757                 clocks = <&cru PCLK_I2C1>;
 758                 pinctrl-names = "default";
 759                 pinctrl-0 = <&i2c1_xfer>;
 760                 status = "disabled";
 761         };
 762
 763         pwm0: pwm@ff680000 {
 764                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 765                 reg = <0x0 0xff680000 0x0 0x10>;
 766                 #pwm-cells = <3>;
 767                 pinctrl-names = "default";
 768                 pinctrl-0 = <&pwm0_pin>;
 769                 clocks = <&cru PCLK_PWM1>;
 770                 clock-names = "pwm";
 771                 status = "disabled";
 772         };
 773
 774         pwm1: pwm@ff680010 {
 775                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 776                 reg = <0x0 0xff680010 0x0 0x10>;
 777                 #pwm-cells = <3>;
 778                 pinctrl-names = "default";
 779                 pinctrl-0 = <&pwm1_pin>;
 780                 clocks = <&cru PCLK_PWM1>;
 781                 clock-names = "pwm";
 782                 status = "disabled";
 783         };
 784
 785         pwm2: pwm@ff680020 {
 786                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 787                 reg = <0x0 0xff680020 0x0 0x10>;
 788                 #pwm-cells = <3>;
 789                 clocks = <&cru PCLK_PWM1>;
 790                 clock-names = "pwm";
 791                 status = "disabled";
 792         };
 793
 794         pwm3: pwm@ff680030 {
 795                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 796                 reg = <0x0 0xff680030 0x0 0x10>;
 797                 #pwm-cells = <3>;
 798                 pinctrl-names = "default";
 799                 pinctrl-0 = <&pwm3_pin>;
 800                 clocks = <&cru PCLK_PWM1>;
 801                 clock-names = "pwm";
 802                 status = "disabled";
 803         };
 804
 805         uart2: serial@ff690000 {
 806                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 807                 reg = <0x0 0xff690000 0x0 0x100>;
 808                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 809                 clock-names = "baudclk", "apb_pclk";
 810                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 811                 pinctrl-names = "default";
 812                 pinctrl-0 = <&uart2_xfer>;
 813                 reg-shift = <2>;
 814                 reg-io-width = <4>;
 815                 status = "disabled";
 816         };
 817
 818         mbox: mbox@ff6b0000 {
 819                 compatible = "rockchip,rk3368-mailbox";
 820                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 821                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 822                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 823                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 824                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 825                 clocks = <&cru PCLK_MAILBOX>;
 826                 clock-names = "pclk_mailbox";
 827                 #mbox-cells = <1>;
 828                 status = "disabled";
 829         };
 830
 831         mailbox: mailbox@ff6b0000 {
 832                 compatible = "rockchip,rk3368-mbox-legacy";
 833                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 834                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 835                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 836                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 837                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 838                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&cru PCLK_MAILBOX>;
 840                 clock-names = "pclk_mailbox";
 841                 #mbox-cells = <1>;
 842                 status = "disabled";
 843         };
 844
 845         mailbox_scpi: mailbox-scpi {
 846                 compatible = "rockchip,rk3368-scpi-legacy";
 847                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 848                 chan-nums = <3>;
 849                 status = "disabled";
 850         };
 851
 852         qos_iep: qos@ffad0000 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffad0000 0x0 0x20>;
 855         };
 856
 857         qos_isp_r0: qos@ffad0080 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffad0080 0x0 0x20>;
 860         };
 861
 862         qos_isp_r1: qos@ffad0100 {
 863                 compatible = "syscon";
 864                 reg = <0x0 0xffad0100 0x0 0x20>;
 865         };
 866
 867         qos_isp_w0: qos@ffad0180 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xffad0180 0x0 0x20>;
 870         };
 871
 872         qos_isp_w1: qos@ffad0200 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xffad0200 0x0 0x20>;
 875         };
 876
 877         qos_vip: qos@ffad0280 {
 878                 compatible = "syscon";
 879                 reg = <0x0 0xffad0280 0x0 0x20>;
 880         };
 881
 882         qos_vop: qos@ffad0300 {
 883                 compatible = "syscon";
 884                 reg = <0x0 0xffad0300 0x0 0x20>;
 885         };
 886
 887         qos_rga_r: qos@ffad0380 {
 888                 compatible = "syscon";
 889                 reg = <0x0 0xffad0380 0x0 0x20>;
 890         };
 891
 892         qos_rga_w: qos@ffad0400 {
 893                 compatible = "syscon";
 894                 reg = <0x0 0xffad0400 0x0 0x20>;
 895         };
 896
 897         qos_hevc_r: qos@ffae0000 {
 898                 compatible = "syscon";
 899                 reg = <0x0 0xffae0000 0x0 0x20>;
 900         };
 901
 902         qos_vpu_r: qos@ffae0100 {
 903                 compatible = "syscon";
 904                 reg = <0x0 0xffae0100 0x0 0x20>;
 905         };
 906
 907         qos_vpu_w: qos@ffae0180 {
 908                 compatible = "syscon";
 909                 reg = <0x0 0xffae0180 0x0 0x20>;
 910         };
 911
 912         qos_gpu: qos@ffaf0000 {
 913                 compatible = "syscon";
 914                 reg = <0x0 0xffaf0000 0x0 0x20>;
 915         };
 916
 917         pmu: power-management@ff730000 {
 918                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 919                 reg = <0x0 0xff730000 0x0 0x1000>;
 920
 921                 power: power-controller {
 922                         compatible = "rockchip,rk3368-power-controller";
 923                         #power-domain-cells = <1>;
 924                         #address-cells = <1>;
 925                         #size-cells = <0>;
 926
 927                         /*
 928                          * Note: Although SCLK_* are the working clocks
 929                          * of device without including on the NOC, needed for
 930                          * synchronous reset.
 931                          *
 932                          * The clocks on the which NOC:
 933                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 934                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 935                          * ACLK_RGA is on ACLK_RGA_NIU.
 936                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 937                          *
 938                          * Which clock are device clocks:
 939                          *      clocks          devices
 940                          *      *_IEP           IEP:Image Enhancement Processor
 941                          *      *_ISP           ISP:Image Signal Processing
 942                          *      *_VIP           VIP:Video Input Processor
 943                          *      *_VOP*          VOP:Visual Output Processor
 944                          *      *_RGA           RGA
 945                          *      *_EDP*          EDP
 946                          *      *_DPHY*         LVDS
 947                          *      *_HDMI          HDMI
 948                          *      *_MIPI_*        MIPI
 949                          */
 950                         pd_vio {
 951                                 reg = <RK3368_PD_VIO>;
 952                                 clocks = <&cru ACLK_IEP>,
 953                                          <&cru ACLK_ISP>,
 954                                          <&cru ACLK_VIP>,
 955                                          <&cru ACLK_RGA>,
 956                                          <&cru ACLK_VOP>,
 957                                          <&cru ACLK_VOP_IEP>,
 958                                          <&cru DCLK_VOP>,
 959                                          <&cru HCLK_IEP>,
 960                                          <&cru HCLK_ISP>,
 961                                          <&cru HCLK_RGA>,
 962                                          <&cru HCLK_VIP>,
 963                                          <&cru HCLK_VOP>,
 964                                          <&cru HCLK_VIO_HDCPMMU>,
 965                                          <&cru PCLK_EDP_CTRL>,
 966                                          <&cru PCLK_HDMI_CTRL>,
 967                                          <&cru PCLK_HDCP>,
 968                                          <&cru PCLK_ISP>,
 969                                          <&cru PCLK_VIP>,
 970                                          <&cru PCLK_DPHYRX>,
 971                                          <&cru PCLK_DPHYTX0>,
 972                                          <&cru PCLK_MIPI_CSI>,
 973                                          <&cru PCLK_MIPI_DSI0>,
 974                                          <&cru SCLK_VOP0_PWM>,
 975                                          <&cru SCLK_EDP_24M>,
 976                                          <&cru SCLK_EDP>,
 977                                          <&cru SCLK_HDCP>,
 978                                          <&cru SCLK_ISP>,
 979                                          <&cru SCLK_RGA>,
 980                                          <&cru SCLK_HDMI_CEC>,
 981                                          <&cru SCLK_HDMI_HDCP>;
 982                                 pm_qos = <&qos_iep>,
 983                                          <&qos_isp_r0>,
 984                                          <&qos_isp_r1>,
 985                                          <&qos_isp_w0>,
 986                                          <&qos_isp_w1>,
 987                                          <&qos_vip>,
 988                                          <&qos_vop>,
 989                                          <&qos_rga_r>,
 990                                          <&qos_rga_w>;
 991                         };
 992                         /*
 993                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 994                          * (video endecoder & decoder) clocks that on the
 995                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 996                          */
 997                         pd_video {
 998                                 reg = <RK3368_PD_VIDEO>;
 999                                 clocks = <&cru ACLK_VIDEO>,
1000                                          <&cru HCLK_VIDEO>,
1001                                          <&cru SCLK_HEVC_CABAC>,
1002                                          <&cru SCLK_HEVC_CORE>;
1003                                 pm_qos = <&qos_hevc_r>,
1004                                          <&qos_vpu_r>,
1005                                          <&qos_vpu_w>;
1006                         };
1007                         /*
1008                          * Note: ACLK_GPU is the GPU clock,
1009                          * and on the ACLK_GPU_NIU (NOC).
1010                          */
1011                         pd_gpu_1 {
1012                                 reg = <RK3368_PD_GPU_1>;
1013                                 clocks = <&cru ACLK_GPU_CFG>,
1014                                          <&cru ACLK_GPU_MEM>,
1015                                          <&cru SCLK_GPU_CORE>;
1016                                 pm_qos = <&qos_gpu>;
1017                         };
1018                 };
1019         };
1020
1021         pmugrf: syscon@ff738000 {
1022                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1023                 reg = <0x0 0xff738000 0x0 0x1000>;
1024
1025                 pmu_io_domains: io-domains {
1026                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1027                         status = "disabled";
1028                 };
1029
1030                 reboot-mode {
1031                         compatible = "syscon-reboot-mode";
1032                         offset = <0x200>;
1033                         mode-normal = <BOOT_NORMAL>;
1034                         mode-recovery = <BOOT_RECOVERY>;
1035                         mode-bootloader = <BOOT_FASTBOOT>;
1036                         mode-loader = <BOOT_BL_DOWNLOAD>;
1037                 };
1038         };
1039
1040         cru: clock-controller@ff760000 {
1041                 compatible = "rockchip,rk3368-cru";
1042                 reg = <0x0 0xff760000 0x0 0x1000>;
1043                 rockchip,grf = <&grf>;
1044                 #clock-cells = <1>;
1045                 #reset-cells = <1>;
1046                 assigned-clocks =
1047                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1048                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1049                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1050                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1051                 assigned-clock-rates =
1052                         <576000000>, <400000000>,
1053                         <300000000>, <300000000>,
1054                         <150000000>, <150000000>,
1055                         <75000000>, <75000000>;
1056         };
1057
1058         grf: syscon@ff770000 {
1059                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1060                 reg = <0x0 0xff770000 0x0 0x1000>;
1061                 #address-cells = <1>;
1062                 #size-cells = <1>;
1063
1064                 io_domains: io-domains {
1065                         compatible = "rockchip,rk3368-io-voltage-domain";
1066                         status = "disabled";
1067                 };
1068
1069                 u2phy: usb2-phy@700 {
1070                         compatible = "rockchip,rk3368-usb2phy";
1071                         reg = <0x700 0x2c>;
1072                         clocks = <&cru SCLK_OTGPHY0>;
1073                         clock-names = "phyclk";
1074                         #clock-cells = <0>;
1075                         clock-output-names = "usbotg_out";
1076                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1077                         assigned-clock-parents = <&u2phy>;
1078                         status = "disabled";
1079
1080                         u2phy_host: host-port {
1081                                 #phy-cells = <0>;
1082                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1083                                 interrupt-names = "linestate";
1084                                 status = "disabled";
1085                         };
1086                 };
1087         };
1088
1089         wdt: watchdog@ff800000 {
1090                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1091                 reg = <0x0 0xff800000 0x0 0x100>;
1092                 clocks = <&cru PCLK_WDT>;
1093                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1094                 status = "disabled";
1095         };
1096
1097         timer@ff810000 {
1098                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1099                 reg = <0x0 0xff810000 0x0 0x20>;
1100                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1101         };
1102
1103         i2s_2ch: i2s-2ch@ff890000 {
1104                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1105                 reg = <0x0 0xff890000 0x0 0x1000>;
1106                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1107                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1108                 dma-names = "tx", "rx";
1109                 clock-names = "i2s_clk", "i2s_hclk";
1110                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1111                 status = "disabled";
1112         };
1113
1114         i2s_8ch: i2s-8ch@ff898000 {
1115                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1116                 reg = <0x0 0xff898000 0x0 0x1000>;
1117                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1118                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1119                 dma-names = "tx", "rx";
1120                 clock-names = "i2s_clk", "i2s_hclk";
1121                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1122                 pinctrl-names = "default";
1123                 pinctrl-0 = <&i2s_8ch_bus>;
1124                 status = "disabled";
1125         };
1126
1127         isp_mmu: iommu@ff914000 {
1128                 compatible = "rockchip,iommu";
1129                 reg = <0x0 0xff914000 0x0 0x100>,
1130                       <0x0 0xff915000 0x0 0x100>;
1131                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1132                 interrupt-names = "isp_mmu";
1133                 #iommu-cells = <0>;
1134                 status = "disabled";
1135         };
1136
1137         vop: vop@ff930000 {
1138                 compatible = "rockchip,rk3368-vop";
1139                 reg = <0x0 0xff930000 0x0 0x2fc>;
1140                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1141                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1142                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1143                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1144                 assigned-clock-rates = <400000000>, <200000000>;
1145                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1146                 reset-names = "axi", "ahb", "dclk";
1147                 power-domains = <&power RK3368_PD_VIO>;
1148                 iommus = <&vop_mmu>;
1149                 status = "disabled";
1150
1151                 vop_out: port {
1152                         #address-cells = <1>;
1153                         #size-cells = <0>;
1154
1155                         vop_out_mipi: endpoint@0 {
1156                                 reg = <0>;
1157                                 remote-endpoint = <&mipi_in_vop>;
1158                         };
1159                 };
1160         };
1161
1162         display_subsystem: display-subsystem {
1163                 compatible = "rockchip,display-subsystem";
1164                 ports = <&vop_out>;
1165                 status = "disabled";
1166         };
1167
1168         vop_mmu: iommu@ff930300 {
1169                 compatible = "rockchip,iommu";
1170                 reg = <0x0 0xff930300 0x0 0x100>;
1171                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1172                 interrupt-names = "vop_mmu";
1173                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1174                 clock-names = "aclk", "hclk";
1175                 power-domains = <&power RK3368_PD_VIO>;
1176                 #iommu-cells = <0>;
1177                 status = "disabled";
1178         };
1179
1180         mipi_dsi_host: mipi-dsi-host@ff960000 {
1181                 compatible = "rockchip,rk3368-mipi-dsi";
1182                 reg = <0x0 0xff960000 0x0 0x4000>;
1183                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1184                 clocks = <&cru PCLK_MIPI_DSI0>;
1185                 clock-names = "pclk";
1186                 phys = <&mipi_dphy>;
1187                 phy-names = "mipi_dphy";
1188                 rockchip,grf = <&grf>;
1189                 power-domains = <&power RK3368_PD_VIO>;
1190                 #address-cells = <1>;
1191                 #size-cells = <0>;
1192                 status = "disabled";
1193
1194                 ports@1 {
1195                         #address-cells = <1>;
1196                         #size-cells = <0>;
1197                         reg = <1>;
1198
1199                         mipi_in: port {
1200                                 #address-cells = <1>;
1201                                 #size-cells = <0>;
1202
1203                                 mipi_in_vop: endpoint@0 {
1204                                         reg = <0>;
1205                                         remote-endpoint = <&vop_out_mipi>;
1206                                 };
1207                         };
1208                 };
1209         };
1210
1211         mipi_dphy: mipi-dphy@ff968000 {
1212                 compatible = "rockchip,rk3368-mipi-dphy";
1213                 reg = <0x0 0xff968000 0x0 0x4000>;
1214                 #phy-cells = <0>;
1215                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1216                 clock-names = "ref", "pclk";
1217                 status = "disabled";
1218         };
1219
1220         hevc_mmu: iommu@ff9a0440 {
1221                 compatible = "rockchip,iommu";
1222                 reg = <0x0 0xff9a0440 0x0 0x100>,
1223                       <0x0 0xff9a0480 0x0 0x100>;
1224                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1225                 interrupt-names = "hevc_mmu";
1226                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1227                 clock-names = "aclk", "hclk";
1228                 power-domains = <&power RK3368_PD_VIDEO>;
1229                 #iommu-cells = <0>;
1230                 status = "disabled";
1231         };
1232
1233         vpu_mmu: iommu@ff9a0800 {
1234                 compatible = "rockchip,iommu";
1235                 reg = <0x0 0xff9a0800 0x0 0x100>;
1236                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1237                 interrupt-names = "vpu_mmu";
1238                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1239                 clock-names = "aclk", "hclk";
1240                 power-domains = <&power RK3368_PD_VIDEO>;
1241                 #iommu-cells = <0>;
1242                 status = "disabled";
1243         };
1244
1245         gic: interrupt-controller@ffb71000 {
1246                 compatible = "arm,gic-400";
1247                 interrupt-controller;
1248                 #interrupt-cells = <3>;
1249                 #address-cells = <0>;
1250
1251                 reg = <0x0 0xffb71000 0x0 0x1000>,
1252                       <0x0 0xffb72000 0x0 0x2000>,
1253                       <0x0 0xffb74000 0x0 0x2000>,
1254                       <0x0 0xffb76000 0x0 0x2000>;
1255                 interrupts = <GIC_PPI 9
1256                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1257         };
1258
1259         gpu: rogue-g6110@ffa30000 {
1260                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1261                 reg = <0x0 0xffa30000 0x0 0x10000>;
1262                 clocks =
1263                         <&cru SCLK_GPU_CORE>,
1264                         <&cru ACLK_GPU_MEM>,
1265                         <&cru ACLK_GPU_CFG>;
1266                 clock-names =
1267                         "sclk_gpu_core",
1268                         "aclk_gpu_mem",
1269                         "aclk_gpu_cfg";
1270                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1271                 interrupt-names = "rogue-g6110-irq";
1272                 power-domains = <&power RK3368_PD_GPU_1>;
1273                 operating-points-v2 = <&gpu_opp_table>;
1274         };
1275
1276         gpu_opp_table: gpu_opp_table {
1277                 compatible = "operating-points-v2";
1278                 opp-shared;
1279
1280                 opp@200000000 {
1281                         opp-hz = /bits/ 64 <200000000>;
1282                         opp-microvolt = <1100000>;
1283                 };
1284                 opp@288000000 {
1285                         opp-hz = /bits/ 64 <288000000>;
1286                         opp-microvolt = <1100000>;
1287                 };
1288                 opp@400000000 {
1289                         opp-hz = /bits/ 64 <400000000>;
1290                         opp-microvolt = <1100000>;
1291                 };
1292                 opp@576000000 {
1293                         opp-hz = /bits/ 64 <576000000>;
1294                         opp-microvolt = <1200000>;
1295                 };
1296         };
1297
1298         efuse: efuse@ffb00000 {
1299                 compatible = "rockchip,rk3368-efuse";
1300                 reg = <0x0 0xffb00000 0x0 0x20>;
1301                 #address-cells = <1>;
1302                 #size-cells = <1>;
1303                 clocks = <&cru PCLK_EFUSE256>;
1304                 clock-names = "pclk_efuse";
1305
1306                 /* Data cells */
1307                 cpu_leakage: cpu-leakage@17 {
1308                         reg = <0x17 0x1>;
1309                 };
1310                 temp_adjust: temp-adjust@1f {
1311                         reg = <0x1f 0x1>;
1312                 };
1313         };
1314
1315         pinctrl: pinctrl {
1316                 compatible = "rockchip,rk3368-pinctrl";
1317                 rockchip,grf = <&grf>;
1318                 rockchip,pmu = <&pmugrf>;
1319                 #address-cells = <0x2>;
1320                 #size-cells = <0x2>;
1321                 ranges;
1322
1323                 gpio0: gpio0@ff750000 {
1324                         compatible = "rockchip,gpio-bank";
1325                         reg = <0x0 0xff750000 0x0 0x100>;
1326                         clocks = <&cru PCLK_GPIO0>;
1327                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1328
1329                         gpio-controller;
1330                         #gpio-cells = <0x2>;
1331
1332                         interrupt-controller;
1333                         #interrupt-cells = <0x2>;
1334                 };
1335
1336                 gpio1: gpio1@ff780000 {
1337                         compatible = "rockchip,gpio-bank";
1338                         reg = <0x0 0xff780000 0x0 0x100>;
1339                         clocks = <&cru PCLK_GPIO1>;
1340                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1341
1342                         gpio-controller;
1343                         #gpio-cells = <0x2>;
1344
1345                         interrupt-controller;
1346                         #interrupt-cells = <0x2>;
1347                 };
1348
1349                 gpio2: gpio2@ff790000 {
1350                         compatible = "rockchip,gpio-bank";
1351                         reg = <0x0 0xff790000 0x0 0x100>;
1352                         clocks = <&cru PCLK_GPIO2>;
1353                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1354
1355                         gpio-controller;
1356                         #gpio-cells = <0x2>;
1357
1358                         interrupt-controller;
1359                         #interrupt-cells = <0x2>;
1360                 };
1361
1362                 gpio3: gpio3@ff7a0000 {
1363                         compatible = "rockchip,gpio-bank";
1364                         reg = <0x0 0xff7a0000 0x0 0x100>;
1365                         clocks = <&cru PCLK_GPIO3>;
1366                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1367
1368                         gpio-controller;
1369                         #gpio-cells = <0x2>;
1370
1371                         interrupt-controller;
1372                         #interrupt-cells = <0x2>;
1373                 };
1374
1375                 pcfg_pull_up: pcfg-pull-up {
1376                         bias-pull-up;
1377                 };
1378
1379                 pcfg_pull_down: pcfg-pull-down {
1380                         bias-pull-down;
1381                 };
1382
1383                 pcfg_pull_none: pcfg-pull-none {
1384                         bias-disable;
1385                 };
1386
1387                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1388                         bias-disable;
1389                         drive-strength = <12>;
1390                 };
1391
1392                 emmc {
1393                         emmc_clk: emmc-clk {
1394                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1395                         };
1396
1397                         emmc_cmd: emmc-cmd {
1398                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1399                         };
1400
1401                         emmc_pwr: emmc-pwr {
1402                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1403                         };
1404
1405                         emmc_bus1: emmc-bus1 {
1406                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1407                         };
1408
1409                         emmc_bus4: emmc-bus4 {
1410                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1411                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1412                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1413                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1414                         };
1415
1416                         emmc_bus8: emmc-bus8 {
1417                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1418                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1419                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1420                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1421                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1422                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1423                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1424                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1425                         };
1426                 };
1427
1428                 gmac {
1429                         rgmii_pins: rgmii-pins {
1430                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1431                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1432                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1433                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1434                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1435                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1436                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1437                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1438                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1439                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1440                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1441                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1442                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1443                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1444                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1445                         };
1446
1447                         rmii_pins: rmii-pins {
1448                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1449                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1450                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1451                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1452                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1453                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1454                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1455                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1456                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1457                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1458                         };
1459                 };
1460
1461                 i2c0 {
1462                         i2c0_xfer: i2c0-xfer {
1463                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1464                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1465                         };
1466                 };
1467
1468                 i2c1 {
1469                         i2c1_xfer: i2c1-xfer {
1470                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1471                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 i2c2 {
1476                         i2c2_xfer: i2c2-xfer {
1477                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1478                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1479                         };
1480                 };
1481
1482                 i2c3 {
1483                         i2c3_xfer: i2c3-xfer {
1484                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1485                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1486                         };
1487                 };
1488
1489                 i2c4 {
1490                         i2c4_xfer: i2c4-xfer {
1491                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1492                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1493                         };
1494                 };
1495
1496                 i2c5 {
1497                         i2c5_xfer: i2c5-xfer {
1498                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1499                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1500                         };
1501                 };
1502
1503                 i2s {
1504                         i2s_8ch_bus: i2s-8ch-bus {
1505                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1506                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1507                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1508                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1509                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1510                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1511                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1512                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1513                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1514                         };
1515                 };
1516
1517                 pwm0 {
1518                         pwm0_pin: pwm0-pin {
1519                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1520                         };
1521
1522                         vop_pwm_pin: vop-pwm {
1523                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1524                         };
1525                 };
1526
1527                 pwm1 {
1528                         pwm1_pin: pwm1-pin {
1529                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1530                         };
1531                 };
1532
1533                 pwm3 {
1534                         pwm3_pin: pwm3-pin {
1535                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 sdio0 {
1540                         sdio0_bus1: sdio0-bus1 {
1541                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1542                         };
1543
1544                         sdio0_bus4: sdio0-bus4 {
1545                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1546                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1547                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1548                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1549                         };
1550
1551                         sdio0_cmd: sdio0-cmd {
1552                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1553                         };
1554
1555                         sdio0_clk: sdio0-clk {
1556                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1557                         };
1558
1559                         sdio0_cd: sdio0-cd {
1560                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1561                         };
1562
1563                         sdio0_wp: sdio0-wp {
1564                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1565                         };
1566
1567                         sdio0_pwr: sdio0-pwr {
1568                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1569                         };
1570
1571                         sdio0_bkpwr: sdio0-bkpwr {
1572                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         sdio0_int: sdio0-int {
1576                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1577                         };
1578                 };
1579
1580                 sdmmc {
1581                         sdmmc_clk: sdmmc-clk {
1582                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1583                         };
1584
1585                         sdmmc_cmd: sdmmc-cmd {
1586                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1587                         };
1588
1589                         sdmmc_cd: sdmmc-cd {
1590                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1591                         };
1592
1593                         sdmmc_bus1: sdmmc-bus1 {
1594                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1595                         };
1596
1597                         sdmmc_bus4: sdmmc-bus4 {
1598                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1599                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1600                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1601                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1602                         };
1603                 };
1604
1605                 spi0 {
1606                         spi0_clk: spi0-clk {
1607                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1608                         };
1609                         spi0_cs0: spi0-cs0 {
1610                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1611                         };
1612                         spi0_cs1: spi0-cs1 {
1613                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1614                         };
1615                         spi0_tx: spi0-tx {
1616                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1617                         };
1618                         spi0_rx: spi0-rx {
1619                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1620                         };
1621                 };
1622
1623                 spi1 {
1624                         spi1_clk: spi1-clk {
1625                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1626                         };
1627                         spi1_cs0: spi1-cs0 {
1628                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1629                         };
1630                         spi1_cs1: spi1-cs1 {
1631                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1632                         };
1633                         spi1_rx: spi1-rx {
1634                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1635                         };
1636                         spi1_tx: spi1-tx {
1637                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1638                         };
1639                 };
1640
1641                 spi2 {
1642                         spi2_clk: spi2-clk {
1643                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1644                         };
1645                         spi2_cs0: spi2-cs0 {
1646                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1647                         };
1648                         spi2_rx: spi2-rx {
1649                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1650                         };
1651                         spi2_tx: spi2-tx {
1652                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1653                         };
1654                 };
1655
1656                 tsadc {
1657                         otp_gpio: otp-gpio {
1658                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1659                         };
1660
1661                         otp_out: otp-out {
1662                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1663                         };
1664                 };
1665
1666                 uart0 {
1667                         uart0_xfer: uart0-xfer {
1668                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1669                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1670                         };
1671
1672                         uart0_cts: uart0-cts {
1673                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1674                         };
1675
1676                         uart0_rts: uart0-rts {
1677                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1678                         };
1679                 };
1680
1681                 uart1 {
1682                         uart1_xfer: uart1-xfer {
1683                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1684                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1685                         };
1686
1687                         uart1_cts: uart1-cts {
1688                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1689                         };
1690
1691                         uart1_rts: uart1-rts {
1692                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1693                         };
1694                 };
1695
1696                 uart2 {
1697                         uart2_xfer: uart2-xfer {
1698                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1699                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1700                         };
1701                         /* no rts / cts for uart2 */
1702                 };
1703
1704                 uart3 {
1705                         uart3_xfer: uart3-xfer {
1706                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1707                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1708                         };
1709
1710                         uart3_cts: uart3-cts {
1711                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1712                         };
1713
1714                         uart3_rts: uart3-rts {
1715                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 uart4 {
1720                         uart4_xfer: uart4-xfer {
1721                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1722                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1723                         };
1724
1725                         uart4_cts: uart4-cts {
1726                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1727                         };
1728
1729                         uart4_rts: uart4-rts {
1730                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1731                         };
1732                 };
1733         };
1734 };