2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
50 compatible = "rockchip,rk3366";
51 interrupt-parent = <&gic>;
70 #address-cells = <0x2>;
75 compatible = "arm,cortex-a53","arm,armv8";
77 enable-method = "psci";
82 compatible = "arm,cortex-a53","arm,armv8";
84 enable-method = "psci";
89 compatible = "arm,cortex-a53","arm,armv8";
91 enable-method = "psci";
96 compatible = "arm,cortex-a53","arm,armv8";
98 enable-method = "psci";
103 compatible = "arm,psci-1.0";
108 compatible = "arm,armv8-timer";
111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
117 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
118 clock-frequency = <24000000>;
122 compatible = "fixed-clock";
124 clock-frequency = <24000000>;
125 clock-output-names = "xin24m";
128 gic: interrupt-controller@ffb71000 {
129 compatible = "arm,gic-400";
130 interrupt-controller;
131 #interrupt-cells = <3>;
132 #address-cells = <0>;
134 reg = <0x0 0xffb71000 0x0 0x1000>,
135 <0x0 0xffb72000 0x0 0x1000>,
136 <0x0 0xffb74000 0x0 0x2000>,
137 <0x0 0xffb76000 0x0 0x2000>;
138 interrupts = <GIC_PPI 9
139 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
142 nandc0: nandc@ff0c0000 {
143 compatible = "rockchip,rk-nandc";
144 reg = <0x0 0xff0c0000 0x0 0x4000>;
145 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
148 clock-names = "clk_nandc", "hclk_nandc";
152 saradc: saradc@ff100000 {
153 compatible = "rockchip,saradc";
154 reg = <0x0 0xff100000 0x0 0x100>;
155 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
156 #io-channel-cells = <1>;
157 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
158 clock-names = "saradc", "apb_pclk";
163 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
164 reg = <0x0 0xff110000 0x0 0x1000>;
165 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
166 clock-names = "spiclk", "apb_pclk";
167 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
170 #address-cells = <1>;
176 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
177 reg = <0x0 0xff120000 0x0 0x1000>;
178 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
179 clock-names = "spiclk", "apb_pclk";
180 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
183 #address-cells = <1>;
189 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
190 reg = <0x0 0xff728000 0x0 0x1000>;
191 clocks = <&cru PCLK_I2C0>;
193 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_xfer>;
196 #address-cells = <1>;
202 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
203 reg = <0x0 0xff140000 0x0 0x1000>;
204 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
208 clocks = <&cru PCLK_I2C2>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&i2c2_xfer>;
215 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
216 reg = <0x0 0xff150000 0x0 0x1000>;
217 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
218 #address-cells = <1>;
221 clocks = <&cru PCLK_I2C3>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&i2c3_xfer>;
228 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
229 reg = <0x0 0xff160000 0x0 0x1000>;
230 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
234 clocks = <&cru PCLK_I2C4>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&i2c4_xfer>;
241 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
242 reg = <0x0 0xff170000 0x0 0x1000>;
243 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
244 #address-cells = <1>;
247 clocks = <&cru PCLK_I2C5>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c5_xfer>;
253 uart0: serial@ff180000 {
254 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
255 reg = <0x0 0xff180000 0x0 0x100>;
256 clock-frequency = <24000000>;
257 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
258 clock-names = "baudclk", "apb_pclk";
259 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
267 uart3: serial@ff1b0000 {
268 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
269 reg = <0x0 0xff1b0000 0x0 0x100>;
270 clock-frequency = <24000000>;
271 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
272 clock-names = "baudclk", "apb_pclk";
273 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
282 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
283 reg = <0x0 0xff660000 0x0 0x1000>;
284 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
285 #address-cells = <1>;
288 clocks = <&cru PCLK_I2C1>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&i2c1_xfer>;
295 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
296 reg = <0x0 0xff680000 0x0 0x10>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pwm0_pin>;
300 clocks = <&cru PCLK_RKPWM>;
306 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
307 reg = <0x0 0xff680010 0x0 0x10>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pwm1_pin>;
311 clocks = <&cru PCLK_RKPWM>;
317 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
318 reg = <0x0 0xff680020 0x0 0x10>;
320 clocks = <&cru PCLK_RKPWM>;
326 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
327 reg = <0x0 0xff680030 0x0 0x10>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pwm3_t2_pin>;
331 clocks = <&cru PCLK_RKPWM>;
336 uart2: serial@ff690000 {
337 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
338 reg = <0x0 0xff690000 0x0 0x100>;
339 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
341 clock-names = "baudclk", "apb_pclk";
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart2_t1_xfer>;
349 pmugrf: syscon@ff738000 {
350 compatible = "rockchip,rk3366-pmugrf", "syscon";
351 reg = <0x0 0xff738000 0x0 0x1000>;
355 compatible = "arm,amba-bus";
356 #address-cells = <2>;
360 dmac_peri: dma-controller@ff250000 {
361 compatible = "arm,pl330", "arm,primecell";
362 reg = <0x0 0xff250000 0x0 0x4000>;
363 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&cru ACLK_DMAC_PERI>;
367 clock-names = "apb_pclk";
370 dmac_bus: dma-controller@ff600000 {
371 compatible = "arm,pl330", "arm,primecell";
372 reg = <0x0 0xff600000 0x0 0x4000>;
373 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cru ACLK_DMAC_BUS>;
377 clock-names = "apb_pclk";
381 cru: clock-controller@ff760000 {
382 compatible = "rockchip,rk3366-cru";
383 reg = <0x0 0xff760000 0x0 0x1000>;
384 rockchip,grf = <&grf>;
389 grf: syscon@ff770000 {
390 compatible = "rockchip,rk3366-grf", "syscon";
391 reg = <0x0 0xff770000 0x0 0x1000>;
395 compatible = "rockchip,rk3366-pinctrl";
396 rockchip,grf = <&grf>;
397 rockchip,pmu = <&pmugrf>;
398 #address-cells = <0x2>;
402 gpio0: gpio0@ff750000 {
403 compatible = "rockchip,gpio-bank";
404 reg = <0x0 0xff750000 0x0 0x100>;
405 clocks = <&cru PCLK_GPIO0>;
406 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
411 interrupt-controller;
412 #interrupt-cells = <0x2>;
415 gpio1: gpio1@ff780000 {
416 compatible = "rockchip,gpio-bank";
417 reg = <0x0 0xff758000 0x0 0x100>;
418 clocks = <&cru PCLK_GPIO1>;
419 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-controller;
425 #interrupt-cells = <0x2>;
428 gpio2: gpio2@ff790000 {
429 compatible = "rockchip,gpio-bank";
430 reg = <0x0 0xff790000 0x0 0x100>;
431 clocks = <&cru PCLK_GPIO2>;
432 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
437 interrupt-controller;
438 #interrupt-cells = <0x2>;
441 gpio3: gpio3@ff7a0000 {
442 compatible = "rockchip,gpio-bank";
443 reg = <0x0 0xff7a0000 0x0 0x100>;
444 clocks = <&cru PCLK_GPIO3>;
445 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
450 interrupt-controller;
451 #interrupt-cells = <0x2>;
454 gpio4: gpio4@ff7b0000 {
455 compatible = "rockchip,gpio-bank";
456 reg = <0x0 0xff7b0000 0x0 0x100>;
457 clocks = <&cru PCLK_GPIO4>;
458 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-controller;
464 #interrupt-cells = <0x2>;
467 gpio5: gpio5@ff7c0000 {
468 compatible = "rockchip,gpio-bank";
469 reg = <0x0 0xff7c0000 0x0 0x100>;
470 clocks = <&cru PCLK_GPIO5>;
471 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <0x2>;
480 pcfg_pull_up: pcfg-pull-up {
484 pcfg_pull_down: pcfg-pull-down {
488 pcfg_pull_none: pcfg-pull-none {
492 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
494 drive-strength = <12>;
500 <3 4 RK_FUNC_2 &pcfg_pull_none>;
505 <2 26 RK_FUNC_2 &pcfg_pull_up>;
510 <2 27 RK_FUNC_2 &pcfg_pull_up>;
513 emmc_bus1: emmc-bus1 {
515 <2 18 RK_FUNC_2 &pcfg_pull_up>;
518 emmc_bus4: emmc-bus4 {
520 <2 18 RK_FUNC_2 &pcfg_pull_up>,
521 <2 19 RK_FUNC_2 &pcfg_pull_up>,
522 <2 20 RK_FUNC_2 &pcfg_pull_up>,
523 <2 21 RK_FUNC_2 &pcfg_pull_up>;
526 emmc_bus8: emmc-bus8 {
528 <2 18 RK_FUNC_2 &pcfg_pull_up>,
529 <2 19 RK_FUNC_2 &pcfg_pull_up>,
530 <2 20 RK_FUNC_2 &pcfg_pull_up>,
531 <2 21 RK_FUNC_2 &pcfg_pull_up>,
532 <2 22 RK_FUNC_2 &pcfg_pull_up>,
533 <2 23 RK_FUNC_2 &pcfg_pull_up>,
534 <2 24 RK_FUNC_2 &pcfg_pull_up>,
535 <2 25 RK_FUNC_2 &pcfg_pull_up>;
540 i2c0_xfer: i2c0-xfer {
542 <0 3 RK_FUNC_1 &pcfg_pull_none>,
543 <0 4 RK_FUNC_1 &pcfg_pull_none>;
548 i2c1_xfer: i2c1-xfer {
550 <4 19 RK_FUNC_1 &pcfg_pull_none>,
551 <4 20 RK_FUNC_1 &pcfg_pull_none>;
556 i2c2_xfer: i2c2-xfer {
558 <5 15 RK_FUNC_2 &pcfg_pull_none>,
559 <5 16 RK_FUNC_2 &pcfg_pull_none>;
564 i2c3_xfer: i2c3-xfer {
566 <2 16 RK_FUNC_2 &pcfg_pull_none>,
567 <2 17 RK_FUNC_2 &pcfg_pull_none>;
572 i2c4_xfer: i2c4-xfer {
574 <5 8 RK_FUNC_1 &pcfg_pull_none>,
575 <5 9 RK_FUNC_1 &pcfg_pull_none>;
580 i2c5_xfer: i2c5-xfer {
582 <5 13 RK_FUNC_1 &pcfg_pull_none>,
583 <5 14 RK_FUNC_1 &pcfg_pull_none>;
588 i2s_8ch_bus: i2s-8ch-bus {
590 <4 16 RK_FUNC_1 &pcfg_pull_none>,
591 <4 17 RK_FUNC_1 &pcfg_pull_none>,
592 <4 18 RK_FUNC_1 &pcfg_pull_none>,
593 <4 19 RK_FUNC_1 &pcfg_pull_none>,
594 <4 20 RK_FUNC_1 &pcfg_pull_none>,
595 <4 21 RK_FUNC_1 &pcfg_pull_none>,
596 <4 22 RK_FUNC_1 &pcfg_pull_none>,
597 <4 23 RK_FUNC_1 &pcfg_pull_none>,
598 <4 24 RK_FUNC_1 &pcfg_pull_none>;
605 <2 29 RK_FUNC_2 &pcfg_pull_up>;
609 <2 24 RK_FUNC_3 &pcfg_pull_up>;
613 <2 25 RK_FUNC_3 &pcfg_pull_up>;
617 <2 23 RK_FUNC_3 &pcfg_pull_up>;
621 <2 22 RK_FUNC_3 &pcfg_pull_up>;
628 <2 4 RK_FUNC_2 &pcfg_pull_up>;
632 <2 5 RK_FUNC_2 &pcfg_pull_up>;
636 <2 6 RK_FUNC_2 &pcfg_pull_up>;
640 <2 7 RK_FUNC_2 &pcfg_pull_up>;
645 uart0_xfer: uart0-xfer {
647 <3 8 RK_FUNC_1 &pcfg_pull_up>,
648 <3 9 RK_FUNC_1 &pcfg_pull_none>;
651 uart0_cts: uart0-cts {
653 <3 10 RK_FUNC_1 &pcfg_pull_none>;
656 uart0_rts: uart0-rts {
658 <3 11 RK_FUNC_1 &pcfg_pull_none>;
663 uart2_t0_xfer: uart2_t0-xfer {
665 <0 22 RK_FUNC_1 &pcfg_pull_up>,
666 <0 21 RK_FUNC_1 &pcfg_pull_none>;
668 /* no rts / cts for uart2 */
672 uart2_t1_xfer: uart2_t1-xfer {
674 <5 0 RK_FUNC_2 &pcfg_pull_up>,
675 <5 1 RK_FUNC_2 &pcfg_pull_none>;
677 /* no rts / cts for uart2 */
681 uart2_t2_xfer: uart2_t2-xfer {
683 <5 14 RK_FUNC_3 &pcfg_pull_up>,
684 <5 13 RK_FUNC_3 &pcfg_pull_none>;
686 /* no rts / cts for uart2 */
690 uart3_xfer: uart3-xfer {
692 <5 15 RK_FUNC_1 &pcfg_pull_up>,
693 <5 16 RK_FUNC_1 &pcfg_pull_none>;
696 uart3_cts: uart3-cts {
698 <5 17 RK_FUNC_1 &pcfg_pull_none>;
701 uart3_rts: uart3-rts {
703 <5 18 RK_FUNC_1 &pcfg_pull_none>;
710 <0 8 RK_FUNC_1 &pcfg_pull_none>;
717 <1 6 RK_FUNC_2 &pcfg_pull_none>;
722 pwm2_t0_pin: pwm2_t0-pin {
724 <2 15 RK_FUNC_3 &pcfg_pull_none>;
729 pwm2_t1_pin: pwm2_t1-pin {
731 <5 17 RK_FUNC_2 &pcfg_pull_none>;
736 pwm3_t0_pin: pwm3_t0-pin {
738 <1 0 RK_FUNC_2 &pcfg_pull_none>;
743 pwm3_t1_pin: pwm3_t1-pin {
745 <0 21 RK_FUNC_2 &pcfg_pull_none>;
750 pwm3_t2_pin: pwm3_t2-pin {
752 <5 18 RK_FUNC_2 &pcfg_pull_none>;