arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3328";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 serial0 = &uart0;
  60                 serial1 = &uart1;
  61                 serial2 = &uart2;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 cpu0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77 //                      clocks = <&cru ARMCLK>;
  78                         operating-points-v2 = <&cpu0_opp_table>;
  79                 };
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                 };
  86                 cpu2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x2>;
  90                         enable-method = "psci";
  91                 };
  92                 cpu3: cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x3>;
  96                         enable-method = "psci";
  97                 };
  98         };
  99
 100         cpu0_opp_table: opp_table0 {
 101                 compatible = "operating-points-v2";
 102                 opp-shared;
 103
 104                 opp@408000000 {
 105                         opp-hz = /bits/ 64 <408000000>;
 106                         opp-microvolt = <950000>;
 107                         clock-latency-ns = <40000>;
 108                         opp-suspend;
 109                 };
 110                 opp@600000000 {
 111                         opp-hz = /bits/ 64 <600000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                 };
 115                 opp@816000000 {
 116                         opp-hz = /bits/ 64 <816000000>;
 117                         opp-microvolt = <1000000>;
 118                         clock-latency-ns = <40000>;
 119                 };
 120                 opp@1008000000 {
 121                         opp-hz = /bits/ 64 <1008000000>;
 122                         opp-microvolt = <1100000>;
 123                         clock-latency-ns = <40000>;
 124                 };
 125                 opp@1200000000 {
 126                         opp-hz = /bits/ 64 <1200000000>;
 127                         opp-microvolt = <1225000>;
 128                         clock-latency-ns = <40000>;
 129                 };
 130                 opp@1296000000 {
 131                         opp-hz = /bits/ 64 <1296000000>;
 132                         opp-microvolt = <1300000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135         };
 136
 137         arm-pmu {
 138                 compatible = "arm,cortex-a53-pmu";
 139                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 143                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-1.0";
 148                 method = "smc";
 149         };
 150
 151         timer {
 152                 compatible = "arm,armv8-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 157         };
 158
 159         xin24m: xin24m {
 160                 compatible = "fixed-clock";
 161                 #clock-cells = <0>;
 162                 clock-frequency = <24000000>;
 163                 clock-output-names = "xin24m";
 164         };
 165
 166         i2s0: i2s@ff000000 {
 167                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 168                 reg = <0x0 0xff000000 0x0 0x1000>;
 169                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 171                 clock-names = "i2s_clk", "i2s_hclk";
 172                 dmas = <&dmac 11>, <&dmac 12>;
 173                 #dma-cells = <2>;
 174                 dma-names = "tx", "rx";
 175                 status = "disabled";
 176         };
 177
 178         i2s1: i2s@ff010000 {
 179                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 180                 reg = <0x0 0xff010000 0x0 0x1000>;
 181                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 dmas = <&dmac 14>, <&dmac 15>;
 185                 #dma-cells = <2>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s2: i2s@ff020000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff020000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 0>, <&dmac 1>;
 197                 #dma-cells = <2>;
 198                 dma-names = "tx", "rx";
 199                 pinctrl-names = "default", "sleep";
 200                 pinctrl-0 = <&i2s2m0_mclk
 201                              &i2s2m0_sclk
 202                              &i2s2m0_lrcktx
 203                              &i2s2m0_lrckrx
 204                              &i2s2m0_sdo
 205                              &i2s2m0_sdi>;
 206                 pinctrl-1 = <&i2s2m0_sleep>;
 207                 status = "disabled";
 208         };
 209
 210         spdif: spdif@ff030000 {
 211                 compatible = "rockchip,rk3328-spdif";
 212                 reg = <0x0 0xff030000 0x0 0x1000>;
 213                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 215                 clock-names = "mclk", "hclk";
 216                 dmas = <&dmac 10>;
 217                 #dma-cells = <1>;
 218                 dma-names = "tx";
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&spdifm2_tx>;
 221                 status = "disabled";
 222         };
 223
 224         grf: syscon@ff100000 {
 225                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 226                 reg = <0x0 0xff100000 0x0 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229
 230                 io_domains: io-domains {
 231                         compatible = "rockchip,rk3328-io-voltage-domain";
 232                         status = "disabled";
 233                 };
 234
 235                 power: power-controller {
 236                         compatible = "rockchip,rk3328-power-controller";
 237                         #power-domain-cells = <1>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241
 242                         pd_hevc@RK3328_PD_HEVC {
 243                                 reg = <RK3328_PD_HEVC>;
 244                         };
 245                         pd_video@RK3328_PD_VIDEO {
 246                                 reg = <RK3328_PD_VIDEO>;
 247                         };
 248                         pd_vpu@RK3328_PD_VPU {
 249                                 reg = <RK3328_PD_VPU>;
 250                         };
 251                 };
 252
 253                 reboot-mode {
 254                         compatible = "syscon-reboot-mode";
 255                         offset = <0x5c8>;
 256                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 257                         mode-charge = <BOOT_CHARGING>;
 258                         mode-fastboot = <BOOT_FASTBOOT>;
 259                         mode-loader = <BOOT_BL_DOWNLOAD>;
 260                         mode-normal = <BOOT_NORMAL>;
 261                         mode-recovery = <BOOT_RECOVERY>;
 262                         mode-ums = <BOOT_UMS>;
 263                 };
 264         };
 265
 266         uart0: serial@ff110000 {
 267                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 268                 reg = <0x0 0xff110000 0x0 0x100>;
 269                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 271                 clock-names = "baudclk", "apb_pclk";
 272                 reg-shift = <2>;
 273                 reg-io-width = <4>;
 274                 dmas = <&dmac 2>, <&dmac 3>;
 275                 #dma-cells = <2>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 278                 status = "disabled";
 279         };
 280
 281         uart1: serial@ff120000 {
 282                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 283                 reg = <0x0 0xff120000 0x0 0x100>;
 284                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 286                 clock-names = "sclk_uart", "pclk_uart";
 287                 reg-shift = <2>;
 288                 reg-io-width = <4>;
 289                 dmas = <&dmac 4>, <&dmac 5>;
 290                 #dma-cells = <2>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 293                 status = "disabled";
 294         };
 295
 296         uart2: serial@ff130000 {
 297                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 298                 reg = <0x0 0xff130000 0x0 0x100>;
 299                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 301                 clock-names = "baudclk", "apb_pclk";
 302                 reg-shift = <2>;
 303                 reg-io-width = <4>;
 304                 dmas = <&dmac 6>, <&dmac 7>;
 305                 #dma-cells = <2>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&uart2m1_xfer>;
 308                 status = "disabled";
 309         };
 310
 311         pmu: power-management@ff140000 {
 312                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 313                 reg = <0x0 0xff140000 0x0 0x1000>;
 314         };
 315
 316         i2c0: i2c@ff150000 {
 317                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 318                 reg = <0x0 0xff150000 0x0 0x1000>;
 319                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 323                 clock-names = "i2c", "pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         i2c1: i2c@ff160000 {
 330                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 331                 reg = <0x0 0xff160000 0x0 0x1000>;
 332                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 336                 clock-names = "i2c", "pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&i2c1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         i2c2: i2c@ff170000 {
 343                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 344                 reg = <0x0 0xff170000 0x0 0x1000>;
 345                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 349                 clock-names = "i2c", "pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@ff180000 {
 356                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 357                 reg = <0x0 0xff180000 0x0 0x1000>;
 358                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 362                 clock-names = "i2c", "pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         spi0: spi@ff190000 {
 369                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 370                 reg = <0x0 0xff190000 0x0 0x1000>;
 371                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac 8>, <&dmac 9>;
 377                 #dma-cells = <2>;
 378                 dma-names = "tx", "rx";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 381                 status = "disabled";
 382         };
 383
 384         wdt: watchdog@ff1a0000 {
 385                 compatible = "snps,dw-wdt";
 386                 reg = <0x0 0xff1a0000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 388                 status = "disabled";
 389         };
 390
 391         amba {
 392                 compatible = "simple-bus";
 393                 #address-cells = <2>;
 394                 #size-cells = <2>;
 395                 ranges;
 396
 397                 dmac: dmac@ff1f0000 {
 398                         compatible = "arm,pl330", "arm,primecell";
 399                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 400                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 401                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&cru ACLK_DMAC>;
 403                         clock-names = "apb_pclk";
 404                         #dma-cells = <1>;
 405                 };
 406         };
 407
 408         saradc: saradc@ff280000 {
 409                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 410                 reg = <0x0 0xff280000 0x0 0x100>;
 411                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 412                 #io-channel-cells = <1>;
 413                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 414                 clock-names = "saradc", "apb_pclk";
 415                 resets = <&cru SRST_SARADC_P>;
 416                 reset-names = "saradc-apb";
 417                 status = "disabled";
 418         };
 419
 420         cru: clock-controller@ff440000 {
 421                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 422                 reg = <0x0 0xff440000 0x0 0x1000>;
 423                 rockchip,grf = <&grf>;
 424                 #clock-cells = <1>;
 425                 #reset-cells = <1>;
 426                 assigned-clocks =
 427                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 428                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 429                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 430                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 431                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 432                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 433                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 434                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 435                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 436                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 437                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 438                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 439                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 440                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 441                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 442                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 443                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 444                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 445                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 446                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 447                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 448                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 449                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 450                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 451                 assigned-clock-parents =
 452                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 453                         <&cru PLL_GPLL>, <&xin24m>,
 454                         <&xin24m>, <&xin24m>;
 455                 assigned-clock-rates =
 456                         <0>, <61440000>,
 457                         <0>, <24000000>,
 458                         <24000000>, <24000000>,
 459                         <15000000>, <15000000>,
 460                         <100000000>, <100000000>,
 461                         <100000000>, <100000000>,
 462                         <50000000>, <100000000>,
 463                         <100000000>, <100000000>,
 464                         <50000000>, <50000000>,
 465                         <50000000>, <50000000>,
 466                         <24000000>, <600000000>,
 467                         <491520000>, <1200000000>,
 468                         <150000000>, <75000000>,
 469                         <75000000>, <150000000>,
 470                         <75000000>, <75000000>,
 471                         <300000000>, <100000000>,
 472                         <300000000>, <200000000>,
 473                         <400000000>, <500000000>,
 474                         <200000000>, <300000000>,
 475                         <300000000>, <250000000>,
 476                         <200000000>, <100000000>,
 477                         <24000000>, <100000000>,
 478                         <150000000>, <50000000>,
 479                         <32768>, <32768>;
 480         };
 481
 482         usb2phy_grf: syscon@ff450000 {
 483                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 484                              "simple-mfd";
 485                 reg = <0x0 0xff450000 0x0 0x10000>;
 486                 #address-cells = <1>;
 487                 #size-cells = <1>;
 488
 489                 u2phy: usb2-phy@100 {
 490                         compatible = "rockchip,rk3328-usb2phy";
 491                         reg = <0x100 0x10>;
 492                         clocks = <&xin24m>;
 493                         clock-names = "phyclk";
 494                         #clock-cells = <0>;
 495                         assigned-clocks = <&cru USB480M>;
 496                         assigned-clock-parents = <&u2phy>;
 497                         clock-output-names = "usb480m_phy";
 498                         status = "disabled";
 499
 500                         u2phy_host: host-port {
 501                                 #phy-cells = <0>;
 502                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 503                                 interrupt-names = "linestate";
 504                                 status = "disabled";
 505                         };
 506                 };
 507         };
 508
 509         usb3phy_grf: syscon@ff460000 {
 510                 compatible = "rockchip,usb3phy-grf", "syscon";
 511                 reg = <0x0 0xff460000 0x0 0x1000>;
 512         };
 513
 514         u3phy: usb3-phy@ff470000 {
 515                 compatible = "rockchip,rk3328-u3phy";
 516                 reg = <0x0 0xff470000 0x0 0x0>;
 517                 rockchip,u3phygrf = <&usb3phy_grf>;
 518                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 519                 interrupt-names = "linestate";
 520                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 521                 clock-names = "u3phy-otg", "u3phy-pipe";
 522                 resets = <&cru SRST_USB3PHY_U2>,
 523                          <&cru SRST_USB3PHY_U3>,
 524                          <&cru SRST_USB3PHY_PIPE>,
 525                          <&cru SRST_USB3OTG_UTMI>,
 526                          <&cru SRST_USB3PHY_OTG_P>,
 527                          <&cru SRST_USB3PHY_PIPE_P>;
 528                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 529                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 530                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 531                 #address-cells = <2>;
 532                 #size-cells = <2>;
 533                 ranges;
 534                 status = "disabled";
 535
 536                 u3phy_utmi: utmi@ff470000 {
 537                         reg = <0x0 0xff470000 0x0 0x8000>;
 538                         #phy-cells = <0>;
 539                         status = "disabled";
 540                 };
 541
 542                 u3phy_pipe: pipe@ff478000 {
 543                         reg = <0x0 0xff478000 0x0 0x8000>;
 544                         #phy-cells = <0>;
 545                         status = "disabled";
 546                 };
 547         };
 548
 549         sdmmc: rksdmmc@ff500000 {
 550                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 551                 reg = <0x0 0xff500000 0x0 0x4000>;
 552                 clock-freq-min-max = <400000 150000000>;
 553                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 554                 clock-names = "biu", "ciu";
 555                 fifo-depth = <0x100>;
 556                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 557                 status = "disabled";
 558         };
 559
 560         sdio: dwmmc@ff510000 {
 561                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 562                 reg = <0x0 0xff510000 0x0 0x4000>;
 563                 clock-freq-min-max = <400000 150000000>;
 564                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 565                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 566                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 567                 fifo-depth = <0x100>;
 568                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 569                 status = "disabled";
 570         };
 571
 572         emmc: rksdmmc@ff520000 {
 573                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 574                 reg = <0x0 0xff520000 0x0 0x4000>;
 575                 clock-freq-min-max = <400000 150000000>;
 576                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 577                 clock-names = "biu", "ciu";
 578                 fifo-depth = <0x100>;
 579                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 580                 status = "disabled";
 581         };
 582
 583         usb20_otg: usb@ff580000 {
 584                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 585                              "snps,dwc2";
 586                 reg = <0x0 0xff580000 0x0 0x40000>;
 587                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 588                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 589                 clock-names = "otg", "otg_pmu";
 590                 dr_mode = "otg";
 591                 g-np-tx-fifo-size = <16>;
 592                 g-rx-fifo-size = <275>;
 593                 g-tx-fifo-size = <256 128 128 64 64 32>;
 594                 g-use-dma;
 595                 status = "disabled";
 596         };
 597
 598         usb_host0_ehci: usb@ff5c0000 {
 599                 compatible = "generic-ehci";
 600                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 601                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 602                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 603                          <&u2phy>;
 604                 clock-names = "usbhost", "arbiter", "utmi";
 605                 phys = <&u2phy_host>;
 606                 phy-names = "usb";
 607                 status = "disabled";
 608         };
 609
 610         usb_host0_ohci: usb@ff5d0000 {
 611                 compatible = "generic-ohci";
 612                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 613                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 615                          <&u2phy>;
 616                 clock-names = "usbhost", "arbiter", "utmi";
 617                 phys = <&u2phy_host>;
 618                 phy-names = "usb";
 619                 status = "disabled";
 620         };
 621
 622         sdmmc_ext: rksdmmc@ff5f0000 {
 623                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 624                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 625                 clock-freq-min-max = <400000 150000000>;
 626                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 627                 clock-names = "biu", "ciu";
 628                 fifo-depth = <0x100>;
 629                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 630                 status = "disabled";
 631         };
 632
 633         usbdrd3: usb@ff600000 {
 634                 compatible = "rockchip,rk3328-dwc3";
 635                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 636                          <&cru ACLK_USB3OTG>;
 637                 clock-names = "ref_clk", "suspend_clk",
 638                               "bus_clk";
 639                 #address-cells = <2>;
 640                 #size-cells = <2>;
 641                 ranges;
 642                 status = "disabled";
 643
 644                 usbdrd_dwc3: dwc3@ff600000 {
 645                         compatible = "snps,dwc3";
 646                         reg = <0x0 0xff600000 0x0 0x100000>;
 647                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 648                         dr_mode = "host";
 649                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 650                         phy-names = "usb2-phy", "usb3-phy";
 651                         phy_type = "utmi_wide";
 652                         snps,dis_enblslpm_quirk;
 653                         snps,dis-u2-freeclk-exists-quirk;
 654                         snps,dis_u2_susphy_quirk;
 655                         snps,dis_u3_susphy_quirk;
 656                         snps,dis-del-phy-power-chg-quirk;
 657                         status = "disabled";
 658                 };
 659         };
 660
 661         gic: interrupt-controller@ff811000 {
 662                 compatible = "arm,gic-400";
 663                 #interrupt-cells = <3>;
 664                 #address-cells = <0>;
 665                 interrupt-controller;
 666                 reg = <0x0 0xff811000 0 0x1000>,
 667                       <0x0 0xff812000 0 0x2000>,
 668                       <0x0 0xff814000 0 0x2000>,
 669                       <0x0 0xff816000 0 0x2000>;
 670                 interrupts = <GIC_PPI 9
 671                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 672         };
 673
 674         pinctrl: pinctrl {
 675                 compatible = "rockchip,rk3328-pinctrl";
 676                 rockchip,grf = <&grf>;
 677                 #address-cells = <2>;
 678                 #size-cells = <2>;
 679                 ranges;
 680
 681                 gpio0: gpio0@ff210000 {
 682                         compatible = "rockchip,gpio-bank";
 683                         reg = <0x0 0xff210000 0x0 0x100>;
 684                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 685                         clocks = <&cru PCLK_GPIO0>;
 686
 687                         gpio-controller;
 688                         #gpio-cells = <2>;
 689
 690                         interrupt-controller;
 691                         #interrupt-cells = <2>;
 692                 };
 693
 694                 gpio1: gpio1@ff220000 {
 695                         compatible = "rockchip,gpio-bank";
 696                         reg = <0x0 0xff220000 0x0 0x100>;
 697                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 698                         clocks = <&cru PCLK_GPIO1>;
 699
 700                         gpio-controller;
 701                         #gpio-cells = <2>;
 702
 703                         interrupt-controller;
 704                         #interrupt-cells = <2>;
 705                 };
 706
 707                 gpio2: gpio2@ff230000 {
 708                         compatible = "rockchip,gpio-bank";
 709                         reg = <0x0 0xff230000 0x0 0x100>;
 710                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&cru PCLK_GPIO2>;
 712
 713                         gpio-controller;
 714                         #gpio-cells = <2>;
 715
 716                         interrupt-controller;
 717                         #interrupt-cells = <2>;
 718                 };
 719
 720                 gpio3: gpio3@ff240000 {
 721                         compatible = "rockchip,gpio-bank";
 722                         reg = <0x0 0xff240000 0x0 0x100>;
 723                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&cru PCLK_GPIO3>;
 725
 726                         gpio-controller;
 727                         #gpio-cells = <2>;
 728
 729                         interrupt-controller;
 730                         #interrupt-cells = <2>;
 731                 };
 732
 733                 pcfg_pull_up: pcfg-pull-up {
 734                         bias-pull-up;
 735                 };
 736
 737                 pcfg_pull_down: pcfg-pull-down {
 738                         bias-pull-down;
 739                 };
 740
 741                 pcfg_pull_none: pcfg-pull-none {
 742                         bias-disable;
 743                 };
 744
 745                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 746                         bias-disable;
 747                         drive-strength = <2>;
 748                 };
 749
 750                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 751                         bias-pull-up;
 752                         drive-strength = <2>;
 753                 };
 754
 755                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 756                         bias-pull-up;
 757                         drive-strength = <4>;
 758                 };
 759
 760                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 761                         bias-disable;
 762                         drive-strength = <4>;
 763                 };
 764
 765                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 766                         bias-pull-down;
 767                         drive-strength = <4>;
 768                 };
 769
 770                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 771                         bias-disable;
 772                         drive-strength = <8>;
 773                 };
 774
 775                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 776                         bias-pull-up;
 777                         drive-strength = <8>;
 778                 };
 779
 780                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 781                         bias-disable;
 782                         drive-strength = <12>;
 783                 };
 784
 785                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 786                         bias-pull-up;
 787                         drive-strength = <12>;
 788                 };
 789
 790                 pcfg_output_high: pcfg-output-high {
 791                         output-high;
 792                 };
 793
 794                 pcfg_output_low: pcfg-output-low {
 795                         output-low;
 796                 };
 797
 798                 pcfg_input_high: pcfg-input-high {
 799                         bias-pull-up;
 800                         input-enable;
 801                 };
 802
 803                 pcfg_input: pcfg-input {
 804                         input-enable;
 805                 };
 806
 807                 i2c0 {
 808                         i2c0_xfer: i2c0-xfer {
 809                                 rockchip,pins =
 810                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 811                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 812                         };
 813                 };
 814
 815                 i2c1 {
 816                         i2c1_xfer: i2c1-xfer {
 817                                 rockchip,pins =
 818                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 819                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 820                         };
 821                 };
 822
 823                 i2c2 {
 824                         i2c2_xfer: i2c2-xfer {
 825                                 rockchip,pins =
 826                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 827                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 828                         };
 829                 };
 830
 831                 i2c3 {
 832                         i2c3_xfer: i2c3-xfer {
 833                                 rockchip,pins =
 834                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 835                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 836                         };
 837                         i2c3_gpio: i2c3-gpio {
 838                                 rockchip,pins =
 839                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 840                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 841                         };
 842                 };
 843
 844                 hdmi_i2c {
 845                         hdmii2c_xfer: hdmii2c-xfer {
 846                                 rockchip,pins =
 847                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 848                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 849                         };
 850                 };
 851
 852                 uart0 {
 853                         uart0_xfer: uart0-xfer {
 854                                 rockchip,pins =
 855                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 856                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 857                         };
 858
 859                         uart0_cts: uart0-cts {
 860                                 rockchip,pins =
 861                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 862                         };
 863
 864                         uart0_rts: uart0-rts {
 865                                 rockchip,pins =
 866                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 867                         };
 868
 869                         uart0_rts_gpio: uart0-rts-gpio {
 870                                 rockchip,pins =
 871                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 872                         };
 873                 };
 874
 875                 uart1 {
 876                         uart1_xfer: uart1-xfer {
 877                                 rockchip,pins =
 878                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 879                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 880                         };
 881
 882                         uart1_cts: uart1-cts {
 883                                 rockchip,pins =
 884                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 885                         };
 886
 887                         uart1_rts: uart1-rts {
 888                                 rockchip,pins =
 889                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 890                         };
 891
 892                         uart1_rts_gpio: uart1-rts-gpio {
 893                                 rockchip,pins =
 894                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 895                         };
 896                 };
 897
 898                 uart2-0 {
 899                         uart2m0_xfer: uart2m0-xfer {
 900                                 rockchip,pins =
 901                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 902                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 903                         };
 904                 };
 905
 906                 uart2-1 {
 907                         uart2m1_xfer: uart2m1-xfer {
 908                                 rockchip,pins =
 909                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 910                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 911                         };
 912                 };
 913
 914                 spi0-0 {
 915                         spi0m0_clk: spi0m0-clk {
 916                                 rockchip,pins =
 917                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 918                         };
 919
 920                         spi0m0_cs0: spi0m0-cs0 {
 921                                 rockchip,pins =
 922                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 923                         };
 924
 925                         spi0m0_tx: spi0m0-tx {
 926                                 rockchip,pins =
 927                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 928                         };
 929
 930                         spi0m0_rx: spi0m0-rx {
 931                                 rockchip,pins =
 932                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 933                         };
 934
 935                         spi0m0_cs1: spi0m0-cs1 {
 936                                 rockchip,pins =
 937                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 938                         };
 939                 };
 940
 941                 spi0-1 {
 942                         spi0m1_clk: spi0m1-clk {
 943                                 rockchip,pins =
 944                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 945                         };
 946
 947                         spi0m1_cs0: spi0m1-cs0 {
 948                                 rockchip,pins =
 949                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 950                         };
 951
 952                         spi0m1_tx: spi0m1-tx {
 953                                 rockchip,pins =
 954                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 955                         };
 956
 957                         spi0m1_rx: spi0m1-rx {
 958                                 rockchip,pins =
 959                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 960                         };
 961
 962                         spi0m1_cs1: spi0m1-cs1 {
 963                                 rockchip,pins =
 964                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 965                         };
 966                 };
 967
 968                 spi0-2 {
 969                         spi0m2_clk: spi0m2-clk {
 970                                 rockchip,pins =
 971                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 972                         };
 973
 974                         spi0m2_cs0: spi0m2-cs0 {
 975                                 rockchip,pins =
 976                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 977                         };
 978
 979                         spi0m2_tx: spi0m2-tx {
 980                                 rockchip,pins =
 981                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 982                         };
 983
 984                         spi0m2_rx: spi0m2-rx {
 985                                 rockchip,pins =
 986                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 987                         };
 988                 };
 989
 990                 i2s1 {
 991                         i2s1_mclk: i2s1-mclk {
 992                                 rockchip,pins =
 993                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 994                         };
 995
 996                         i2s1_sclk: i2s1-sclk {
 997                                 rockchip,pins =
 998                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 999                         };
1000
1001                         i2s1_lrckrx: i2s1-lrckrx {
1002                                 rockchip,pins =
1003                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
1004                         };
1005
1006                         i2s1_lrcktx: i2s1-lrcktx {
1007                                 rockchip,pins =
1008                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1009                         };
1010
1011                         i2s1_sdi: i2s1-sdi {
1012                                 rockchip,pins =
1013                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1014                         };
1015
1016                         i2s1_sdo: i2s1-sdo {
1017                                 rockchip,pins =
1018                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
1019                         };
1020
1021                         i2s1_sdio1: i2s1-sdio1 {
1022                                 rockchip,pins =
1023                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
1024                         };
1025
1026                         i2s1_sdio2: i2s1-sdio2 {
1027                                 rockchip,pins =
1028                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
1029                         };
1030
1031                         i2s1_sdio3: i2s1-sdio3 {
1032                                 rockchip,pins =
1033                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
1034                         };
1035
1036                         i2s1_sleep: i2s1-sleep {
1037                                 rockchip,pins =
1038                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1039                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1040                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1041                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1042                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1043                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1044                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1045                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1046                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1047                         };
1048                 };
1049
1050                 i2s2-0 {
1051                         i2s2m0_mclk: i2s2m0-mclk {
1052                                 rockchip,pins =
1053                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1054                         };
1055
1056                         i2s2m0_sclk: i2s2m0-sclk {
1057                                 rockchip,pins =
1058                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
1059                         };
1060
1061                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1062                                 rockchip,pins =
1063                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
1064                         };
1065
1066                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1067                                 rockchip,pins =
1068                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1069                         };
1070
1071                         i2s2m0_sdi: i2s2m0-sdi {
1072                                 rockchip,pins =
1073                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1074                         };
1075
1076                         i2s2m0_sdo: i2s2m0-sdo {
1077                                 rockchip,pins =
1078                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1079                         };
1080
1081                         i2s2m0_sleep: i2s2m0-sleep {
1082                                 rockchip,pins =
1083                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1084                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1085                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1086                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1087                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1088                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1089                         };
1090                 };
1091
1092                 i2s2-1 {
1093                         i2s2m1_mclk: i2s2m1-mclk {
1094                                 rockchip,pins =
1095                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1096                         };
1097
1098                         i2s2m1_sclk: i2s2m1-sclk {
1099                                 rockchip,pins =
1100                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1101                         };
1102
1103                         i2s2m1_lrckrx: i2sm1-lrckrx {
1104                                 rockchip,pins =
1105                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1106                         };
1107
1108                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1109                                 rockchip,pins =
1110                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1111                         };
1112
1113                         i2s2m1_sdi: i2s2m1-sdi {
1114                                 rockchip,pins =
1115                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1116                         };
1117
1118                         i2s2m1_sdo: i2s2m1-sdo {
1119                                 rockchip,pins =
1120                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1121                         };
1122
1123                         i2s2m1_sleep: i2s2m1-sleep {
1124                                 rockchip,pins =
1125                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1126                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1127                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1128                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1129                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1130                         };
1131                 };
1132
1133                 spdif-0 {
1134                         spdifm0_tx: spdifm0-tx {
1135                                 rockchip,pins =
1136                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1137                         };
1138                 };
1139
1140                 spdif-1 {
1141                         spdifm1_tx: spdifm1-tx {
1142                                 rockchip,pins =
1143                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1144                         };
1145                 };
1146
1147                 spdif-2 {
1148                         spdifm2_tx: spdifm2-tx {
1149                                 rockchip,pins =
1150                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1151                         };
1152                 };
1153
1154                 sdmmc0-0 {
1155                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1156                                 rockchip,pins =
1157                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1158                         };
1159
1160                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1161                                 rockchip,pins =
1162                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1163                         };
1164                 };
1165
1166                 sdmmc0-1 {
1167                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1168                                 rockchip,pins =
1169                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1170                         };
1171
1172                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1173                                 rockchip,pins =
1174                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1175                         };
1176                 };
1177
1178                 sdmmc0 {
1179                         sdmmc0_clk: sdmmc0-clk {
1180                                 rockchip,pins =
1181                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1182                         };
1183
1184                         sdmmc0_cmd: sdmmc0-cmd {
1185                                 rockchip,pins =
1186                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1187                         };
1188
1189                         sdmmc0_dectn: sdmmc0-dectn {
1190                                 rockchip,pins =
1191                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1192                         };
1193
1194                         sdmmc0_wrprt: sdmmc0-wrprt {
1195                                 rockchip,pins =
1196                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1197                         };
1198
1199                         sdmmc0_bus1: sdmmc0-bus1 {
1200                                 rockchip,pins =
1201                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1202                         };
1203
1204                         sdmmc0_bus4: sdmmc0-bus4 {
1205                                 rockchip,pins =
1206                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1207                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1208                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1209                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1210                         };
1211
1212                         sdmmc0_gpio: sdmmc0-gpio {
1213                                 rockchip,pins =
1214                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1215                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1216                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1217                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1218                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1219                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1220                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1221                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1222                         };
1223                 };
1224
1225                 sdmmc0ext {
1226                         sdmmc0ext_clk: sdmmc0ext-clk {
1227                                 rockchip,pins =
1228                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1229                         };
1230
1231                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1232                                 rockchip,pins =
1233                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1234                         };
1235
1236                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1237                                 rockchip,pins =
1238                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1239                         };
1240
1241                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1242                                 rockchip,pins =
1243                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1244                         };
1245
1246                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1247                                 rockchip,pins =
1248                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1249                         };
1250
1251                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1252                                 rockchip,pins =
1253                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1254                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1255                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1256                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1257                         };
1258
1259                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1260                                 rockchip,pins =
1261                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1262                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1263                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1264                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1265                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1266                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1267                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1268                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1269                         };
1270                 };
1271
1272                 sdmmc1 {
1273                         sdmmc1_clk: sdmmc1-clk {
1274                                 rockchip,pins =
1275                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1276                         };
1277
1278                         sdmmc1_cmd: sdmmc1-cmd {
1279                                 rockchip,pins =
1280                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1281                         };
1282
1283                         sdmmc1_pwren: sdmmc1-pwren {
1284                                 rockchip,pins =
1285                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1286                         };
1287
1288                         sdmmc1_wrprt: sdmmc1-wrprt {
1289                                 rockchip,pins =
1290                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1291                         };
1292
1293                         sdmmc1_dectn: sdmmc1-dectn {
1294                                 rockchip,pins =
1295                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1296                         };
1297
1298                         sdmmc1_bus1: sdmmc1-bus1 {
1299                                 rockchip,pins =
1300                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1301                         };
1302
1303                         sdmmc1_bus4: sdmmc1-bus4 {
1304                                 rockchip,pins =
1305                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1306                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1307                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1308                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1309                         };
1310
1311                         sdmmc1_gpio: sdmmc1-gpio {
1312                                 rockchip,pins =
1313                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1314                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1315                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1316                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1317                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1318                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1319                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1320                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1321                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1322                         };
1323                 };
1324
1325                 emmc {
1326                         emmc_clk: emmc-clk {
1327                                 rockchip,pins =
1328                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1329                         };
1330
1331                         emmc_cmd: emmc-cmd {
1332                                 rockchip,pins =
1333                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1334                         };
1335
1336                         emmc_pwren: emmc-pwren {
1337                                 rockchip,pins =
1338                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1339                         };
1340
1341                         emmc_rstnout: emmc-rstnout {
1342                                 rockchip,pins =
1343                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1344                         };
1345
1346                         emmc_bus1: emmc-bus1 {
1347                                 rockchip,pins =
1348                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1349                         };
1350
1351                         emmc_bus4: emmc-bus4 {
1352                                 rockchip,pins =
1353                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1354                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1355                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1356                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1357                         };
1358
1359                         emmc_bus8: emmc-bus8 {
1360                                 rockchip,pins =
1361                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1362                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1363                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1364                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1365                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1366                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1367                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1368                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1369                         };
1370                 };
1371
1372                 pwm0 {
1373                         pwm0_pin: pwm0-pin {
1374                                 rockchip,pins =
1375                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1376                         };
1377                 };
1378
1379                 pwm1 {
1380                         pwm1_pin: pwm1-pin {
1381                                 rockchip,pins =
1382                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1383                         };
1384                 };
1385
1386                 pwm2 {
1387                         pwm2_pin: pwm2-pin {
1388                                 rockchip,pins =
1389                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1390                         };
1391                 };
1392
1393                 pwmir {
1394                         pwmir_pin: pwmir-pin {
1395                                 rockchip,pins =
1396                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398                 };
1399
1400                 gmac-0 {
1401                         rgmiim0_pins: rgmiim0-pins {
1402                                 rockchip,pins =
1403                                         /* mac_txclk */
1404                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1405                                         /* mac_rxclk */
1406                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1407                                         /* mac_mdio */
1408                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1409                                         /* mac_txen */
1410                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1411                                         /* mac_clk */
1412                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1413                                         /* mac_rxdv */
1414                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1415                                         /* mac_mdc */
1416                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1417                                         /* mac_rxd1 */
1418                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1419                                         /* mac_rxd0 */
1420                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1421                                         /* mac_txd1 */
1422                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1423                                         /* mac_txd0 */
1424                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1425                                         /* mac_rxd3 */
1426                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1427                                         /* mac_rxd2 */
1428                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1429                                         /* mac_txd3 */
1430                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1431                                         /* mac_txd2 */
1432                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1433                         };
1434
1435                         rmiim0_pins: rmiim0-pins {
1436                                 rockchip,pins =
1437                                         /* mac_mdio */
1438                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1439                                         /* mac_txen */
1440                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1441                                         /* mac_clk */
1442                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1443                                         /* mac_rxer */
1444                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1445                                         /* mac_rxdv */
1446                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1447                                         /* mac_mdc */
1448                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1449                                         /* mac_rxd1 */
1450                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1451                                         /* mac_rxd0 */
1452                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1453                                         /* mac_txd1 */
1454                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1455                                         /* mac_txd0 */
1456                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1457                         };
1458                 };
1459
1460                 gmac-1 {
1461                         rgmiim1_pins: rgmiim1-pins {
1462                                 rockchip,pins =
1463                                         /* mac_txclk */
1464                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1465                                         /* mac_rxclk */
1466                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1467                                         /* mac_mdio */
1468                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1469                                         /* mac_txen */
1470                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1471                                         /* mac_clk */
1472                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1473                                         /* mac_rxdv */
1474                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1475                                         /* mac_mdc */
1476                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1477                                         /* mac_rxd1 */
1478                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1479                                         /* mac_rxd0 */
1480                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1481                                         /* mac_txd1 */
1482                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1483                                         /* mac_txd0 */
1484                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1485                                         /* mac_rxd3 */
1486                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1487                                         /* mac_rxd2 */
1488                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1489                                         /* mac_txd3 */
1490                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1491                                         /* mac_txd2 */
1492                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1493
1494                                         /* mac_txclk */
1495                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1496                                         /* mac_txen */
1497                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1498                                         /* mac_clk */
1499                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1500                                         /* mac_txd1 */
1501                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1502                                         /* mac_txd0 */
1503                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1504                                         /* mac_txd3 */
1505                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1506                                         /* mac_txd2 */
1507                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1508                         };
1509
1510                         rmiim1_pins: rmiim1-pins {
1511                                 rockchip,pins =
1512                                         /* mac_mdio */
1513                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1514                                         /* mac_txen */
1515                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1516                                         /* mac_clk */
1517                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1518                                         /* mac_rxer */
1519                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1520                                         /* mac_rxdv */
1521                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1522                                         /* mac_mdc */
1523                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1524                                         /* mac_rxd1 */
1525                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1526                                         /* mac_rxd0 */
1527                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1528                                         /* mac_txd1 */
1529                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1530                                         /* mac_txd0 */
1531                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1532
1533                                         /* mac_mdio */
1534                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1535                                         /* mac_txen */
1536                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1537                                         /* mac_clk */
1538                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1539                                         /* mac_mdc */
1540                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1541                                         /* mac_txd1 */
1542                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1543                                         /* mac_txd0 */
1544                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1545                         };
1546                 };
1547
1548                 gmac2phy {
1549                         fephyled_speed100: fephyled-speed100 {
1550                                 rockchip,pins =
1551                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1552                         };
1553
1554                         fephyled_speed10: fephyled-speed10 {
1555                                 rockchip,pins =
1556                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1557                         };
1558
1559                         fephyled_duplex: fephyled-duplex {
1560                                 rockchip,pins =
1561                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1562                         };
1563
1564                         fephyled_rxm0: fephyled-rxm0 {
1565                                 rockchip,pins =
1566                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1567                         };
1568
1569                         fephyled_txm0: fephyled-txm0 {
1570                                 rockchip,pins =
1571                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1572                         };
1573
1574                         fephyled_linkm0: fephyled-linkm0 {
1575                                 rockchip,pins =
1576                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1577                         };
1578
1579                         fephyled_rxm1: fephyled-rxm1 {
1580                                 rockchip,pins =
1581                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1582                         };
1583
1584                         fephyled_txm1: fephyled-txm1 {
1585                                 rockchip,pins =
1586                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1587                         };
1588
1589                         fephyled_linkm1: fephyled-linkm1 {
1590                                 rockchip,pins =
1591                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1592                         };
1593                 };
1594
1595                 tsadc_pin {
1596                         tsadc_int: tsadc-int {
1597                                 rockchip,pins =
1598                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1599                         };
1600                         tsadc_gpio: tsadc-gpio {
1601                                 rockchip,pins =
1602                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1603                         };
1604                 };
1605
1606                 hdmi_pin {
1607                         hdmi_cec: hdmi-cec {
1608                                 rockchip,pins =
1609                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1610                         };
1611
1612                         hdmi_hpd: hdmi-hpd {
1613                                 rockchip,pins =
1614                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1615                         };
1616                 };
1617
1618                 cif-0 {
1619                         dvp_d2d9_m0:dvp-d2d9-m0 {
1620                                 rockchip,pins =
1621                                         /* cif_d0 */
1622                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1623                                         /* cif_d1 */
1624                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1625                                         /* cif_d2 */
1626                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1627                                         /* cif_d3 */
1628                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1629                                         /* cif_d4 */
1630                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1631                                         /* cif_d5m0 */
1632                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1633                                         /* cif_d6m0 */
1634                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1635                                         /* cif_d7m0 */
1636                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1637                                         /* cif_href */
1638                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1639                                         /* cif_vsync */
1640                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1641                                         /* cif_clkoutm0 */
1642                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1643                                         /* cif_clkin */
1644                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1645                         };
1646                 };
1647
1648                 cif-1 {
1649                         dvp_d2d9_m1:dvp-d2d9-m1 {
1650                                 rockchip,pins =
1651                                         /* cif_d0 */
1652                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1653                                         /* cif_d1 */
1654                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1655                                         /* cif_d2 */
1656                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1657                                         /* cif_d3 */
1658                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1659                                         /* cif_d4 */
1660                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1661                                         /* cif_d5m1 */
1662                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1663                                         /* cif_d6m1 */
1664                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1665                                         /* cif_d7m1 */
1666                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1667                                         /* cif_href */
1668                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1669                                         /* cif_vsync */
1670                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1671                                         /* cif_clkoutm1 */
1672                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1673                                         /* cif_clkin */
1674                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1675                         };
1676                 };
1677         };
1678 };