arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3328";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         dynamic-power-coefficient = <120>;
  81                         operating-points-v2 = <&cpu0_opp_table>;
  82                 };
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                         operating-points-v2 = <&cpu0_opp_table>;
  89                 };
  90                 cpu2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53", "arm,armv8";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                 };
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                 };
 104         };
 105
 106         cpu0_opp_table: opp_table0 {
 107                 compatible = "operating-points-v2";
 108                 opp-shared;
 109
 110                 opp@408000000 {
 111                         opp-hz = /bits/ 64 <408000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                         opp-suspend;
 115                 };
 116                 opp@600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <950000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp@816000000 {
 122                         opp-hz = /bits/ 64 <816000000>;
 123                         opp-microvolt = <1000000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126                 opp@1008000000 {
 127                         opp-hz = /bits/ 64 <1008000000>;
 128                         opp-microvolt = <1100000>;
 129                         clock-latency-ns = <40000>;
 130                 };
 131                 opp@1200000000 {
 132                         opp-hz = /bits/ 64 <1200000000>;
 133                         opp-microvolt = <1225000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@1296000000 {
 137                         opp-hz = /bits/ 64 <1296000000>;
 138                         opp-microvolt = <1300000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141         };
 142
 143         arm-pmu {
 144                 compatible = "arm,cortex-a53-pmu";
 145                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 149                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 150         };
 151
 152         cpuinfo {
 153                 compatible = "rockchip,cpuinfo";
 154                 nvmem-cells = <&efuse_id>;
 155                 nvmem-cell-names = "id";
 156         };
 157
 158         psci {
 159                 compatible = "arm,psci-1.0";
 160                 method = "smc";
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv8-timer";
 165                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 169         };
 170
 171         xin24m: xin24m {
 172                 compatible = "fixed-clock";
 173                 #clock-cells = <0>;
 174                 clock-frequency = <24000000>;
 175                 clock-output-names = "xin24m";
 176         };
 177
 178         i2s0: i2s@ff000000 {
 179                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 180                 reg = <0x0 0xff000000 0x0 0x1000>;
 181                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 dmas = <&dmac 11>, <&dmac 12>;
 185                 #dma-cells = <2>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s1: i2s@ff010000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff010000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 14>, <&dmac 15>;
 197                 #dma-cells = <2>;
 198                 dma-names = "tx", "rx";
 199                 status = "disabled";
 200         };
 201
 202         i2s2: i2s@ff020000 {
 203                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 204                 reg = <0x0 0xff020000 0x0 0x1000>;
 205                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 207                 clock-names = "i2s_clk", "i2s_hclk";
 208                 dmas = <&dmac 0>, <&dmac 1>;
 209                 #dma-cells = <2>;
 210                 dma-names = "tx", "rx";
 211                 pinctrl-names = "default", "sleep";
 212                 pinctrl-0 = <&i2s2m0_mclk
 213                              &i2s2m0_sclk
 214                              &i2s2m0_lrcktx
 215                              &i2s2m0_lrckrx
 216                              &i2s2m0_sdo
 217                              &i2s2m0_sdi>;
 218                 pinctrl-1 = <&i2s2m0_sleep>;
 219                 status = "disabled";
 220         };
 221
 222         spdif: spdif@ff030000 {
 223                 compatible = "rockchip,rk3328-spdif";
 224                 reg = <0x0 0xff030000 0x0 0x1000>;
 225                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 227                 clock-names = "mclk", "hclk";
 228                 dmas = <&dmac 10>;
 229                 #dma-cells = <1>;
 230                 dma-names = "tx";
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&spdifm2_tx>;
 233                 status = "disabled";
 234         };
 235
 236         pdm: pdm@ff040000 {
 237                 compatible = "rockchip,pdm";
 238                 reg = <0x0 0xff040000 0x0 0x1000>;
 239                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 240                 clock-names = "pdm_clk", "pdm_hclk";
 241                 dmas = <&dmac 16>;
 242                 #dma-cells = <1>;
 243                 dma-names = "rx";
 244                 pinctrl-names = "default", "sleep";
 245                 pinctrl-0 = <&pdmm0_clk
 246                              &pdmm0_fsync
 247                              &pdmm0_sdi0
 248                              &pdmm0_sdi1
 249                              &pdmm0_sdi2
 250                              &pdmm0_sdi3>;
 251                 pinctrl-1 = <&pdmm0_sleep>;
 252                 status = "disabled";
 253         };
 254
 255         grf: syscon@ff100000 {
 256                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 257                 reg = <0x0 0xff100000 0x0 0x1000>;
 258                 #address-cells = <1>;
 259                 #size-cells = <1>;
 260
 261                 io_domains: io-domains {
 262                         compatible = "rockchip,rk3328-io-voltage-domain";
 263                         status = "disabled";
 264                 };
 265
 266                 power: power-controller {
 267                         compatible = "rockchip,rk3328-power-controller";
 268                         #power-domain-cells = <1>;
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                         status = "disabled";
 272
 273                         pd_hevc@RK3328_PD_HEVC {
 274                                 reg = <RK3328_PD_HEVC>;
 275                         };
 276                         pd_video@RK3328_PD_VIDEO {
 277                                 reg = <RK3328_PD_VIDEO>;
 278                         };
 279                         pd_vpu@RK3328_PD_VPU {
 280                                 reg = <RK3328_PD_VPU>;
 281                         };
 282                 };
 283
 284                 reboot-mode {
 285                         compatible = "syscon-reboot-mode";
 286                         offset = <0x5c8>;
 287                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 288                         mode-charge = <BOOT_CHARGING>;
 289                         mode-fastboot = <BOOT_FASTBOOT>;
 290                         mode-loader = <BOOT_BL_DOWNLOAD>;
 291                         mode-normal = <BOOT_NORMAL>;
 292                         mode-recovery = <BOOT_RECOVERY>;
 293                         mode-ums = <BOOT_UMS>;
 294                 };
 295         };
 296
 297         thermal-zones {
 298                 soc_thermal: soc-thermal {
 299                         polling-delay-passive = <20>; /* milliseconds */
 300                         polling-delay = <1000>; /* milliseconds */
 301                         sustainable-power = <1000>; /* milliwatts */
 302
 303                         thermal-sensors = <&tsadc 0>;
 304
 305                         trips {
 306                                 threshold: trip-point@0 {
 307                                         temperature = <70000>; /* millicelsius */
 308                                         hysteresis = <2000>; /* millicelsius */
 309                                         type = "passive";
 310                                 };
 311                                 target: trip-point@1 {
 312                                         temperature = <85000>; /* millicelsius */
 313                                         hysteresis = <2000>; /* millicelsius */
 314                                         type = "passive";
 315                                 };
 316                                 soc_crit: soc-crit {
 317                                         temperature = <95000>; /* millicelsius */
 318                                         hysteresis = <2000>; /* millicelsius */
 319                                         type = "critical";
 320                                 };
 321                         };
 322
 323                         cooling-maps {
 324                                 map0 {
 325                                         trip = <&target>;
 326                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 327                                         contribution = <4096>;
 328                                 };
 329                         };
 330                 };
 331
 332         };
 333
 334         tsadc: tsadc@ff250000 {
 335                 compatible = "rockchip,rk3328-tsadc";
 336                 reg = <0x0 0xff250000 0x0 0x100>;
 337                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 338                 rockchip,grf = <&grf>;
 339                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 340                 clock-names = "tsadc", "apb_pclk";
 341                 assigned-clocks = <&cru SCLK_TSADC>;
 342                 assigned-clock-rates = <50000>;
 343                 resets = <&cru SRST_TSADC>;
 344                 reset-names = "tsadc-apb";
 345                 pinctrl-names = "init", "default", "sleep";
 346                 pinctrl-0 = <&otp_gpio>;
 347                 pinctrl-1 = <&otp_out>;
 348                 pinctrl-2 = <&otp_gpio>;
 349                 #thermal-sensor-cells = <1>;
 350                 rockchip,hw-tshut-temp = <100000>;
 351                 status = "disabled";
 352         };
 353
 354         uart0: serial@ff110000 {
 355                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 356                 reg = <0x0 0xff110000 0x0 0x100>;
 357                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 359                 clock-names = "baudclk", "apb_pclk";
 360                 reg-shift = <2>;
 361                 reg-io-width = <4>;
 362                 dmas = <&dmac 2>, <&dmac 3>;
 363                 #dma-cells = <2>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 366                 status = "disabled";
 367         };
 368
 369         uart1: serial@ff120000 {
 370                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 371                 reg = <0x0 0xff120000 0x0 0x100>;
 372                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 374                 clock-names = "sclk_uart", "pclk_uart";
 375                 reg-shift = <2>;
 376                 reg-io-width = <4>;
 377                 dmas = <&dmac 4>, <&dmac 5>;
 378                 #dma-cells = <2>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 381                 status = "disabled";
 382         };
 383
 384         uart2: serial@ff130000 {
 385                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 386                 reg = <0x0 0xff130000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 389                 clock-names = "baudclk", "apb_pclk";
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 dmas = <&dmac 6>, <&dmac 7>;
 393                 #dma-cells = <2>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&uart2m1_xfer>;
 396                 status = "disabled";
 397         };
 398
 399         pmu: power-management@ff140000 {
 400                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 401                 reg = <0x0 0xff140000 0x0 0x1000>;
 402         };
 403
 404         i2c0: i2c@ff150000 {
 405                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 406                 reg = <0x0 0xff150000 0x0 0x1000>;
 407                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 411                 clock-names = "i2c", "pclk";
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&i2c0_xfer>;
 414                 status = "disabled";
 415         };
 416
 417         i2c1: i2c@ff160000 {
 418                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 419                 reg = <0x0 0xff160000 0x0 0x1000>;
 420                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 424                 clock-names = "i2c", "pclk";
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&i2c1_xfer>;
 427                 status = "disabled";
 428         };
 429
 430         i2c2: i2c@ff170000 {
 431                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 432                 reg = <0x0 0xff170000 0x0 0x1000>;
 433                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 437                 clock-names = "i2c", "pclk";
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&i2c2_xfer>;
 440                 status = "disabled";
 441         };
 442
 443         i2c3: i2c@ff180000 {
 444                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 445                 reg = <0x0 0xff180000 0x0 0x1000>;
 446                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 450                 clock-names = "i2c", "pclk";
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&i2c3_xfer>;
 453                 status = "disabled";
 454         };
 455
 456         spi0: spi@ff190000 {
 457                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 458                 reg = <0x0 0xff190000 0x0 0x1000>;
 459                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 463                 clock-names = "spiclk", "apb_pclk";
 464                 dmas = <&dmac 8>, <&dmac 9>;
 465                 #dma-cells = <2>;
 466                 dma-names = "tx", "rx";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 469                 status = "disabled";
 470         };
 471
 472         wdt: watchdog@ff1a0000 {
 473                 compatible = "snps,dw-wdt";
 474                 reg = <0x0 0xff1a0000 0x0 0x100>;
 475                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 476                 status = "disabled";
 477         };
 478
 479         pwm0: pwm@ff1b0000 {
 480                 compatible = "rockchip,rk3328-pwm";
 481                 reg = <0x0 0xff1b0000 0x0 0x10>;
 482                 #pwm-cells = <3>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pwm0_pin>;
 485                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 486                 clock-names = "pwm", "pclk";
 487                 status = "disabled";
 488         };
 489
 490         pwm1: pwm@ff1b0010 {
 491                 compatible = "rockchip,rk3328-pwm";
 492                 reg = <0x0 0xff1b0010 0x0 0x10>;
 493                 #pwm-cells = <3>;
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&pwm1_pin>;
 496                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 497                 clock-names = "pwm", "pclk";
 498                 status = "disabled";
 499         };
 500
 501         pwm2: pwm@ff1b0020 {
 502                 compatible = "rockchip,rk3328-pwm";
 503                 reg = <0x0 0xff1b0020 0x0 0x10>;
 504                 #pwm-cells = <3>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&pwm2_pin>;
 507                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 508                 clock-names = "pwm", "pclk";
 509                 status = "disabled";
 510         };
 511
 512         pwm3: pwm@ff1b0030 {
 513                 compatible = "rockchip,rk3328-pwm";
 514                 reg = <0x0 0xff1b0030 0x0 0x10>;
 515                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 516                 #pwm-cells = <3>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&pwmir_pin>;
 519                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 520                 clock-names = "pwm", "pclk";
 521                 status = "disabled";
 522         };
 523
 524         amba {
 525                 compatible = "simple-bus";
 526                 #address-cells = <2>;
 527                 #size-cells = <2>;
 528                 ranges;
 529
 530                 dmac: dmac@ff1f0000 {
 531                         compatible = "arm,pl330", "arm,primecell";
 532                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 533                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 535                         clocks = <&cru ACLK_DMAC>;
 536                         clock-names = "apb_pclk";
 537                         #dma-cells = <1>;
 538                 };
 539         };
 540
 541         efuse: efuse@ff260000 {
 542                 compatible = "rockchip,rk3328-efuse";
 543                 reg = <0x0 0xff260000 0x0 0x50>;
 544                 #address-cells = <1>;
 545                 #size-cells = <1>;
 546                 clocks = <&cru SCLK_EFUSE>;
 547                 clock-names = "pclk_efuse";
 548                 rockchip,efuse-size = <0x20>;
 549
 550                 /* Data cells */
 551                 efuse_id: id@7 {
 552                         reg = <0x07 0x10>;
 553                 };
 554                 cpu_leakage: cpu-leakage@17 {
 555                         reg = <0x17 0x1>;
 556                 };
 557                 logic_leakage: logic-leakage@19 {
 558                         reg = <0x19 0x1>;
 559                 };
 560         };
 561
 562         saradc: saradc@ff280000 {
 563                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 564                 reg = <0x0 0xff280000 0x0 0x100>;
 565                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 566                 #io-channel-cells = <1>;
 567                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 568                 clock-names = "saradc", "apb_pclk";
 569                 resets = <&cru SRST_SARADC_P>;
 570                 reset-names = "saradc-apb";
 571                 status = "disabled";
 572         };
 573
 574         gpu: gpu@ff300000 {
 575                 compatible = "arm,mali-450";
 576                 /* first item of 'reg' is dummy, to fit src code. */
 577                 reg = <0x0 0xff300000 0x0 0x40000>,
 578                       <0x0 0xff300000 0x0 0x40000>;
 579                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 580                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 581                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 582                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 583                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 584                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 585                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 586                 interrupt-names = "Mali_GP_IRQ",
 587                                   "Mali_GP_MMU_IRQ",
 588                                   "IRQPP",
 589                                   "Mali_PP0_IRQ",
 590                                   "Mali_PP0_MMU_IRQ",
 591                                   "Mali_PP1_IRQ",
 592                                   "Mali_PP1_MMU_IRQ";
 593                 clocks = <&cru ACLK_GPU>;
 594                 clock-names = "clk_mali";
 595                 operating-points-v2 = <&gpu_opp_table>;
 596                 status = "disabled";
 597         };
 598
 599         gpu_opp_table: opp-table2 {
 600                 compatible = "operating-points-v2";
 601
 602                 opp@200000000 {
 603                         opp-hz = /bits/ 64 <200000000>;
 604                         opp-microvolt = <1050000>;
 605                 };
 606                 opp@300000000 {
 607                         opp-hz = /bits/ 64 <300000000>;
 608                         opp-microvolt = <1050000>;
 609                 };
 610                 opp@400000000 {
 611                         opp-hz = /bits/ 64 <400000000>;
 612                         opp-microvolt = <1050000>;
 613                 };
 614                 opp@500000000 {
 615                         opp-hz = /bits/ 64 <500000000>;
 616                         opp-microvolt = <1100000>;
 617                 };
 618         };
 619
 620         vop: vop@ff370000 {
 621                 compatible = "rockchip,rk3328-vop";
 622                 reg = <0x0 0xff370000 0x0 0x3efc>;
 623                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 624                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 625                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 626                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 627                 reset-names = "axi", "ahb", "dclk";
 628                 iommus = <&vop_mmu>;
 629                 status = "disabled";
 630
 631                 vop_out: port {
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634                 };
 635         };
 636
 637         vop_mmu: iommu@ff373f00 {
 638                 compatible = "rockchip,iommu";
 639                 reg = <0x0 0xff373f00 0x0 0x100>;
 640                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 641                 interrupt-names = "vop_mmu";
 642                 #iommu-cells = <0>;
 643                 status = "disabled";
 644         };
 645
 646         display_subsystem: display-subsystem {
 647                 compatible = "rockchip,display-subsystem";
 648                 ports = <&vop_out>;
 649                 status = "disabled";
 650         };
 651
 652         codec: codec@ff410000 {
 653                 compatible = "rockchip,rk3328-codec";
 654                 reg = <0x0 0xff410000 0x0 0x1000>;
 655                 rockchip,grf = <&grf>;
 656                 clocks = <&cru PCLK_ACODEC>;
 657                 clock-names = "pclk";
 658                 status = "disabled";
 659         };
 660
 661         cru: clock-controller@ff440000 {
 662                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 663                 reg = <0x0 0xff440000 0x0 0x1000>;
 664                 rockchip,grf = <&grf>;
 665                 #clock-cells = <1>;
 666                 #reset-cells = <1>;
 667                 assigned-clocks =
 668                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 669                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 670                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 671                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 672                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 673                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 674                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 675                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 676                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 677                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 678                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 679                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 680                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 681                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 682                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 683                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 684                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 685                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 686                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 687                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 688                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 689                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 690                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 691                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 692                 assigned-clock-parents =
 693                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 694                         <&cru PLL_GPLL>, <&xin24m>,
 695                         <&xin24m>, <&xin24m>;
 696                 assigned-clock-rates =
 697                         <0>, <61440000>,
 698                         <0>, <24000000>,
 699                         <24000000>, <24000000>,
 700                         <15000000>, <15000000>,
 701                         <100000000>, <100000000>,
 702                         <100000000>, <100000000>,
 703                         <50000000>, <100000000>,
 704                         <100000000>, <100000000>,
 705                         <50000000>, <50000000>,
 706                         <50000000>, <50000000>,
 707                         <24000000>, <600000000>,
 708                         <491520000>, <1200000000>,
 709                         <150000000>, <75000000>,
 710                         <75000000>, <150000000>,
 711                         <75000000>, <75000000>,
 712                         <300000000>, <100000000>,
 713                         <300000000>, <200000000>,
 714                         <400000000>, <500000000>,
 715                         <200000000>, <300000000>,
 716                         <300000000>, <250000000>,
 717                         <200000000>, <100000000>,
 718                         <24000000>, <100000000>,
 719                         <150000000>, <50000000>,
 720                         <32768>, <32768>;
 721         };
 722
 723         usb2phy_grf: syscon@ff450000 {
 724                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 725                              "simple-mfd";
 726                 reg = <0x0 0xff450000 0x0 0x10000>;
 727                 #address-cells = <1>;
 728                 #size-cells = <1>;
 729
 730                 u2phy: usb2-phy@100 {
 731                         compatible = "rockchip,rk3328-usb2phy";
 732                         reg = <0x100 0x10>;
 733                         clocks = <&xin24m>;
 734                         clock-names = "phyclk";
 735                         #clock-cells = <0>;
 736                         assigned-clocks = <&cru USB480M>;
 737                         assigned-clock-parents = <&u2phy>;
 738                         clock-output-names = "usb480m_phy";
 739                         status = "disabled";
 740
 741                         u2phy_host: host-port {
 742                                 #phy-cells = <0>;
 743                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 744                                 interrupt-names = "linestate";
 745                                 status = "disabled";
 746                         };
 747
 748                         u2phy_otg: otg-port {
 749                                 #phy-cells = <0>;
 750                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 751                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 752                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 753                                 interrupt-names = "otg-bvalid", "otg-id",
 754                                                   "linestate";
 755                                 status = "disabled";
 756                         };
 757                 };
 758         };
 759
 760         usb3phy_grf: syscon@ff460000 {
 761                 compatible = "rockchip,usb3phy-grf", "syscon";
 762                 reg = <0x0 0xff460000 0x0 0x1000>;
 763         };
 764
 765         u3phy: usb3-phy@ff470000 {
 766                 compatible = "rockchip,rk3328-u3phy";
 767                 reg = <0x0 0xff470000 0x0 0x0>;
 768                 rockchip,u3phygrf = <&usb3phy_grf>;
 769                 rockchip,grf = <&grf>;
 770                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 771                 interrupt-names = "linestate";
 772                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 773                 clock-names = "u3phy-otg", "u3phy-pipe";
 774                 resets = <&cru SRST_USB3PHY_U2>,
 775                          <&cru SRST_USB3PHY_U3>,
 776                          <&cru SRST_USB3PHY_PIPE>,
 777                          <&cru SRST_USB3OTG_UTMI>,
 778                          <&cru SRST_USB3PHY_OTG_P>,
 779                          <&cru SRST_USB3PHY_PIPE_P>;
 780                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 781                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 782                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 783                 #address-cells = <2>;
 784                 #size-cells = <2>;
 785                 ranges;
 786                 status = "disabled";
 787
 788                 u3phy_utmi: utmi@ff470000 {
 789                         reg = <0x0 0xff470000 0x0 0x8000>;
 790                         #phy-cells = <0>;
 791                         status = "disabled";
 792                 };
 793
 794                 u3phy_pipe: pipe@ff478000 {
 795                         reg = <0x0 0xff478000 0x0 0x8000>;
 796                         #phy-cells = <0>;
 797                         status = "disabled";
 798                 };
 799         };
 800
 801         sdmmc: rksdmmc@ff500000 {
 802                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 803                 reg = <0x0 0xff500000 0x0 0x4000>;
 804                 clock-freq-min-max = <400000 150000000>;
 805                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 806                 clock-names = "biu", "ciu";
 807                 fifo-depth = <0x100>;
 808                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 809                 status = "disabled";
 810         };
 811
 812         sdio: dwmmc@ff510000 {
 813                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 814                 reg = <0x0 0xff510000 0x0 0x4000>;
 815                 clock-freq-min-max = <400000 150000000>;
 816                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 817                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 818                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 819                 fifo-depth = <0x100>;
 820                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 821                 status = "disabled";
 822         };
 823
 824         emmc: rksdmmc@ff520000 {
 825                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 826                 reg = <0x0 0xff520000 0x0 0x4000>;
 827                 clock-freq-min-max = <400000 150000000>;
 828                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 829                 clock-names = "biu", "ciu";
 830                 fifo-depth = <0x100>;
 831                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 832                 status = "disabled";
 833         };
 834
 835         gmac2io: eth@ff540000 {
 836                 compatible = "rockchip,rk3328-gmac";
 837                 reg = <0x0 0xff540000 0x0 0x10000>;
 838                 rockchip,grf = <&grf>;
 839                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 840                 interrupt-names = "macirq";
 841                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 842                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 843                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 844                          <&cru PCLK_MAC2IO>;
 845                 clock-names = "stmmaceth", "mac_clk_rx",
 846                               "mac_clk_tx", "clk_mac_ref",
 847                               "clk_mac_refout", "aclk_mac",
 848                               "pclk_mac";
 849                 resets = <&cru SRST_GMAC2IO_A>;
 850                 reset-names = "stmmaceth";
 851                 status = "disabled";
 852         };
 853
 854         usb20_otg: usb@ff580000 {
 855                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 856                              "snps,dwc2";
 857                 reg = <0x0 0xff580000 0x0 0x40000>;
 858                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 859                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 860                 clock-names = "otg", "otg_pmu";
 861                 dr_mode = "otg";
 862                 g-np-tx-fifo-size = <16>;
 863                 g-rx-fifo-size = <275>;
 864                 g-tx-fifo-size = <256 128 128 64 64 32>;
 865                 g-use-dma;
 866                 phys = <&u2phy_otg>;
 867                 phy-names = "usb2-phy";
 868                 status = "disabled";
 869         };
 870
 871         usb_host0_ehci: usb@ff5c0000 {
 872                 compatible = "generic-ehci";
 873                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 874                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 875                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 876                          <&u2phy>;
 877                 clock-names = "usbhost", "arbiter", "utmi";
 878                 phys = <&u2phy_host>;
 879                 phy-names = "usb";
 880                 status = "disabled";
 881         };
 882
 883         usb_host0_ohci: usb@ff5d0000 {
 884                 compatible = "generic-ohci";
 885                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 886                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 887                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 888                          <&u2phy>;
 889                 clock-names = "usbhost", "arbiter", "utmi";
 890                 phys = <&u2phy_host>;
 891                 phy-names = "usb";
 892                 status = "disabled";
 893         };
 894
 895         sdmmc_ext: rksdmmc@ff5f0000 {
 896                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 897                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 898                 clock-freq-min-max = <400000 150000000>;
 899                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 900                 clock-names = "biu", "ciu";
 901                 fifo-depth = <0x100>;
 902                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 903                 status = "disabled";
 904         };
 905
 906         usbdrd3: usb@ff600000 {
 907                 compatible = "rockchip,rk3328-dwc3";
 908                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 909                          <&cru ACLK_USB3OTG>;
 910                 clock-names = "ref_clk", "suspend_clk",
 911                               "bus_clk";
 912                 #address-cells = <2>;
 913                 #size-cells = <2>;
 914                 ranges;
 915                 status = "disabled";
 916
 917                 usbdrd_dwc3: dwc3@ff600000 {
 918                         compatible = "snps,dwc3";
 919                         reg = <0x0 0xff600000 0x0 0x100000>;
 920                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 921                         dr_mode = "host";
 922                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 923                         phy-names = "usb2-phy", "usb3-phy";
 924                         phy_type = "utmi_wide";
 925                         snps,dis_enblslpm_quirk;
 926                         snps,dis-u2-freeclk-exists-quirk;
 927                         snps,dis_u2_susphy_quirk;
 928                         snps,dis-u3-autosuspend-quirk;
 929                         snps,dis_u3_susphy_quirk;
 930                         snps,dis-del-phy-power-chg-quirk;
 931                         status = "disabled";
 932                 };
 933         };
 934
 935         gic: interrupt-controller@ff811000 {
 936                 compatible = "arm,gic-400";
 937                 #interrupt-cells = <3>;
 938                 #address-cells = <0>;
 939                 interrupt-controller;
 940                 reg = <0x0 0xff811000 0 0x1000>,
 941                       <0x0 0xff812000 0 0x2000>,
 942                       <0x0 0xff814000 0 0x2000>,
 943                       <0x0 0xff816000 0 0x2000>;
 944                 interrupts = <GIC_PPI 9
 945                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 946         };
 947
 948         pinctrl: pinctrl {
 949                 compatible = "rockchip,rk3328-pinctrl";
 950                 rockchip,grf = <&grf>;
 951                 #address-cells = <2>;
 952                 #size-cells = <2>;
 953                 ranges;
 954
 955                 gpio0: gpio0@ff210000 {
 956                         compatible = "rockchip,gpio-bank";
 957                         reg = <0x0 0xff210000 0x0 0x100>;
 958                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 959                         clocks = <&cru PCLK_GPIO0>;
 960
 961                         gpio-controller;
 962                         #gpio-cells = <2>;
 963
 964                         interrupt-controller;
 965                         #interrupt-cells = <2>;
 966                 };
 967
 968                 gpio1: gpio1@ff220000 {
 969                         compatible = "rockchip,gpio-bank";
 970                         reg = <0x0 0xff220000 0x0 0x100>;
 971                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&cru PCLK_GPIO1>;
 973
 974                         gpio-controller;
 975                         #gpio-cells = <2>;
 976
 977                         interrupt-controller;
 978                         #interrupt-cells = <2>;
 979                 };
 980
 981                 gpio2: gpio2@ff230000 {
 982                         compatible = "rockchip,gpio-bank";
 983                         reg = <0x0 0xff230000 0x0 0x100>;
 984                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 985                         clocks = <&cru PCLK_GPIO2>;
 986
 987                         gpio-controller;
 988                         #gpio-cells = <2>;
 989
 990                         interrupt-controller;
 991                         #interrupt-cells = <2>;
 992                 };
 993
 994                 gpio3: gpio3@ff240000 {
 995                         compatible = "rockchip,gpio-bank";
 996                         reg = <0x0 0xff240000 0x0 0x100>;
 997                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 998                         clocks = <&cru PCLK_GPIO3>;
 999
1000                         gpio-controller;
1001                         #gpio-cells = <2>;
1002
1003                         interrupt-controller;
1004                         #interrupt-cells = <2>;
1005                 };
1006
1007                 pcfg_pull_up: pcfg-pull-up {
1008                         bias-pull-up;
1009                 };
1010
1011                 pcfg_pull_down: pcfg-pull-down {
1012                         bias-pull-down;
1013                 };
1014
1015                 pcfg_pull_none: pcfg-pull-none {
1016                         bias-disable;
1017                 };
1018
1019                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1020                         bias-disable;
1021                         drive-strength = <2>;
1022                 };
1023
1024                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1025                         bias-pull-up;
1026                         drive-strength = <2>;
1027                 };
1028
1029                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1030                         bias-pull-up;
1031                         drive-strength = <4>;
1032                 };
1033
1034                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1035                         bias-disable;
1036                         drive-strength = <4>;
1037                 };
1038
1039                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1040                         bias-pull-down;
1041                         drive-strength = <4>;
1042                 };
1043
1044                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1045                         bias-disable;
1046                         drive-strength = <8>;
1047                 };
1048
1049                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1050                         bias-pull-up;
1051                         drive-strength = <8>;
1052                 };
1053
1054                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1055                         bias-disable;
1056                         drive-strength = <12>;
1057                 };
1058
1059                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1060                         bias-pull-up;
1061                         drive-strength = <12>;
1062                 };
1063
1064                 pcfg_output_high: pcfg-output-high {
1065                         output-high;
1066                 };
1067
1068                 pcfg_output_low: pcfg-output-low {
1069                         output-low;
1070                 };
1071
1072                 pcfg_input_high: pcfg-input-high {
1073                         bias-pull-up;
1074                         input-enable;
1075                 };
1076
1077                 pcfg_input: pcfg-input {
1078                         input-enable;
1079                 };
1080
1081                 i2c0 {
1082                         i2c0_xfer: i2c0-xfer {
1083                                 rockchip,pins =
1084                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1085                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1086                         };
1087                 };
1088
1089                 i2c1 {
1090                         i2c1_xfer: i2c1-xfer {
1091                                 rockchip,pins =
1092                                         <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1093                                         <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>;
1094                         };
1095                 };
1096
1097                 i2c2 {
1098                         i2c2_xfer: i2c2-xfer {
1099                                 rockchip,pins =
1100                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1101                                         <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
1102                         };
1103                 };
1104
1105                 i2c3 {
1106                         i2c3_xfer: i2c3-xfer {
1107                                 rockchip,pins =
1108                                         <0 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1109                                         <0 RK_PA6 RK_FUNC_2 &pcfg_pull_none>;
1110                         };
1111                         i2c3_gpio: i2c3-gpio {
1112                                 rockchip,pins =
1113                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1114                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1115                         };
1116                 };
1117
1118                 hdmi_i2c {
1119                         hdmii2c_xfer: hdmii2c-xfer {
1120                                 rockchip,pins =
1121                                         <0 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1122                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1123                         };
1124                 };
1125
1126                 tsadc {
1127                         otp_gpio: otp-gpio {
1128                                 rockchip,pins =
1129                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1130                         };
1131
1132                         otp_out: otp-out {
1133                                 rockchip,pins =
1134                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136                 };
1137
1138                 uart0 {
1139                         uart0_xfer: uart0-xfer {
1140                                 rockchip,pins =
1141                                         <1 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1142                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
1143                         };
1144
1145                         uart0_cts: uart0-cts {
1146                                 rockchip,pins =
1147                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1148                         };
1149
1150                         uart0_rts: uart0-rts {
1151                                 rockchip,pins =
1152                                         <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
1153                         };
1154
1155                         uart0_rts_gpio: uart0-rts-gpio {
1156                                 rockchip,pins =
1157                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1158                         };
1159                 };
1160
1161                 uart1 {
1162                         uart1_xfer: uart1-xfer {
1163                                 rockchip,pins =
1164                                         <3 RK_PA4 RK_FUNC_4 &pcfg_pull_up>,
1165                                         <3 RK_PA6 RK_FUNC_4 &pcfg_pull_none>;
1166                         };
1167
1168                         uart1_cts: uart1-cts {
1169                                 rockchip,pins =
1170                                         <3 RK_PA7 RK_FUNC_4 &pcfg_pull_none>;
1171                         };
1172
1173                         uart1_rts: uart1-rts {
1174                                 rockchip,pins =
1175                                         <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>;
1176                         };
1177
1178                         uart1_rts_gpio: uart1-rts-gpio {
1179                                 rockchip,pins =
1180                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1181                         };
1182                 };
1183
1184                 uart2-0 {
1185                         uart2m0_xfer: uart2m0-xfer {
1186                                 rockchip,pins =
1187                                         <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up>,
1188                                         <1 RK_PA1 RK_FUNC_2 &pcfg_pull_none>;
1189                         };
1190                 };
1191
1192                 uart2-1 {
1193                         uart2m1_xfer: uart2m1-xfer {
1194                                 rockchip,pins =
1195                                         <2 RK_PA0 RK_FUNC_1 &pcfg_pull_up>,
1196                                         <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1197                         };
1198                 };
1199
1200                 spi0-0 {
1201                         spi0m0_clk: spi0m0-clk {
1202                                 rockchip,pins =
1203                                         <2 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1204                         };
1205
1206                         spi0m0_cs0: spi0m0-cs0 {
1207                                 rockchip,pins =
1208                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1209                         };
1210
1211                         spi0m0_tx: spi0m0-tx {
1212                                 rockchip,pins =
1213                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
1214                         };
1215
1216                         spi0m0_rx: spi0m0-rx {
1217                                 rockchip,pins =
1218                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
1219                         };
1220
1221                         spi0m0_cs1: spi0m0-cs1 {
1222                                 rockchip,pins =
1223                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
1224                         };
1225                 };
1226
1227                 spi0-1 {
1228                         spi0m1_clk: spi0m1-clk {
1229                                 rockchip,pins =
1230                                         <3 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
1231                         };
1232
1233                         spi0m1_cs0: spi0m1-cs0 {
1234                                 rockchip,pins =
1235                                         <3 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
1236                         };
1237
1238                         spi0m1_tx: spi0m1-tx {
1239                                 rockchip,pins =
1240                                         <3 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
1241                         };
1242
1243                         spi0m1_rx: spi0m1-rx {
1244                                 rockchip,pins =
1245                                         <3 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
1246                         };
1247
1248                         spi0m1_cs1: spi0m1-cs1 {
1249                                 rockchip,pins =
1250                                         <3 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
1251                         };
1252                 };
1253
1254                 spi0-2 {
1255                         spi0m2_clk: spi0m2-clk {
1256                                 rockchip,pins =
1257                                         <3 RK_PA0 RK_FUNC_4 &pcfg_pull_up>;
1258                         };
1259
1260                         spi0m2_cs0: spi0m2-cs0 {
1261                                 rockchip,pins =
1262                                         <3 RK_PB0 RK_FUNC_3 &pcfg_pull_up>;
1263                         };
1264
1265                         spi0m2_tx: spi0m2-tx {
1266                                 rockchip,pins =
1267                                         <3 RK_PA1 RK_FUNC_4 &pcfg_pull_up>;
1268                         };
1269
1270                         spi0m2_rx: spi0m2-rx {
1271                                 rockchip,pins =
1272                                         <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>;
1273                         };
1274                 };
1275
1276                 pdm-0 {
1277                         pdmm0_clk: pdmm0-clk {
1278                                 rockchip,pins =
1279                                         <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
1280                         };
1281
1282                         pdmm0_fsync: pdmm0-fsync {
1283                                 rockchip,pins =
1284                                         <2 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1285                         };
1286
1287                         pdmm0_sdi0: pdmm0-sdi0 {
1288                                 rockchip,pins =
1289                                         <2 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
1290                         };
1291
1292                         pdmm0_sdi1: pdmm0-sdi1 {
1293                                 rockchip,pins =
1294                                         <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1295                         };
1296
1297                         pdmm0_sdi2: pdmm0-sdi2 {
1298                                 rockchip,pins =
1299                                         <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
1300                         };
1301
1302                         pdmm0_sdi3: pdmm0-sdi3 {
1303                                 rockchip,pins =
1304                                         <2 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1305                         };
1306
1307                         pdmm0_sleep: pdmm0-sleep {
1308                                 rockchip,pins =
1309                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1310                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1311                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1312                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1313                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1314                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1315                         };
1316                 };
1317
1318                 i2s1 {
1319                         i2s1_mclk: i2s1-mclk {
1320                                 rockchip,pins =
1321                                         <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323
1324                         i2s1_sclk: i2s1-sclk {
1325                                 rockchip,pins =
1326                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
1327                         };
1328
1329                         i2s1_lrckrx: i2s1-lrckrx {
1330                                 rockchip,pins =
1331                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1332                         };
1333
1334                         i2s1_lrcktx: i2s1-lrcktx {
1335                                 rockchip,pins =
1336                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338
1339                         i2s1_sdi: i2s1-sdi {
1340                                 rockchip,pins =
1341                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
1342                         };
1343
1344                         i2s1_sdo: i2s1-sdo {
1345                                 rockchip,pins =
1346                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1347                         };
1348
1349                         i2s1_sdio1: i2s1-sdio1 {
1350                                 rockchip,pins =
1351                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1352                         };
1353
1354                         i2s1_sdio2: i2s1-sdio2 {
1355                                 rockchip,pins =
1356                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1357                         };
1358
1359                         i2s1_sdio3: i2s1-sdio3 {
1360                                 rockchip,pins =
1361                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1362                         };
1363
1364                         i2s1_sleep: i2s1-sleep {
1365                                 rockchip,pins =
1366                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1367                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1368                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1369                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1370                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1371                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1372                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1373                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1374                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1375                         };
1376                 };
1377
1378                 i2s2-0 {
1379                         i2s2m0_mclk: i2s2m0-mclk {
1380                                 rockchip,pins =
1381                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1382                         };
1383
1384                         i2s2m0_sclk: i2s2m0-sclk {
1385                                 rockchip,pins =
1386                                         <1 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1387                         };
1388
1389                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1390                                 rockchip,pins =
1391                                         <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
1392                         };
1393
1394                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1395                                 rockchip,pins =
1396                                         <1 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398
1399                         i2s2m0_sdi: i2s2m0-sdi {
1400                                 rockchip,pins =
1401                                         <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
1402                         };
1403
1404                         i2s2m0_sdo: i2s2m0-sdo {
1405                                 rockchip,pins =
1406                                         <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1407                         };
1408
1409                         i2s2m0_sleep: i2s2m0-sleep {
1410                                 rockchip,pins =
1411                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1412                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1413                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1414                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1415                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1416                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1417                         };
1418                 };
1419
1420                 i2s2-1 {
1421                         i2s2m1_mclk: i2s2m1-mclk {
1422                                 rockchip,pins =
1423                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1424                         };
1425
1426                         i2s2m1_sclk: i2s2m1-sclk {
1427                                 rockchip,pins =
1428                                         <3 RK_PA0 RK_FUNC_6 &pcfg_pull_none>;
1429                         };
1430
1431                         i2s2m1_lrckrx: i2sm1-lrckrx {
1432                                 rockchip,pins =
1433                                         <3 RK_PB0 RK_FUNC_6 &pcfg_pull_none>;
1434                         };
1435
1436                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1437                                 rockchip,pins =
1438                                         <3 RK_PB0 RK_FUNC_4 &pcfg_pull_none>;
1439                         };
1440
1441                         i2s2m1_sdi: i2s2m1-sdi {
1442                                 rockchip,pins =
1443                                         <3 RK_PA2 RK_FUNC_6 &pcfg_pull_none>;
1444                         };
1445
1446                         i2s2m1_sdo: i2s2m1-sdo {
1447                                 rockchip,pins =
1448                                         <3 RK_PA1 RK_FUNC_6 &pcfg_pull_none>;
1449                         };
1450
1451                         i2s2m1_sleep: i2s2m1-sleep {
1452                                 rockchip,pins =
1453                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1454                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1455                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1456                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1457                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1458                         };
1459                 };
1460
1461                 spdif-0 {
1462                         spdifm0_tx: spdifm0-tx {
1463                                 rockchip,pins =
1464                                         <0 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
1465                         };
1466                 };
1467
1468                 spdif-1 {
1469                         spdifm1_tx: spdifm1-tx {
1470                                 rockchip,pins =
1471                                         <2 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 spdif-2 {
1476                         spdifm2_tx: spdifm2-tx {
1477                                 rockchip,pins =
1478                                         <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1479                         };
1480                 };
1481
1482                 sdmmc0-0 {
1483                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1484                                 rockchip,pins =
1485                                         <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1486                         };
1487
1488                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1489                                 rockchip,pins =
1490                                         <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1491                         };
1492                 };
1493
1494                 sdmmc0-1 {
1495                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1496                                 rockchip,pins =
1497                                         <0 RK_PD6 RK_FUNC_3 &pcfg_pull_up_4ma>;
1498                         };
1499
1500                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1501                                 rockchip,pins =
1502                                         <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1503                         };
1504                 };
1505
1506                 sdmmc0 {
1507                         sdmmc0_clk: sdmmc0-clk {
1508                                 rockchip,pins =
1509                                         <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1510                         };
1511
1512                         sdmmc0_cmd: sdmmc0-cmd {
1513                                 rockchip,pins =
1514                                         <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1515                         };
1516
1517                         sdmmc0_dectn: sdmmc0-dectn {
1518                                 rockchip,pins =
1519                                         <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1520                         };
1521
1522                         sdmmc0_wrprt: sdmmc0-wrprt {
1523                                 rockchip,pins =
1524                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1525                         };
1526
1527                         sdmmc0_bus1: sdmmc0-bus1 {
1528                                 rockchip,pins =
1529                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1530                         };
1531
1532                         sdmmc0_bus4: sdmmc0-bus4 {
1533                                 rockchip,pins =
1534                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1535                                         <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1536                                         <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1537                                         <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1538                         };
1539
1540                         sdmmc0_gpio: sdmmc0-gpio {
1541                                 rockchip,pins =
1542                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1543                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1544                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1545                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1546                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1547                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1548                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1549                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1550                         };
1551                 };
1552
1553                 sdmmc0ext {
1554                         sdmmc0ext_clk: sdmmc0ext-clk {
1555                                 rockchip,pins =
1556                                         <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1557                         };
1558
1559                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1560                                 rockchip,pins =
1561                                         <3 RK_PA0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1562                         };
1563
1564                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1565                                 rockchip,pins =
1566                                         <3 RK_PA3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1567                         };
1568
1569                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1570                                 rockchip,pins =
1571                                         <3 RK_PA1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1572                         };
1573
1574                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1575                                 rockchip,pins =
1576                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1577                         };
1578
1579                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1580                                 rockchip,pins =
1581                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1582                                         <3 RK_PA5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1583                                         <3 RK_PA6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1584                                         <3 RK_PA7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1585                         };
1586
1587                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1588                                 rockchip,pins =
1589                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1590                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1591                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1592                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1593                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1594                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1595                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1596                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1597                         };
1598                 };
1599
1600                 sdmmc1 {
1601                         sdmmc1_clk: sdmmc1-clk {
1602                                 rockchip,pins =
1603                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>;
1604                         };
1605
1606                         sdmmc1_cmd: sdmmc1-cmd {
1607                                 rockchip,pins =
1608                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>;
1609                         };
1610
1611                         sdmmc1_pwren: sdmmc1-pwren {
1612                                 rockchip,pins =
1613                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up_8ma>;
1614                         };
1615
1616                         sdmmc1_wrprt: sdmmc1-wrprt {
1617                                 rockchip,pins =
1618                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>;
1619                         };
1620
1621                         sdmmc1_dectn: sdmmc1-dectn {
1622                                 rockchip,pins =
1623                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_up_8ma>;
1624                         };
1625
1626                         sdmmc1_bus1: sdmmc1-bus1 {
1627                                 rockchip,pins =
1628                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>;
1629                         };
1630
1631                         sdmmc1_bus4: sdmmc1-bus4 {
1632                                 rockchip,pins =
1633                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>,
1634                                         <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up_8ma>,
1635                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
1636                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
1637                         };
1638
1639                         sdmmc1_gpio: sdmmc1-gpio {
1640                                 rockchip,pins =
1641                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1642                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1643                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1644                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1645                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1646                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1647                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1648                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1649                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1650                         };
1651                 };
1652
1653                 emmc {
1654                         emmc_clk: emmc-clk {
1655                                 rockchip,pins =
1656                                         <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none_12ma>;
1657                         };
1658
1659                         emmc_cmd: emmc-cmd {
1660                                 rockchip,pins =
1661                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up_12ma>;
1662                         };
1663
1664                         emmc_pwren: emmc-pwren {
1665                                 rockchip,pins =
1666                                         <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1667                         };
1668
1669                         emmc_rstnout: emmc-rstnout {
1670                                 rockchip,pins =
1671                                         <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1672                         };
1673
1674                         emmc_bus1: emmc-bus1 {
1675                                 rockchip,pins =
1676                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1677                         };
1678
1679                         emmc_bus4: emmc-bus4 {
1680                                 rockchip,pins =
1681                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1682                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1683                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1684                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>;
1685                         };
1686
1687                         emmc_bus8: emmc-bus8 {
1688                                 rockchip,pins =
1689                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1690                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1691                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1692                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>,
1693                                         <2 RK_PD7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1694                                         <3 RK_PC0 RK_FUNC_2 &pcfg_pull_up_12ma>,
1695                                         <3 RK_PC1 RK_FUNC_2 &pcfg_pull_up_12ma>,
1696                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_up_12ma>;
1697                         };
1698                 };
1699
1700                 pwm0 {
1701                         pwm0_pin: pwm0-pin {
1702                                 rockchip,pins =
1703                                         <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
1704                         };
1705                 };
1706
1707                 pwm1 {
1708                         pwm1_pin: pwm1-pin {
1709                                 rockchip,pins =
1710                                         <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1711                         };
1712                 };
1713
1714                 pwm2 {
1715                         pwm2_pin: pwm2-pin {
1716                                 rockchip,pins =
1717                                         <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1718                         };
1719                 };
1720
1721                 pwmir {
1722                         pwmir_pin: pwmir-pin {
1723                                 rockchip,pins =
1724                                         <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>;
1725                         };
1726                 };
1727
1728                 gmac-1 {
1729                         rgmiim1_pins: rgmiim1-pins {
1730                                 rockchip,pins =
1731                                         /* mac_txclk */
1732                                         <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none_12ma>,
1733                                         /* mac_rxclk */
1734                                         <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1735                                         /* mac_mdio */
1736                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1737                                         /* mac_txen */
1738                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1739                                         /* mac_clk */
1740                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1741                                         /* mac_rxdv */
1742                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1743                                         /* mac_mdc */
1744                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1745                                         /* mac_rxd1 */
1746                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1747                                         /* mac_rxd0 */
1748                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1749                                         /* mac_txd1 */
1750                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1751                                         /* mac_txd0 */
1752                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1753                                         /* mac_rxd3 */
1754                                         <1 RK_PB6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1755                                         /* mac_rxd2 */
1756                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1757                                         /* mac_txd3 */
1758                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1759                                         /* mac_txd2 */
1760                                         <1 RK_PC1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1761
1762                                         /* mac_txclk */
1763                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1764                                         /* mac_txen */
1765                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1766                                         /* mac_clk */
1767                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1768                                         /* mac_txd1 */
1769                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1770                                         /* mac_txd0 */
1771                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1772                                         /* mac_txd3 */
1773                                         <0 RK_PC7 RK_FUNC_1 &pcfg_pull_none>,
1774                                         /* mac_txd2 */
1775                                         <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1776                         };
1777
1778                         rmiim1_pins: rmiim1-pins {
1779                                 rockchip,pins =
1780                                         /* mac_mdio */
1781                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1782                                         /* mac_txen */
1783                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1784                                         /* mac_clk */
1785                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1786                                         /* mac_rxer */
1787                                         <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none_2ma>,
1788                                         /* mac_rxdv */
1789                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1790                                         /* mac_mdc */
1791                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1792                                         /* mac_rxd1 */
1793                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1794                                         /* mac_rxd0 */
1795                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1796                                         /* mac_txd1 */
1797                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1798                                         /* mac_txd0 */
1799                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1800
1801                                         /* mac_mdio */
1802                                         <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1803                                         /* mac_txen */
1804                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1805                                         /* mac_clk */
1806                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1807                                         /* mac_mdc */
1808                                         <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
1809                                         /* mac_txd1 */
1810                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1811                                         /* mac_txd0 */
1812                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1813                         };
1814                 };
1815
1816                 gmac2phy {
1817                         fephyled_speed100: fephyled-speed100 {
1818                                 rockchip,pins =
1819                                         <0 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
1820                         };
1821
1822                         fephyled_speed10: fephyled-speed10 {
1823                                 rockchip,pins =
1824                                         <0 RK_PD6 RK_FUNC_1 &pcfg_pull_none>;
1825                         };
1826
1827                         fephyled_duplex: fephyled-duplex {
1828                                 rockchip,pins =
1829                                         <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
1830                         };
1831
1832                         fephyled_rxm0: fephyled-rxm0 {
1833                                 rockchip,pins =
1834                                         <0 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
1835                         };
1836
1837                         fephyled_txm0: fephyled-txm0 {
1838                                 rockchip,pins =
1839                                         <0 RK_PD5 RK_FUNC_2 &pcfg_pull_none>;
1840                         };
1841
1842                         fephyled_linkm0: fephyled-linkm0 {
1843                                 rockchip,pins =
1844                                         <0 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
1845                         };
1846
1847                         fephyled_rxm1: fephyled-rxm1 {
1848                                 rockchip,pins =
1849                                         <2 RK_PD1 RK_FUNC_2 &pcfg_pull_none>;
1850                         };
1851
1852                         fephyled_txm1: fephyled-txm1 {
1853                                 rockchip,pins =
1854                                         <2 RK_PD1 RK_FUNC_3 &pcfg_pull_none>;
1855                         };
1856
1857                         fephyled_linkm1: fephyled-linkm1 {
1858                                 rockchip,pins =
1859                                         <2 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
1860                         };
1861                 };
1862
1863                 tsadc_pin {
1864                         tsadc_int: tsadc-int {
1865                                 rockchip,pins =
1866                                         <2 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
1867                         };
1868                         tsadc_gpio: tsadc-gpio {
1869                                 rockchip,pins =
1870                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1871                         };
1872                 };
1873
1874                 hdmi_pin {
1875                         hdmi_cec: hdmi-cec {
1876                                 rockchip,pins =
1877                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
1878                         };
1879
1880                         hdmi_hpd: hdmi-hpd {
1881                                 rockchip,pins =
1882                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_down>;
1883                         };
1884                 };
1885
1886                 cif-0 {
1887                         dvp_d2d9_m0:dvp-d2d9-m0 {
1888                                 rockchip,pins =
1889                                         /* cif_d0 */
1890                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1891                                         /* cif_d1 */
1892                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1893                                         /* cif_d2 */
1894                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1895                                         /* cif_d3 */
1896                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1897                                         /* cif_d4 */
1898                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1899                                         /* cif_d5m0 */
1900                                         <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>,
1901                                         /* cif_d6m0 */
1902                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1903                                         /* cif_d7m0 */
1904                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1905                                         /* cif_href */
1906                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1907                                         /* cif_vsync */
1908                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1909                                         /* cif_clkoutm0 */
1910                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>,
1911                                         /* cif_clkin */
1912                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1913                         };
1914                 };
1915
1916                 cif-1 {
1917                         dvp_d2d9_m1:dvp-d2d9-m1 {
1918                                 rockchip,pins =
1919                                         /* cif_d0 */
1920                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1921                                         /* cif_d1 */
1922                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1923                                         /* cif_d2 */
1924                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1925                                         /* cif_d3 */
1926                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1927                                         /* cif_d4 */
1928                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1929                                         /* cif_d5m1 */
1930                                         <2 RK_PC0 RK_FUNC_4 &pcfg_pull_none>,
1931                                         /* cif_d6m1 */
1932                                         <2 RK_PC1 RK_FUNC_4 &pcfg_pull_none>,
1933                                         /* cif_d7m1 */
1934                                         <2 RK_PC2 RK_FUNC_4 &pcfg_pull_none>,
1935                                         /* cif_href */
1936                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1937                                         /* cif_vsync */
1938                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1939                                         /* cif_clkoutm1 */
1940                                         <2 RK_PB7 RK_FUNC_4 &pcfg_pull_none>,
1941                                         /* cif_clkin */
1942                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1943                         };
1944                 };
1945         };
1946 };