arch/arm/mach-rockchip/rk3288.c

   1 /*
   2  * Device Tree support for Rockchip RK3288
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/rockchip/common.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/cru.h>
  29 #include <linux/rockchip/dvfs.h>
  30 #include <linux/rockchip/grf.h>
  31 #include <linux/rockchip/iomap.h>
  32 #include <linux/rockchip/pmu.h>
  33 #include <linux/fb.h>
  34 #include <asm/cpuidle.h>
  35 #include <asm/cputype.h>
  36 #include <asm/mach/arch.h>
  37 #include <asm/mach/map.h>
  38 #include "cpu_axi.h"
  39 #include "loader.h"
  40 #define CPU 3288
  41 #include "sram.h"
  42 #include "pm.h"
  43
  44 #define RK3288_DEVICE(name) \
  45         { \
  46                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  47                 .pfn            = __phys_to_pfn(RK3288_##name##_PHYS), \
  48                 .length         = RK3288_##name##_SIZE, \
  49                 .type           = MT_DEVICE, \
  50         }
  51
  52 #define RK3288_SERVICE_DEVICE(name) \
  53         RK_DEVICE(RK3288_SERVICE_##name##_VIRT, RK3288_SERVICE_##name##_PHYS, RK3288_SERVICE_##name##_SIZE)
  54
  55 #define RK3288_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  56 #define RK3288_TIMER7_VIRT (RK_TIMER_VIRT + 0x20)
  57
  58 static struct map_desc rk3288_io_desc[] __initdata = {
  59         RK3288_DEVICE(CRU),
  60         RK3288_DEVICE(GRF),
  61         RK3288_DEVICE(SGRF),
  62         RK3288_DEVICE(PMU),
  63         RK3288_DEVICE(ROM),
  64         RK3288_DEVICE(EFUSE),
  65         RK3288_SERVICE_DEVICE(CORE),
  66         RK3288_SERVICE_DEVICE(DMAC),
  67         RK3288_SERVICE_DEVICE(GPU),
  68         RK3288_SERVICE_DEVICE(PERI),
  69         RK3288_SERVICE_DEVICE(VIO),
  70         RK3288_SERVICE_DEVICE(VIDEO),
  71         RK3288_SERVICE_DEVICE(HEVC),
  72         RK3288_SERVICE_DEVICE(BUS),
  73         RK_DEVICE(RK_DDR_VIRT, RK3288_DDR_PCTL0_PHYS, RK3288_DDR_PCTL_SIZE),
  74         RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE, RK3288_DDR_PUBL0_PHYS, RK3288_DDR_PUBL_SIZE),
  75         RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PCTL1_PHYS, RK3288_DDR_PCTL_SIZE),
  76         RK_DEVICE(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PUBL1_PHYS, RK3288_DDR_PUBL_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(0), RK3288_GPIO0_PHYS, RK3288_GPIO_SIZE),
  78         RK_DEVICE(RK_GPIO_VIRT(1), RK3288_GPIO1_PHYS, RK3288_GPIO_SIZE),
  79         RK_DEVICE(RK_GPIO_VIRT(2), RK3288_GPIO2_PHYS, RK3288_GPIO_SIZE),
  80         RK_DEVICE(RK_GPIO_VIRT(3), RK3288_GPIO3_PHYS, RK3288_GPIO_SIZE),
  81         RK_DEVICE(RK_GPIO_VIRT(4), RK3288_GPIO4_PHYS, RK3288_GPIO_SIZE),
  82         RK_DEVICE(RK_GPIO_VIRT(5), RK3288_GPIO5_PHYS, RK3288_GPIO_SIZE),
  83         RK_DEVICE(RK_GPIO_VIRT(6), RK3288_GPIO6_PHYS, RK3288_GPIO_SIZE),
  84         RK_DEVICE(RK_GPIO_VIRT(7), RK3288_GPIO7_PHYS, RK3288_GPIO_SIZE),
  85         RK_DEVICE(RK_GPIO_VIRT(8), RK3288_GPIO8_PHYS, RK3288_GPIO_SIZE),
  86         RK_DEVICE(RK_DEBUG_UART_VIRT, RK3288_UART_DBG_PHYS, RK3288_UART_SIZE),
  87         RK_DEVICE(RK_GIC_VIRT, RK3288_GIC_DIST_PHYS, RK3288_GIC_DIST_SIZE),
  88         RK_DEVICE(RK_GIC_VIRT + RK3288_GIC_DIST_SIZE, RK3288_GIC_CPU_PHYS, RK3288_GIC_CPU_SIZE),
  89         RK_DEVICE(RK_BOOTRAM_VIRT, RK3288_BOOTRAM_PHYS, RK3288_BOOTRAM_SIZE),
  90         RK_DEVICE(RK3288_IMEM_VIRT, RK3288_IMEM_PHYS, SZ_4K),
  91         RK_DEVICE(RK_TIMER_VIRT, RK3288_TIMER6_PHYS, RK3288_TIMER_SIZE),
  92 };
  93
  94 static void __init rk3288_boot_mode_init(void)
  95 {
  96         u32 flag = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG0);
  97         u32 mode = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG1);
  98         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_ST);
  99
 100         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
 101                 mode = BOOT_MODE_RECOVERY;
 102         if (rst_st & ((1 << 4) | (1 << 5)))
 103                 mode = BOOT_MODE_WATCHDOG;
 104         else if (rst_st & ((1 << 2) | (1 << 3)))
 105                 mode = BOOT_MODE_TSADC;
 106         rockchip_boot_mode_init(flag, mode);
 107 }
 108
 109 static void usb_uart_init(void)
 110 {
 111         u32 soc_status2;
 112
 113         writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
 114         soc_status2 = (readl_relaxed(RK_GRF_VIRT + RK3288_GRF_SOC_STATUS2));
 115
 116 #ifdef CONFIG_RK_USB_UART
 117         if (!(soc_status2 & (1<<14)) && (soc_status2 & (1<<17))) {
 118                 /* software control usb phy enable */
 119                 writel_relaxed(0x00040004, RK_GRF_VIRT + RK3288_GRF_UOC0_CON2);
 120                 /* usb phy enter suspend */
 121                 writel_relaxed(0x003f002a, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
 122                 writel_relaxed(0x00c000c0, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
 123         }
 124 #endif
 125 }
 126
 127 extern void secondary_startup(void);
 128
 129 static void __init rk3288_dt_map_io(void)
 130 {
 131         u32 v;
 132
 133         rockchip_soc_id = ROCKCHIP_SOC_RK3288;
 134
 135         iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
 136         debug_ll_io_init();
 137         usb_uart_init();
 138
 139         /* pmu reset by second global soft reset */
 140         v = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
 141         v &= ~(3 << 2);
 142         v |= 1 << 2;
 143         writel_relaxed(v, RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
 144
 145         /* rkpwm is used instead of old pwm */
 146         writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
 147
 148         /* disable address remap */
 149         writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
 150
 151         /* enable timer7 for core */
 152         writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
 153         dsb();
 154         writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
 155         writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
 156         dsb();
 157         writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
 158         dsb();
 159
 160         /* power up/down GPU domain wait 1us */
 161         writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRDWN_CNT);
 162         writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRUP_CNT);
 163
 164         rk3288_boot_mode_init();
 165         rockchip_efuse_init();
 166 }
 167
 168 static const u8 pmu_st_map[] = {
 169         [PD_CPU_0] = 0,
 170         [PD_CPU_1] = 1,
 171         [PD_CPU_2] = 2,
 172         [PD_CPU_3] = 3,
 173         [PD_BUS] = 5,
 174         [PD_PERI] = 6,
 175         [PD_VIO] = 7,
 176         [PD_VIDEO] = 8,
 177         [PD_GPU] = 9,
 178         [PD_HEVC] = 10,
 179         [PD_SCU] = 11,
 180 };
 181
 182 static bool rk3288_pmu_power_domain_is_on(enum pmu_power_domain pd)
 183 {
 184         /* 1'b0: power on, 1'b1: power off */
 185         return !(readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 186 }
 187
 188 static DEFINE_SPINLOCK(pmu_idle_lock);
 189
 190 static const u8 pmu_idle_map[] = {
 191         [IDLE_REQ_BUS] = 0,
 192         [IDLE_REQ_PERI] = 1,
 193         [IDLE_REQ_GPU] = 2,
 194         [IDLE_REQ_VIDEO] = 3,
 195         [IDLE_REQ_VIO] = 4,
 196         [IDLE_REQ_CORE] = 5,
 197         [IDLE_REQ_ALIVE] = 6,
 198         [IDLE_REQ_DMA] = 7,
 199         [IDLE_REQ_CPUP] = 8,
 200         [IDLE_REQ_HEVC] = 9,
 201 };
 202
 203 static int rk3288_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 204 {
 205         u32 bit = pmu_idle_map[req];
 206         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 207         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 208         u32 mask = BIT(bit);
 209         u32 val;
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&pmu_idle_lock, flags);
 213         val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
 214         if (idle)
 215                 val |=  mask;
 216         else
 217                 val &= ~mask;
 218         writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
 219         dsb();
 220
 221         while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_ST) & idle_mask) != idle_target)
 222                 ;
 223         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 224
 225         return 0;
 226 }
 227
 228 static const u8 pmu_pd_map[] = {
 229         [PD_CPU_0] = 0,
 230         [PD_CPU_1] = 1,
 231         [PD_CPU_2] = 2,
 232         [PD_CPU_3] = 3,
 233         [PD_BUS] = 5,
 234         [PD_PERI] = 6,
 235         [PD_VIO] = 7,
 236         [PD_VIDEO] = 8,
 237         [PD_GPU] = 9,
 238         [PD_SCU] = 11,
 239         [PD_HEVC] = 14,
 240 };
 241
 242 static DEFINE_SPINLOCK(pmu_pd_lock);
 243
 244 static noinline void rk3288_do_pmu_set_power_domain(enum pmu_power_domain domain, bool on)
 245 {
 246         u8 pd = pmu_pd_map[domain];
 247         u32 val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
 248         if (on)
 249                 val &= ~BIT(pd);
 250         else
 251                 val |=  BIT(pd);
 252         writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
 253         dsb();
 254
 255         while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 256                 ;
 257 }
 258
 259 static u32 gpu_r_qos[CPU_AXI_QOS_NUM_REGS];
 260 static u32 gpu_w_qos[CPU_AXI_QOS_NUM_REGS];
 261 static u32 vio0_iep_qos[CPU_AXI_QOS_NUM_REGS];
 262 static u32 vio0_vip_qos[CPU_AXI_QOS_NUM_REGS];
 263 static u32 vio0_vop_qos[CPU_AXI_QOS_NUM_REGS];
 264 static u32 vio1_isp_r_qos[CPU_AXI_QOS_NUM_REGS];
 265 static u32 vio1_isp_w0_qos[CPU_AXI_QOS_NUM_REGS];
 266 static u32 vio1_isp_w1_qos[CPU_AXI_QOS_NUM_REGS];
 267 static u32 vio1_vop_qos[CPU_AXI_QOS_NUM_REGS];
 268 static u32 vio2_rga_r_qos[CPU_AXI_QOS_NUM_REGS];
 269 static u32 vio2_rga_w_qos[CPU_AXI_QOS_NUM_REGS];
 270 static u32 video_qos[CPU_AXI_QOS_NUM_REGS];
 271 static u32 hevc_r_qos[CPU_AXI_QOS_NUM_REGS];
 272 static u32 hevc_w_qos[CPU_AXI_QOS_NUM_REGS];
 273
 274 #define SAVE_QOS(array, NAME) CPU_AXI_SAVE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
 275 #define RESTORE_QOS(array, NAME) CPU_AXI_RESTORE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
 276
 277 static int rk3288_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 278 {
 279         unsigned long flags;
 280
 281         spin_lock_irqsave(&pmu_pd_lock, flags);
 282         if (rk3288_pmu_power_domain_is_on(pd) == on)
 283                 goto out;
 284
 285         if (!on) {
 286                 /* if power down, idle request to NIU first */
 287                 if (pd == PD_VIO) {
 288                         SAVE_QOS(vio0_iep_qos, VIO0_IEP);
 289                         SAVE_QOS(vio0_vip_qos, VIO0_VIP);
 290                         SAVE_QOS(vio0_vop_qos, VIO0_VOP);
 291                         SAVE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
 292                         SAVE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
 293                         SAVE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
 294                         SAVE_QOS(vio1_vop_qos, VIO1_VOP);
 295                         SAVE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
 296                         SAVE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
 297                         rk3288_pmu_set_idle_request(IDLE_REQ_VIO, true);
 298                 } else if (pd == PD_VIDEO) {
 299                         SAVE_QOS(video_qos, VIDEO);
 300                         rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 301                 } else if (pd == PD_GPU) {
 302                         SAVE_QOS(gpu_r_qos, GPU_R);
 303                         SAVE_QOS(gpu_w_qos, GPU_W);
 304                         rk3288_pmu_set_idle_request(IDLE_REQ_GPU, true);
 305                 } else if (pd == PD_HEVC) {
 306                         SAVE_QOS(hevc_r_qos, HEVC_R);
 307                         SAVE_QOS(hevc_w_qos, HEVC_W);
 308                         rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, true);
 309                 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 310                         writel_relaxed(0x20002 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
 311                         dsb();
 312                 }
 313                  else if (pd == PD_PERI) {
 314                         rk3288_pmu_set_idle_request(IDLE_REQ_PERI, true);
 315                 }
 316
 317         }
 318
 319         rk3288_do_pmu_set_power_domain(pd, on);
 320
 321         if (on) {
 322                 /* if power up, idle request release to NIU */
 323                 if (pd == PD_VIO) {
 324                         rk3288_pmu_set_idle_request(IDLE_REQ_VIO, false);
 325                         RESTORE_QOS(vio0_iep_qos, VIO0_IEP);
 326                         RESTORE_QOS(vio0_vip_qos, VIO0_VIP);
 327                         RESTORE_QOS(vio0_vop_qos, VIO0_VOP);
 328                         RESTORE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
 329                         RESTORE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
 330                         RESTORE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
 331                         RESTORE_QOS(vio1_vop_qos, VIO1_VOP);
 332                         RESTORE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
 333                         RESTORE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
 334                 } else if (pd == PD_VIDEO) {
 335                         rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 336                         RESTORE_QOS(video_qos, VIDEO);
 337                 } else if (pd == PD_GPU) {
 338                         rk3288_pmu_set_idle_request(IDLE_REQ_GPU, false);
 339                         RESTORE_QOS(gpu_r_qos, GPU_R);
 340                         RESTORE_QOS(gpu_w_qos, GPU_W);
 341                 } else if (pd == PD_HEVC) {
 342                         rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, false);
 343                         RESTORE_QOS(hevc_r_qos, HEVC_R);
 344                         RESTORE_QOS(hevc_w_qos, HEVC_W);
 345                 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 346 #ifdef CONFIG_SMP
 347                         writel_relaxed(0x20000 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
 348                         dsb();
 349                         udelay(10);
 350                         writel_relaxed(virt_to_phys(secondary_startup), RK3288_IMEM_VIRT + 8);
 351                         writel_relaxed(0xDEADBEAF, RK3288_IMEM_VIRT + 4);
 352                         dsb_sev();
 353 #endif
 354                 }
 355                 else if (pd == PD_PERI) {
 356                         rk3288_pmu_set_idle_request(IDLE_REQ_PERI, false);
 357                 }
 358         }
 359
 360 out:
 361         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 362         return 0;
 363 }
 364
 365 static int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 366 {
 367         u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT];
 368         u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT];
 369         u32 i, ret;
 370
 371         for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
 372                 clks_save[i] = cru_readl(RK3288_CRU_CLKGATES_CON(i));
 373                 clks_ungating[i] = 0;
 374         }
 375
 376         switch (pd) {
 377         case PD_GPU:
 378                 /* gpu */
 379                 clks_ungating[5] = 1 << 7;
 380                 /* aclk_gpu */
 381                 clks_ungating[18] = 1 << 0;
 382                 break;
 383         case PD_VIDEO:
 384                 /* aclk_vdpu_src hclk_vpu aclk_vepu_src */
 385                 clks_ungating[3] = 1 << 11 | 1 << 10 | 1 << 9;
 386                 /* hclk_video aclk_video */
 387                 clks_ungating[9] = 1 << 1 | 1 << 0;
 388                 break;
 389         case PD_VIO:
 390                 /* aclk_lcdc0/1_src dclk_lcdc0/1_src rga_core aclk_rga_src */
 391                 /* edp_24m edp isp isp_jpeg */
 392                 clks_ungating[3] =
 393                     1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 |
 394                     1 << 12 | 1 << 13 | 1 << 14 | 1 << 15;
 395                 clks_ungating[15] = 0xffff;
 396                 clks_ungating[16] = 0x0fff;
 397                 break;
 398         case PD_HEVC:
 399                 /* hevc_core hevc_cabac aclk_hevc */
 400                 clks_ungating[13] = 1 << 15 | 1 << 14 | 1 << 13;
 401                 break;
 402 #if 0
 403         case PD_CS:
 404                 clks_ungating[12] = 1 << 11 | 1 < 10 | 1 << 9 | 1 << 8;
 405                 break;
 406 #endif
 407         default:
 408                 break;
 409         }
 410
 411         for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
 412                 if (clks_ungating[i])
 413                         cru_writel(clks_ungating[i] << 16, RK3288_CRU_CLKGATES_CON(i));
 414         }
 415
 416         ret = rk3288_pmu_set_power_domain(pd, on);
 417
 418         for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
 419                 if (clks_ungating[i])
 420                         cru_writel(clks_save[i] | 0xffff0000, RK3288_CRU_CLKGATES_CON(i));
 421         }
 422
 423         return ret;
 424 }
 425
 426 static void __init rk3288_dt_init_timer(void)
 427 {
 428         rockchip_pmu_ops.set_power_domain = rk3288_sys_set_power_domain;
 429         rockchip_pmu_ops.power_domain_is_on = rk3288_pmu_power_domain_is_on;
 430         rockchip_pmu_ops.set_idle_request = rk3288_pmu_set_idle_request;
 431         of_clk_init(NULL);
 432         clocksource_of_init();
 433         of_dvfs_init();
 434 }
 435
 436 static void __init rk3288_reserve(void)
 437 {
 438         /* reserve memory for ION */
 439         rockchip_ion_reserve();
 440 }
 441
 442 static const char * const rk3288_dt_compat[] __initconst = {
 443         "rockchip,rk3288",
 444         NULL,
 445 };
 446
 447 static void rk3288_restart(char mode, const char *cmd)
 448 {
 449         u32 boot_flag, boot_mode;
 450
 451         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 452
 453         writel_relaxed(boot_flag, RK_PMU_VIRT + RK3288_PMU_SYS_REG0);   // for loader
 454         writel_relaxed(boot_mode, RK_PMU_VIRT + RK3288_PMU_SYS_REG1);   // for linux
 455         dsb();
 456
 457         /* pll enter slow mode */
 458         writel_relaxed(0xf3030000, RK_CRU_VIRT + RK3288_CRU_MODE_CON);
 459         dsb();
 460         writel_relaxed(0xeca8, RK_CRU_VIRT + RK3288_CRU_GLB_SRST_SND_VALUE);
 461         dsb();
 462 }
 463
 464 static struct cpuidle_driver rk3288_cpuidle_driver = {
 465         .name = "rk3288_cpuidle",
 466         .owner = THIS_MODULE,
 467         .states[0] = ARM_CPUIDLE_WFI_STATE,
 468         .state_count = 1,
 469 };
 470
 471 static int rk3288_cpuidle_enter(struct cpuidle_device *dev,
 472                 struct cpuidle_driver *drv, int index)
 473 {
 474         void *sel = RK_CRU_VIRT + RK3288_CRU_CLKSELS_CON(36);
 475         u32 con = readl_relaxed(sel);
 476         u32 cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0);
 477         writel_relaxed(0x70007 << (cpu << 2), sel);
 478         cpu_do_idle();
 479         writel_relaxed((0x70000 << (cpu << 2)) | con, sel);
 480         dsb();
 481         return index;
 482 }
 483
 484 static void __init rk3288_init_cpuidle(void)
 485 {
 486         int ret;
 487
 488         if (!rockchip_jtag_enabled)
 489                 rk3288_cpuidle_driver.states[0].enter = rk3288_cpuidle_enter;
 490         ret = cpuidle_register(&rk3288_cpuidle_driver, NULL);
 491         if (ret)
 492                 pr_err("%s: failed to register cpuidle driver: %d\n", __func__, ret);
 493 }
 494
 495 static int rk3288_pll_early_suspend_notifier_call(struct notifier_block *self,
 496                                 unsigned long action, void *data)
 497 {
 498         struct fb_event *event = data;
 499         int blank_mode = *((int *)event->data);
 500
 501         if (action == FB_EARLY_EVENT_BLANK) {
 502                 switch (blank_mode) {
 503                 case FB_BLANK_UNBLANK:
 504                         clk_prepare_enable(clk_get_sys(NULL, "clk_cpll"));
 505                         clk_prepare_enable(clk_get_sys(NULL, "clk_npll"));
 506                         break;
 507                 default:
 508                         break;
 509                 }
 510         } else if (action == FB_EVENT_BLANK) {
 511                 switch (blank_mode) {
 512                 case FB_BLANK_POWERDOWN:
 513                         clk_disable_unprepare(clk_get_sys(NULL, "clk_cpll"));
 514                         clk_disable_unprepare(clk_get_sys(NULL, "clk_npll"));
 515                         break;
 516                 default:
 517                         break;
 518                 }
 519         }
 520
 521         return NOTIFY_OK;
 522 }
 523
 524 static struct notifier_block rk3288_pll_early_suspend_notifier = {
 525         .notifier_call = rk3288_pll_early_suspend_notifier_call,
 526 };
 527
 528 #ifdef CONFIG_PM
 529 static void __init rk3288_init_suspend(void);
 530 #endif
 531 static void __init rk3288_init_late(void)
 532 {
 533 #ifdef CONFIG_PM
 534         rk3288_init_suspend();
 535 #endif
 536 #ifdef CONFIG_CPU_IDLE
 537         rk3288_init_cpuidle();
 538 #endif
 539         if (rockchip_jtag_enabled)
 540                 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
 541 }
 542
 543 DT_MACHINE_START(RK3288_DT, "Rockchip RK3288 (Flattened Device Tree)")
 544         .smp            = smp_ops(rockchip_smp_ops),
 545         .map_io         = rk3288_dt_map_io,
 546         .init_time      = rk3288_dt_init_timer,
 547         .dt_compat      = rk3288_dt_compat,
 548         .init_late      = rk3288_init_late,
 549         .reserve        = rk3288_reserve,
 550         .restart        = rk3288_restart,
 551 MACHINE_END
 552
 553 char PIE_DATA(sram_stack)[1024];
 554 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 555
 556 static int __init rk3288_pie_init(void)
 557 {
 558         int err;
 559         if (!cpu_is_rk3288())
 560                 return 0;
 561
 562         err = rockchip_pie_init();
 563         if (err)
 564                 return err;
 565
 566         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3288);
 567         if (IS_ERR(rockchip_pie_chunk)) {
 568                 err = PTR_ERR(rockchip_pie_chunk);
 569                 pr_err("%s: failed to load section %d\n", __func__, err);
 570                 rockchip_pie_chunk = NULL;
 571                 return err;
 572         }
 573
 574         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 575         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *) DATA(sram_stack) + sizeof(DATA(sram_stack)));
 576
 577     return 0;
 578 }
 579 arch_initcall(rk3288_pie_init);
 580 #ifdef CONFIG_PM
 581 #include "pm-rk3288.c"
 582
 583 static u32 rk_pmu_pwrdn_st;
 584 static inline void rk_pm_soc_pd_suspend(void)
 585 {
 586     rk_pmu_pwrdn_st = pmu_readl(RK3288_PMU_PWRDN_ST);
 587
 588     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
 589     rk3288_sys_set_power_domain(PD_GPU, false);
 590
 591     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
 592     rk3288_sys_set_power_domain(PD_HEVC, false);
 593
 594     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
 595     rk3288_sys_set_power_domain(PD_VIO, false);
 596
 597     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
 598     rk3288_sys_set_power_domain(PD_VIDEO, false);
 599 #if 0
 600     rkpm_ddr_printascii("pd state:");
 601     rkpm_ddr_printhex(rk_pmu_pwrdn_st);
 602     rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
 603     rkpm_ddr_printascii("\n");
 604  #endif
 605 }
 606 static inline void rk_pm_soc_pd_resume(void)
 607 {
 608     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
 609         rk3288_sys_set_power_domain(PD_GPU, true);
 610
 611     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
 612         rk3288_sys_set_power_domain(PD_HEVC, true);
 613
 614     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
 615      rk3288_sys_set_power_domain(PD_VIO, true);
 616
 617     if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
 618         rk3288_sys_set_power_domain(PD_VIDEO, true);
 619
 620 #if 0
 621     rkpm_ddr_printascii("pd state:");
 622     rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
 623     rkpm_ddr_printascii("\n");
 624 #endif
 625 }
 626 void inline rkpm_periph_pd_dn(bool on)
 627 {
 628     rk3288_sys_set_power_domain(PD_PERI, on);
 629 }
 630
 631 static void __init rk3288_init_suspend(void)
 632 {
 633     printk("%s\n",__FUNCTION__);
 634     fb_register_client(&rk3288_pll_early_suspend_notifier);
 635     rockchip_suspend_init();
 636     rkpm_pie_init();
 637     rk3288_suspend_init();
 638    rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend,rk_pm_soc_pd_resume);
 639 }
 640
 641 #if 0
 642 extern bool console_suspend_enabled;
 643
 644 static int  __init rk3288_pm_dbg(void)
 645 {
 646 #if 1
 647         console_suspend_enabled=0;
 648         do{
 649             pm_suspend(PM_SUSPEND_MEM);
 650         }
 651         while(1);
 652
 653 #endif
 654
 655 }
 656
 657 //late_initcall_sync(rk3288_pm_dbg);
 658 #endif
 659
 660
 661 #endif
 662 #define sram_printascii(s) do {} while (0) /* FIXME */
 663 #include "ddr_rk32.c"
 664
 665 static int __init rk3288_ddr_init(void)
 666 {
 667     if (cpu_is_rk3288())
 668     {
 669         ddr_change_freq = _ddr_change_freq;
 670         ddr_round_rate = _ddr_round_rate;
 671         ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 672         ddr_bandwidth_get = _ddr_bandwidth_get;
 673
 674         ddr_init(DDR3_DEFAULT, 0);
 675     }
 676
 677     return 0;
 678 }
 679 arch_initcall_sync(rk3288_ddr_init);
 680