arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/suspend/rockchip-pm.h>
   5 #include <dt-bindings/sensor-dev.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk3288-pinctrl.dtsi"
   9 #include "rk3288-clocks.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk3288";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial0 = &uart_bt;
  17                 serial1 = &uart_bb;
  18                 serial2 = &uart_dbg;
  19                 serial3 = &uart_gps;
  20                 serial4 = &uart_exp;
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 lcdc0 = &lcdc0;
  28                 lcdc1 = &lcdc1;
  29                 spi0 = &spi0;
  30                 spi1 = &spi1;
  31                 spi2 = &spi2;
  32
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <0x500>;
  43                 };
  44 /*
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60 */
  61         };
  62
  63         gic: interrupt-controller@ffc01000 {
  64                 compatible = "arm,cortex-a15-gic";
  65                 interrupt-controller;
  66                 #interrupt-cells = <3>;
  67                 #address-cells = <0>;
  68                 reg = <0xffc01000 0x1000>,
  69                       <0xffc02000 0x1000>;
  70         };
  71
  72         cpu_axi_bus: cpu_axi_bus {
  73                 compatible = "rockchip,cpu_axi_bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77                 qos {
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges;
  81                         /* service core */
  82                         cpup {
  83                                 reg = <0xffa80000 0x20>;
  84                         };
  85                         cpum_r {
  86                                 reg = <0xffa80080 0x20>;
  87                         };
  88                         cpum_w {
  89                                 reg = <0xffa80100 0x20>;
  90                         };
  91                         /* service dmac */
  92                         bus_dmac {
  93                                 reg = <0xffa90000 0x20>;
  94                         };
  95                         host {
  96                                 reg = <0xffa90080 0x20>;
  97                         };
  98                         crypto {
  99                                 reg = <0xffa90100 0x20>;
 100                         };
 101                         ccp {
 102                                 reg = <0xffa90180 0x20>;
 103                         };
 104                         ccs {
 105                                 reg = <0xffa90200 0x20>;
 106                         };
 107                         /* service gpu */
 108                         gpu_r {
 109                                 reg = <0xffaa0000 0x20>;
 110                         };
 111                         gpu_w {
 112                                 reg = <0xffaa0080 0x20>;
 113                         };
 114                         /* service peri */
 115                         peri {
 116                                 reg = <0xffab0000 0x20>;
 117                         };
 118                         /* service vio */
 119                         vio1_vop {
 120                                 reg = <0xffad0000 0x20>;
 121                         };
 122                         vio1_isp_w0 {
 123                                 reg = <0xffad0100 0x20>;
 124                         };
 125                         vio1_isp_w1 {
 126                                 reg = <0xffad0180 0x20>;
 127                         };
 128                         vio0_vop {
 129                                 reg = <0xffad0400 0x20>;
 130                         };
 131                         vio0_vip {
 132                                 reg = <0xffad0480 0x20>;
 133                         };
 134                         vio0_iep {
 135                                 reg = <0xffad0500 0x20>;
 136                         };
 137                         vio2_rga_r {
 138                                 reg = <0xffad0800 0x20>;
 139                         };
 140                         vio2_rga_w {
 141                                 reg = <0xffad0880 0x20>;
 142                         };
 143                         vio1_isp_r {
 144                                 reg = <0xffad0900 0x20>;
 145                         };
 146                         /* service video */
 147                         video {
 148                                 reg = <0xffae0000 0x20>;
 149                         };
 150                         /* service hevc */
 151                         hevc_r {
 152                                 reg = <0xffaf0000 0x20>;
 153                         };
 154                         hevc_w {
 155                                 reg = <0xffaf0080 0x20>;
 156                         };
 157                 };
 158                 msch {
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         ranges;
 162                         msch@0 {
 163                                 reg = <0xffac0000 0x40>;
 164                                 rockchip,read-latency = <0xff>;
 165                         };
 166                         msch@1 {
 167                                 reg = <0xffac0080 0x40>;
 168                                 rockchip,read-latency = <0xff>;
 169                         };
 170                 };
 171         };
 172
 173         sram: sram@ff710000 {
 174                 compatible = "mmio-sram";
 175                 reg = <0xff710000 0x8000>; /* 32k */
 176                 map-exec;
 177         };
 178
 179 /*
 180         timer {
 181                 compatible = "arm,armv7-timer";
 182                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 183                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 185                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 186                 clock-frequency = <24000000>;
 187         };
 188 */
 189
 190         timer@ff810000 {
 191                 compatible = "rockchip,timer";
 192                 reg = <0xff810000 0x20>;
 193                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 194                 rockchip,broadcast = <1>;
 195         };
 196
 197         timer@ff810020 {
 198                 compatible = "rockchip,timer";
 199                 reg = <0xff810020 0x20>;
 200                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,clocksource = <1>;
 202                 rockchip,count-up = <1>;
 203         };
 204
 205     amba {
 206                 #address-cells = <1>;
 207                 #size-cells = <1>;
 208                 compatible = "arm,amba-bus";
 209                 interrupt-parent = <&gic>;
 210                 ranges;
 211
 212                 pdma0: pdma@ffb20000 {
 213                         compatible = "arm,pl330", "arm,primecell";
 214                         reg = <0xffb20000 0x4000>;
 215                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 217                         #dma-cells = <1>;
 218                 };
 219
 220                 pdma1: pdma@ff250000 {
 221                         compatible = "arm,pl330", "arm,primecell";
 222                         reg = <0xff250000 0x4000>;
 223                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 225                         #dma-cells = <1>;
 226                 };
 227         };
 228
 229
 230         emmc: rksdmmc@ff0f0000 {
 231                 compatible = "rockchip,rk_mmc";
 232                 reg = <0xff0f0000 0x4000>;
 233                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 //pinctrl-names = "default",,"suspend";
 237                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 238
 239                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 240                 clock-names = "clk_mmc", "hclk_mmc";
 241                 num-slots = <1>;
 242                 fifo-depth = <0x80>;
 243                 bus-width = <4>;
 244         };
 245
 246         sdmmc: rksdmmc@ff0c0000 {
 247                 compatible = "rockchip,rk_mmc";
 248                 reg = <0xff0c0000 0x4000>;
 249                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 250                 #address-cells = <1>;
 251                 #size-cells = <0>;
 252
 253                 //pinctrl-names = "default","suspend";
 254                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 255                 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 256
 257                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 258                 clock-names = "clk_mmc", "hclk_mmc";
 259                 num-slots = <1>;
 260                 fifo-depth = <0x100>;
 261                 bus-width = <4>;
 262
 263         };
 264
 265         sdio: rksdmmc@ff0d0000 {
 266                 compatible = "rockchip,rk_mmc";
 267                 reg = <0xff0d0000 0x4000>;
 268                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 //pinctrl-names = "default","suspend";
 272                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 273
 274                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 275                 clock-names = "clk_mmc", "hclk_mmc";
 276                 num-slots = <1>;
 277
 278                 fifo-depth = <0x100>;
 279                 bus-width = <4>;
 280         };
 281
 282         sdio1: rksdmmc@ff0e0000 {
 283                 compatible = "rockchip,rk_mmc";
 284                 reg = <0xff0e0000 0x4000>;
 285                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 //pinctrl-names = "default","suspend";
 289                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 290
 291                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 292                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 293                 clock-names = "clk_mmc", "hclk_mmc";
 294                 num-slots = <1>;
 295
 296                 fifo-depth = <0x100>;
 297                 bus-width = <4>;
 298         };
 299
 300         spi0: spi@ff110000 {
 301                 compatible = "rockchip,rockchip-spi";
 302                 reg = <0xff110000 0x1000>;
 303                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 308                 rockchip,spi-src-clk = <0>;
 309                 num-cs = <2>;
 310                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 311                 clock-names = "spi","pclk_spi0";
 312                 //dmas = <&pdma1 11>, <&pdma1 12>;
 313                 //#dma-cells = <2>;
 314                 //dma-names = "tx", "rx";
 315                 status = "disabled";
 316         };
 317
 318         spi1: spi@ff120000 {
 319                 compatible = "rockchip,rockchip-spi";
 320                 reg = <0xff120000 0x1000>;
 321                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 326                 rockchip,spi-src-clk = <1>;
 327                 num-cs = <1>;
 328                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 329                 clock-names = "spi","pclk_spi1";
 330                 //dmas = <&pdma1 13>, <&pdma1 14>;
 331                 //#dma-cells = <2>;
 332                 //dma-names = "tx", "rx";
 333                 status = "disabled";
 334         };
 335
 336         spi2: spi@ff130000 {
 337                 compatible = "rockchip,rockchip-spi";
 338                 reg = <0xff130000 0x1000>;
 339                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 344                 rockchip,spi-src-clk = <2>;
 345                 num-cs = <2>;
 346                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 347                 clock-names = "spi","pclk_spi2";
 348                 //dmas = <&pdma1 15>, <&pdma1 16>;
 349                 //#dma-cells = <2>;
 350                 //dma-names = "tx", "rx";
 351                 status = "disabled";
 352         };
 353
 354         uart_bt: serial@ff180000 {
 355                 compatible = "rockchip,serial";
 356                 reg = <0xff180000 0x100>;
 357                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 358                 clock-frequency = <24000000>;
 359                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 360                 clock-names = "sclk_uart", "pclk_uart";
 361                 reg-shift = <2>;
 362                 reg-io-width = <4>;
 363                 dmas = <&pdma1 1>, <&pdma1 2>;
 364                 #dma-cells = <2>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 367                 status = "disabled";
 368         };
 369
 370         uart_bb: serial@ff190000 {
 371                 compatible = "rockchip,serial";
 372                 reg = <0xff190000 0x100>;
 373                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 374                 clock-frequency = <24000000>;
 375                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 376                 clock-names = "sclk_uart", "pclk_uart";
 377                 reg-shift = <2>;
 378                 reg-io-width = <4>;
 379                 dmas = <&pdma1 3>, <&pdma1 4>;
 380                 #dma-cells = <2>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 383                 status = "disabled";
 384         };
 385
 386         uart_dbg: serial@ff690000 {
 387                 compatible = "rockchip,serial";
 388                 reg = <0xff690000 0x100>;
 389                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 390                 clock-frequency = <24000000>;
 391                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 392                 clock-names = "sclk_uart", "pclk_uart";
 393                 reg-shift = <2>;
 394                 reg-io-width = <4>;
 395                 dmas = <&pdma0 4>, <&pdma0 5>;
 396                 #dma-cells = <2>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&uart2_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         uart_gps: serial@ff1b0000 {
 403                 compatible = "rockchip,serial";
 404                 reg = <0xff1b0000 0x100>;
 405                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 406                 clock-frequency = <24000000>;
 407                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 408                 clock-names = "sclk_uart", "pclk_uart";
 409                 current-speed = <115200>;
 410                 reg-shift = <2>;
 411                 reg-io-width = <4>;
 412                 dmas = <&pdma1 7>, <&pdma1 8>;
 413                 #dma-cells = <2>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 416                 status = "disabled";
 417         };
 418
 419         uart_exp: serial@ff1c0000 {
 420                 compatible = "rockchip,serial";
 421                 reg = <0xff1c0000 0x100>;
 422                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 423                 clock-frequency = <24000000>;
 424                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 425                 clock-names = "sclk_uart", "pclk_uart";
 426                 reg-shift = <2>;
 427                 reg-io-width = <4>;
 428                 dmas = <&pdma1 9>, <&pdma1 10>;
 429                 #dma-cells = <2>;
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 432                 status = "disabled";
 433         };
 434
 435         fiq-debugger {
 436                 compatible = "rockchip,fiq-debugger";
 437                 rockchip,serial-id = <2>;
 438                 rockchip,signal-irq = <106>;
 439                 rockchip,wake-irq = <0>;
 440                 status = "disabled";
 441         };
 442
 443         clocks-init{
 444                 compatible = "rockchip,clocks-init";
 445                 rockchip,clocks-init-parent =
 446                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 447                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 448                         <&clk_i2s_pll &clk_cpll>;
 449                 rockchip,clocks-init-rate =
 450                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 451                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 452                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 453                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 454                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 455                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 456                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 457                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 458                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 459                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 460                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 461                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 462                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 463                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 464                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 465                         <&clk_tspout 80000000>, <&clk_mac 50000000>;
 466         };
 467
 468         i2c0: i2c@ff650000 {
 469                 compatible = "rockchip,rk30-i2c";
 470                 reg = <0xff650000 0x1000>;
 471                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 pinctrl-names = "default", "gpio";
 475                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 476                 pinctrl-1 = <&i2c0_gpio>;
 477                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 478                 clocks = <&clk_gates10 2>;
 479                 rockchip,check-idle = <1>;
 480                 status = "disabled";
 481         };
 482
 483         i2c1: i2c@ff140000 {
 484                 compatible = "rockchip,rk30-i2c";
 485                 reg = <0xff140000 0x1000>;
 486                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 487                 #address-cells = <1>;
 488                 #size-cells = <0>;
 489                 pinctrl-names = "default", "gpio";
 490                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 491                 pinctrl-1 = <&i2c1_gpio>;
 492                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 493                 clocks = <&clk_gates10 3>;
 494                 rockchip,check-idle = <1>;
 495                 status = "disabled";
 496         };
 497
 498         i2c2: i2c@ff660000 {
 499                 compatible = "rockchip,rk30-i2c";
 500                 reg = <0xff660000 0x1000>;
 501                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 502                 #address-cells = <1>;
 503                 #size-cells = <0>;
 504                 pinctrl-names = "default", "gpio";
 505                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 506                 pinctrl-1 = <&i2c2_gpio>;
 507                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 508                 clocks = <&clk_gates6 13>;
 509                 rockchip,check-idle = <1>;
 510                 status = "disabled";
 511         };
 512
 513         i2c3: i2c@ff150000 {
 514                 compatible = "rockchip,rk30-i2c";
 515                 reg = <0xff150000 0x1000>;
 516                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519                 pinctrl-names = "default", "gpio";
 520                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 521                 pinctrl-1 = <&i2c3_gpio>;
 522                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 523                 clocks = <&clk_gates6 14>;
 524                 rockchip,check-idle = <1>;
 525                 status = "disabled";
 526         };
 527
 528         i2c4: i2c@ff160000 {
 529                 compatible = "rockchip,rk30-i2c";
 530                 reg = <0xff160000 0x1000>;
 531                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 pinctrl-names = "default", "gpio";
 535                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 536                 pinctrl-1 = <&i2c4_gpio>;
 537                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 538                 clocks = <&clk_gates6 15>;
 539                 rockchip,check-idle = <1>;
 540                 status = "disabled";
 541         };
 542
 543         i2c5: i2c@ff170000 {
 544                 compatible = "rockchip,rk30-i2c";
 545                 reg = <0xff170000 0x1000>;
 546                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 pinctrl-names = "default", "gpio";
 550                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 551                 pinctrl-1 = <&i2c5_gpio>;
 552                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 553                 clocks = <&clk_gates7 0>;
 554                 rockchip,check-idle = <1>;
 555                 status = "disabled";
 556         };
 557
 558
 559         fb: fb{
 560                 compatible = "rockchip,rk-fb";
 561                 rockchip,disp-mode = <DUAL>;
 562         };
 563
 564         rk_screen: rk_screen{
 565                         compatible = "rockchip,screen";
 566         };
 567
 568         lvds: lvds@ff96c000 {
 569                 compatible = "rockchip, rk32-lvds";
 570                 reg = <0xff96c000 0x4000>;
 571                 clocks = <&clk_gates16 7>;
 572                 clock-names = "pclk_lvds";
 573         };
 574
 575         edp: edp@ff970000 {
 576                 compatible = "rockchip, rk32-edp";
 577                 reg = <0xff970000 0x4000>;
 578                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 580                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 581         };
 582
 583         hdmi: hdmi@ff980000 {
 584                 compatible = "rockchip,rk3288-hdmi";
 585                 reg = <0xff980000 0x20000>;
 586                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 587                 pinctrl-names = "default", "gpio";
 588                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 589                 pinctrl-1 = <&i2c5_gpio>;
 590                 clocks = <&clk_gates16 9>;
 591                 clock-names = "pclk_hdmi";
 592                 status = "disabled";
 593         };
 594
 595         lcdc1: lcdc@ff940000 {
 596                 compatible = "rockchip,rk3288-lcdc";
 597                 rockchip,prop = <PRMRY>;
 598                 rochchip,pwr18 = <0>;
 599                 reg = <0xff940000 0x10000>;
 600                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 601                 pinctrl-names = "default", "gpio";
 602                 pinctrl-0 = <&lcdc0_lcdc>;
 603                 pinctrl-1 = <&lcdc0_gpio>;
 604                 status = "disabled";
 605                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>;
 606                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 607         };
 608
 609         lcdc0: lcdc@ff930000 {
 610                 compatible = "rockchip,rk3288-lcdc";
 611                 rockchip,prop = <EXTEND>;
 612                 rockchip,pwr18 = <0>;
 613                 reg = <0xff930000 0x10000>;
 614                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 615                 //pinctrl-names = "default", "gpio";
 616                 //pinctrl-0 = <&lcdc0_lcdc>;
 617                 //pinctrl-1 = <&lcdc0_gpio>;
 618                 status = "disabled";
 619                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>;
 620                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 621         };
 622
 623         adc: adc@ff100000 {
 624                 compatible = "rockchip,saradc";
 625                 reg = <0xff100000 0x100>;
 626                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 627                 #io-channel-cells = <1>;
 628                 io-channel-ranges;
 629                 rockchip,adc-vref = <1800>;
 630                 clock-frequency = <1000000>;
 631                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 632                 clock-names = "saradc", "pclk_saradc";
 633                 status = "disabled";
 634         };
 635
 636         rga@ff920000 {
 637                 compatible = "rockchip,rga";
 638                 reg = <0xff920000 0x1000>;
 639                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 640                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 641                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 642         };
 643
 644         i2s: rockchip-i2s@0xff890000 {
 645                 compatible = "rockchip-i2s";
 646                 reg = <0xff890000 0x10000>;
 647                 i2s-id = <0>;
 648                 clocks = <&clk_i2s>, <&clk_i2s_out>;
 649                 clock-names = "i2s_clk","i2s_mclk";
 650                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 651                 dmas = <&pdma0 0>,
 652                         <&pdma0 1>;
 653                 //#dma-cells = <2>;
 654                 dma-names = "tx", "rx";
 655                 pinctrl-names = "default", "sleep";
 656                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 657                 pinctrl-1 = <&i2s_gpio>;
 658         };
 659
 660         spdif: rockchip-spdif@0xff8b0000 {
 661                 compatible = "rockchip-spdif";
 662                 reg = <0xff8b0000 0x10000>;     //8channel
 663                 //reg = <ff880000 0x10000>;//2channel
 664                 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
 665                 clock-names = "spdif_mclk","spdif_8ch_mclk";
 666                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 667                 dmas = <&pdma0 3>;
 668                 //dmas = <&pdma0 2>; //2channel
 669                 //#dma-cells = <1>;
 670                 dma-names = "tx";
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&spdif_tx>;
 673         };
 674
 675         pwm0: pwm@ff680000 {
 676                 compatible = "rockchip,rk-pwm";
 677                 reg = <0xff680000 0x10>;
 678                 #pwm-cells = <2>;
 679                 pinctrl-names = "default";
 680                 pinctrl-0 = <&pwm0_pin>;
 681                 clocks = <&clk_gates11 11>;
 682                 clock-names = "pclk_pwm";
 683                 status = "okay";
 684         };
 685
 686         pwm1: pwm@ff680010 {
 687                 compatible = "rockchip,rk-pwm";
 688                 reg = <0xff680010 0x10>;
 689                 #pwm-cells = <2>;
 690                 pinctrl-names = "default";
 691                 pinctrl-0 = <&pwm1_pin>;
 692                 clocks = <&clk_gates11 11>;
 693                 clock-names = "pclk_pwm";
 694                 status = "disabled";
 695         };
 696
 697         pwm2: pwm@ff680020 {
 698                 compatible = "rockchip,rk-pwm";
 699                 reg = <0xff680020 0x10>;
 700                 #pwm-cells = <2>;
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&pwm2_pin>;
 703                 clocks = <&clk_gates11 11>;
 704                 clock-names = "pclk_pwm";
 705                 status = "disabled";
 706         };
 707
 708         pwm3: pwm@ff680030 {
 709                 compatible = "rockchip,rk-pwm";
 710                 reg = <0xff680030 0x10>;
 711                 #pwm-cells = <2>;
 712                 pinctrl-names = "default";
 713                 pinctrl-0 = <&pwm3_pin>;
 714                 clocks = <&clk_gates11 11>;
 715                 clock-names = "pclk_pwm";
 716                 status = "disabled";
 717         };
 718         dvfs {
 719                 vd_arm:
 720                 vd_arm {
 721                         regulator_name="vdd_arm";
 722                         suspend_volt=<1000>; //mV
 723                         pd_a12 {
 724                                 clk_core_dvfs_table:
 725                                 clk_core {
 726                                         operating-points = <
 727                                                 /* KHz    uV */
 728                                                 312000 1100000
 729                                                 504000 1100000
 730                                                 816000 1100000
 731                                                 1008000 1100000
 732                                                 >;
 733                                         status = "okay";
 734                                 };
 735                         };
 736                 };
 737
 738                 vd_logic:
 739                 vd_logic {
 740                         regulator_name="vdd_logic";
 741                         suspend_volt=<1000>; //mV
 742                         pd_ddr {
 743                                 clk_ddr_dvfs_table:
 744                                 clk_ddr {
 745                                         operating-points = <
 746                                                 /* KHz    uV */
 747                                                 200000 1200000
 748                                                 300000 1200000
 749                                                 400000 1200000
 750                                                 >;
 751                                         status = "disable";
 752                                 };
 753                         };
 754
 755                         pd_vpu {
 756                                 clk_ddr_vepu_table:
 757                                 clk_vepu {
 758                                         operating-points = <
 759                                                 /* KHz    uV */
 760                                                 200000 1200000
 761                                                 300000 1200000
 762                                                 400000 1200000
 763                                                 >;
 764                                         status = "okay";
 765                                 };
 766                         };
 767                 };
 768
 769                 vd_gpu:
 770                 vd_gpu {
 771                         regulator_name="vdd_gpu";
 772                         suspend_volt=<1000>; //mV
 773                         pd_gpu {
 774                                 clk_gpu_dvfs_table:
 775                                 clk_gpu {
 776                                         operating-points = <
 777                                                 /* KHz    uV */
 778                                                 200000 1200000
 779                                                 300000 1200000
 780                                                 400000 1200000
 781                                                 >;
 782                                         status = "okay";
 783                                 };
 784                         };
 785                 };
 786         };
 787
 788         ion {
 789                 compatible = "rockchip,ion";
 790                 #address-cells = <1>;
 791                 #size-cells = <0>;
 792                 rockchip,ion-heap@1 { /* CMA HEAP */
 793                         compatible = "rockchip,ion-reserve";
 794                         reg = <1>;
 795                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 796                 };
 797                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 798                         reg = <3>;
 799                 };
 800         };
 801
 802
 803         vpu: vpu_service@ff9a0000 {
 804                 compatible = "vpu_service";
 805                 reg = <0xff9a0000 0x800>;
 806                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 807                 interrupt-names = "irq_enc", "irq_dec";
 808                 clocks = <&clk_vepu>, <&hclk_vepu>;
 809                 clock-names = "aclk_vcodec", "hclk_vcodec";
 810                 name = "vpu_service";
 811                 //status = "disabled";
 812         };
 813
 814         hevc: hevc_service@ff9c0000 {
 815                 compatible = "rockchip,hevc_service";
 816                 reg = <0xff9c0000 0x800>;
 817                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 818                 interrupt-names = "irq_dec";
 819                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 820                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 821                 name = "hevc_service";
 822                 //status = "disabled";
 823         };
 824
 825         iep: iep@ff900000 {
 826                 compatible = "rockchip,iep";
 827                 reg = <0xff900000 0x800>;
 828                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 829                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 830                 clock_names = "aclk_iep", "hclk_iep";
 831                 status = "disabled";
 832         };
 833
 834         dwc_control_usb: dwc-control-usb@ff770284 {
 835                 compatible = "rockchip,rk3288-dwc-control-usb";
 836                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 837                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 838                       <0xff770320 0x14>, <0xff770334 0x14>,
 839                       <0xff770348 0x10>, <0xff770358 0x08>,
 840                       <0xff770360 0x08>;
 841                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 842                     "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 843                     "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 844                     "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 845                     "GRF_UOC4_BASE";
 846                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 847                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 848                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 849                 interrupt-names = "otg_id", "otg_bvalid",
 850                           "otg_linestate", "host0_linestate",
 851                           "host1_linestate";
 852                 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
 853                 /*        <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
 854                 /*clocks = <&clk_gates7 9>;*/
 855                 /*clock-names = "hclk_usb_peri";*/
 856                 rockchip,remote_wakeup;
 857                 rockchip,usb_irq_wakeup;
 858
 859                 usb_bc{
 860                         compatible = "synopsys,phy";
 861                                         /* offset bit mask */
 862                         rk_usb,bvalid     = <0x288 14 1>;
 863                         rk_usb,dcdenb     = <0x328 14 1>;
 864                         rk_usb,vdatsrcenb = <0x328  7 1>;
 865                         rk_usb,vdatdetenb = <0x328  6 1>;
 866                         rk_usb,chrgsel    = <0x328  5 1>;
 867                         rk_usb,chgdet     = <0x2cc 23 1>;
 868                         rk_usb,fsvminus   = <0x2cc 25 1>;
 869                         rk_usb,fsvplus    = <0x2cc 24 1>;
 870                 };
 871         };
 872
 873         usb0: usb@ff580000 {
 874                 compatible = "rockchip,rk3288_usb20_otg";
 875                 reg = <0xff580000 0x40000>;
 876                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 877                 /*clocks = <&clk_gates13 4>, <&clk_gates7 4>;*/
 878                 /*clock-names = "clk_usbphy0", "hclk_usb0";*/
 879         };
 880
 881         usb1: usb@ff540000 {
 882                 compatible = "rockchip,rk3288_usb20_host";
 883                 reg = <0xff540000 0x40000>;
 884                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 885                 /*clocks = <&clk_gates13 5>, <&clk_gates7 6>;*/
 886                 /*clock-names = "clk_usbphy1", "hclk_usb1";*/
 887         };
 888
 889         usb2: usb@ff500000 {
 890                 compatible = "rockchip,rk3288_usbhs_host";
 891                 reg = <0xff500000 0x40000>;
 892                 /*clocks = <&clk_gates13 6>, <&clk_gates7 7>;*/
 893                 /*clock-names = "clk_usbphy2", "hclk_usb2";*/
 894                 #address-cells = <1>;
 895                 #size-cells = <1>;
 896                 ranges;
 897
 898                 ehci: ehci@ff500000 {
 899                         compatible = "rockchip,rk3288_rk_ehci_host";
 900                         reg = <0xff500000 0x20000>;
 901                         interrupt-parent = <&gic>;
 902                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 903                 };
 904
 905                 ohci: ohci@ff520000 {
 906                         compatible = "rockchip,rk3288_rk_ohci_host";
 907                         reg = <0xff520000 0x20000>;
 908                         interrupt-parent = <&gic>;
 909                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 910                 };
 911         };
 912
 913         hsic: hsic@ff5c0000 {
 914                 compatible = "rockchip,rk3288_rk_hsic_host";
 915                 reg = <0xff5c0000 0x40000>;
 916                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 917                 /*clocks = <&hsicphy_480m>, <&clk_gates7 8>,*/
 918                 /*         <&hsicphy_12m>, <&clk_otgphy1_480m>,*/
 919                 /*         <&clk_otgphy2_480m>;*/
 920                 /*clock-names = "hsicphy_480m", "hclk_hsic",*/
 921                 /*              "hsicphy_12m", "hsic_usbphy1",*/
 922                 /*              "hsic_usbphy2";*/
 923         };
 924
 925         gmac: eth@ff290000 {
 926                 compatible = "rockchip,gmac";
 927                 reg = <0xff290000 0x10000>;
 928                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 929                 interrupt-names = "macirq";
 930                 phy-mode = "rmii";
 931                 //phy-mode = "gmii";
 932                 pinctrl-names = "default";
 933                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 934         };
 935     gpu{
 936         compatible = "arm,malit764",
 937                      "arm,malit76x",
 938                      "arm,malit7xx",
 939                      "arm,mali-midgard";
 940         reg = <0xffa30000 0x10000>;
 941         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 942                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 943                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 944         interrupt-names = "JOB",
 945                           "MMU",
 946                           "GPU";
 947     };
 948
 949     iep_mmu{
 950         dbgname = "iep";
 951         compatible = "iommu,iep_mmu";
 952         reg = <0xffa40000 0x10000>;
 953         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 954         interrupt-names = "iep_mmu";
 955     };
 956
 957     vip_mmu{
 958         dbgname = "vip";
 959         compatible = "iommu,vip_mmu";
 960         reg = <0xffa40000 0x10000>;
 961         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 962         interrupt-names = "vip_mmu";
 963     };
 964
 965     isp0_mmu{
 966         dbgname = "isp0";
 967         compatible = "iommu,isp0_mmu";
 968         reg = <0xffa40000 0x10000>;
 969         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 970         interrupt-names = "isp0_mmu";
 971     };
 972
 973     isp1_mmu{
 974         dbgname = "isp1";
 975         compatible = "iommu,isp1_mmu";
 976         reg = <0xffa40000 0x10000>;
 977         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 978         interrupt-names = "isp1_mmu";
 979     };
 980
 981     vopb_mmu{
 982         dbgname = "vopb";
 983         compatible = "iommu,vopb_mmu";
 984         reg = <0xffa40000 0x10000>;
 985         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 986         interrupt-names = "vopb_mmu";
 987     };
 988
 989     vopl_mmu{
 990         dbgname = "vopl";
 991         compatible = "iommu,vopl_mmu";
 992         reg = <0xffa40000 0x10000>;
 993         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 994         interrupt-names = "vopl_mmu";
 995     };
 996
 997     rockchip_suspend {
 998                     rockchip,ctrbits = <
 999                                     (0
1000                                    // RKPM_CTR_PWR_DMNS
1001                                     //|RKPM_CTR_GTCLKS
1002                                     //|RKPM_CTR_PLLS
1003                                     //|RKPM_CTR_SYSCLK_DIV
1004                                     |RKPM_CTR_NORIDLE_MD
1005                                     )
1006                                 >;
1007                   rockchip,pmic-gpios=<
1008                                                     RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1009                                                     RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1010                                                     >;
1011             };
1012
1013 };