arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/display/drm_mipi_dsi.h>
  50 #include "skeleton.dtsi"
  51
  52 / {
  53         compatible = "rockchip,rk3288";
  54
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 mshc0 = &emmc;
  66                 mshc1 = &sdmmc;
  67                 mshc2 = &sdio0;
  68                 mshc3 = &sdio1;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         arm-pmu {
  80                 compatible = "arm,cortex-a12-pmu";
  81                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  85                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  86         };
  87
  88         cpus {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 enable-method = "rockchip,rk3066-smp";
  92                 rockchip,pmu = <&pmu>;
  93
  94                 cpu0: cpu@500 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x500>;
  98                         resets = <&cru SRST_CORE0>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         dynamic-power-coefficient = <322>;
 102                         clocks = <&cru ARMCLK>;
 103                 };
 104                 cpu1: cpu@501 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a12";
 107                         reg = <0x501>;
 108                         resets = <&cru SRST_CORE1>;
 109                         operating-points-v2 = <&cpu0_opp_table>;
 110                 };
 111                 cpu2: cpu@502 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a12";
 114                         reg = <0x502>;
 115                         resets = <&cru SRST_CORE2>;
 116                         operating-points-v2 = <&cpu0_opp_table>;
 117                 };
 118                 cpu3: cpu@503 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a12";
 121                         reg = <0x503>;
 122                         resets = <&cru SRST_CORE3>;
 123                         operating-points-v2 = <&cpu0_opp_table>;
 124                 };
 125         };
 126
 127         cpu0_opp_table: opp_table0 {
 128                 compatible = "operating-points-v2";
 129                 opp-shared;
 130
 131                 opp@126000000 {
 132                         opp-hz = /bits/ 64 <126000000>;
 133                         opp-microvolt = <900000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@216000000 {
 137                         opp-hz = /bits/ 64 <216000000>;
 138                         opp-microvolt = <900000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141                 opp@408000000 {
 142                         opp-hz = /bits/ 64 <408000000>;
 143                         opp-microvolt = <900000>;
 144                         clock-latency-ns = <40000>;
 145                 };
 146                 opp@600000000 {
 147                         opp-hz = /bits/ 64 <600000000>;
 148                         opp-microvolt = <900000>;
 149                         clock-latency-ns = <40000>;
 150                 };
 151                 opp@696000000 {
 152                         opp-hz = /bits/ 64 <696000000>;
 153                         opp-microvolt = <950000>;
 154                         clock-latency-ns = <40000>;
 155                 };
 156                 opp@816000000 {
 157                         opp-hz = /bits/ 64 <816000000>;
 158                         opp-microvolt = <1000000>;
 159                         clock-latency-ns = <40000>;
 160                         opp-suspend;
 161                 };
 162                 opp@1008000000 {
 163                         opp-hz = /bits/ 64 <1008000000>;
 164                         opp-microvolt = <1050000>;
 165                         clock-latency-ns = <40000>;
 166                 };
 167                 opp@1200000000 {
 168                         opp-hz = /bits/ 64 <1200000000>;
 169                         opp-microvolt = <1100000>;
 170                         clock-latency-ns = <40000>;
 171                 };
 172                 opp@1416000000 {
 173                         opp-hz = /bits/ 64 <1416000000>;
 174                         opp-microvolt = <1200000>;
 175                         clock-latency-ns = <40000>;
 176                 };
 177                 opp@1512000000 {
 178                         opp-hz = /bits/ 64 <1512000000>;
 179                         opp-microvolt = <1300000>;
 180                         clock-latency-ns = <40000>;
 181                 };
 182                 opp@1608000000 {
 183                         opp-hz = /bits/ 64 <1608000000>;
 184                         opp-microvolt = <1350000>;
 185                         clock-latency-ns = <40000>;
 186                 };
 187         };
 188
 189         cpu_avs: cpu-avs {
 190                 cluster0-avs {
 191                         cluster-id = <0>;
 192                         min-volt = <900000>; /* uV */
 193                         min-freq = <126000>; /* KHz */
 194                         leakage-adjust-volt = <
 195                         /*  mA        mA         uV */
 196                             0         254        0
 197                         >;
 198                         nvmem-cells = <&cpu_leakage>;
 199                         nvmem-cell-names = "cpu_leakage";
 200                 };
 201         };
 202
 203         amba {
 204                 compatible = "arm,amba-bus";
 205                 #address-cells = <1>;
 206                 #size-cells = <1>;
 207                 ranges;
 208
 209                 dmac_peri: dma-controller@ff250000 {
 210                         compatible = "arm,pl330", "arm,primecell";
 211                         reg = <0xff250000 0x4000>;
 212                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 214                         #dma-cells = <1>;
 215                         arm,pl330-broken-no-flushp;
 216                         peripherals-req-type-burst;
 217                         clocks = <&cru ACLK_DMAC2>;
 218                         clock-names = "apb_pclk";
 219                 };
 220
 221                 dmac_bus_ns: dma-controller@ff600000 {
 222                         compatible = "arm,pl330", "arm,primecell";
 223                         reg = <0xff600000 0x4000>;
 224                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 226                         #dma-cells = <1>;
 227                         arm,pl330-broken-no-flushp;
 228                         peripherals-req-type-burst;
 229                         clocks = <&cru ACLK_DMAC1>;
 230                         clock-names = "apb_pclk";
 231                         status = "disabled";
 232                 };
 233
 234                 dmac_bus_s: dma-controller@ffb20000 {
 235                         compatible = "arm,pl330", "arm,primecell";
 236                         reg = <0xffb20000 0x4000>;
 237                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 239                         #dma-cells = <1>;
 240                         arm,pl330-broken-no-flushp;
 241                         peripherals-req-type-burst;
 242                         clocks = <&cru ACLK_DMAC1>;
 243                         clock-names = "apb_pclk";
 244                 };
 245         };
 246
 247         reserved-memory {
 248                 #address-cells = <1>;
 249                 #size-cells = <1>;
 250                 ranges;
 251
 252                 /*
 253                  * The rk3288 cannot use the memory area above 0xfe000000
 254                  * for dma operations for some reason. While there is
 255                  * probably a better solution available somewhere, we
 256                  * haven't found it yet and while devices with 2GB of ram
 257                  * are not affected, this issue prevents 4GB from booting.
 258                  * So to make these devices at least bootable, block
 259                  * this area for the time being until the real solution
 260                  * is found.
 261                  */
 262                 dma-unusable@fe000000 {
 263                         reg = <0xfe000000 0x1000000>;
 264                 };
 265         };
 266
 267         xin24m: oscillator {
 268                 compatible = "fixed-clock";
 269                 clock-frequency = <24000000>;
 270                 clock-output-names = "xin24m";
 271                 #clock-cells = <0>;
 272         };
 273
 274         timer {
 275                 compatible = "arm,armv7-timer";
 276                 arm,cpu-registers-not-fw-configured;
 277                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 278                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 279                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 280                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 281                 clock-frequency = <24000000>;
 282         };
 283
 284         timer: timer@ff810000 {
 285                 compatible = "rockchip,rk3288-timer";
 286                 reg = <0xff810000 0x20>;
 287                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 289                 clock-names = "timer", "pclk";
 290         };
 291
 292         display-subsystem {
 293                 compatible = "rockchip,display-subsystem";
 294                 ports = <&vopl_out>, <&vopb_out>;
 295         };
 296
 297         sdmmc: dwmmc@ff0c0000 {
 298                 compatible = "rockchip,rk3288-dw-mshc";
 299                 clock-freq-min-max = <400000 150000000>;
 300                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 301                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 302                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 303                 fifo-depth = <0x100>;
 304                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 305                 reg = <0xff0c0000 0x4000>;
 306                 status = "disabled";
 307         };
 308
 309         sdio0: dwmmc@ff0d0000 {
 310                 compatible = "rockchip,rk3288-dw-mshc";
 311                 clock-freq-min-max = <400000 150000000>;
 312                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 313                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 314                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 315                 fifo-depth = <0x100>;
 316                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 317                 reg = <0xff0d0000 0x4000>;
 318                 status = "disabled";
 319         };
 320
 321         sdio1: dwmmc@ff0e0000 {
 322                 compatible = "rockchip,rk3288-dw-mshc";
 323                 clock-freq-min-max = <400000 150000000>;
 324                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 325                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 326                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 327                 fifo-depth = <0x100>;
 328                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 329                 reg = <0xff0e0000 0x4000>;
 330                 status = "disabled";
 331         };
 332
 333         emmc: dwmmc@ff0f0000 {
 334                 compatible = "rockchip,rk3288-dw-mshc";
 335                 clock-freq-min-max = <400000 150000000>;
 336                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 337                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 338                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 339                 fifo-depth = <0x100>;
 340                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 341                 reg = <0xff0f0000 0x4000>;
 342                 status = "disabled";
 343                 supports-emmc;
 344         };
 345
 346         saradc: saradc@ff100000 {
 347                 compatible = "rockchip,saradc";
 348                 reg = <0xff100000 0x100>;
 349                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 350                 #io-channel-cells = <1>;
 351                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 352                 clock-names = "saradc", "apb_pclk";
 353                 resets = <&cru SRST_SARADC>;
 354                 reset-names = "saradc-apb";
 355                 status = "disabled";
 356         };
 357
 358         spi0: spi@ff110000 {
 359                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 360                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 361                 clock-names = "spiclk", "apb_pclk";
 362                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 363                 dma-names = "tx", "rx";
 364                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 367                 reg = <0xff110000 0x1000>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 status = "disabled";
 371         };
 372
 373         spi1: spi@ff120000 {
 374                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 375                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 376                 clock-names = "spiclk", "apb_pclk";
 377                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 378                 dma-names = "tx", "rx";
 379                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 382                 reg = <0xff120000 0x1000>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 status = "disabled";
 386         };
 387
 388         spi2: spi@ff130000 {
 389                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 390                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 391                 clock-names = "spiclk", "apb_pclk";
 392                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 393                 dma-names = "tx", "rx";
 394                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 397                 reg = <0xff130000 0x1000>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 status = "disabled";
 401         };
 402
 403         i2c0: i2c@ff650000 {
 404                 compatible = "rockchip,rk3288-i2c";
 405                 reg = <0xff650000 0x1000>;
 406                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 clock-names = "i2c";
 410                 clocks = <&cru PCLK_I2C0>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&i2c0_xfer>;
 413                 status = "disabled";
 414         };
 415
 416         i2c1: i2c@ff140000 {
 417                 compatible = "rockchip,rk3288-i2c";
 418                 reg = <0xff140000 0x1000>;
 419                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 clock-names = "i2c";
 423                 clocks = <&cru PCLK_I2C1>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&i2c1_xfer>;
 426                 status = "disabled";
 427         };
 428
 429         i2c3: i2c@ff150000 {
 430                 compatible = "rockchip,rk3288-i2c";
 431                 reg = <0xff150000 0x1000>;
 432                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 clock-names = "i2c";
 436                 clocks = <&cru PCLK_I2C3>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&i2c3_xfer>;
 439                 status = "disabled";
 440         };
 441
 442         i2c4: i2c@ff160000 {
 443                 compatible = "rockchip,rk3288-i2c";
 444                 reg = <0xff160000 0x1000>;
 445                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clock-names = "i2c";
 449                 clocks = <&cru PCLK_I2C4>;
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&i2c4_xfer>;
 452                 status = "disabled";
 453         };
 454
 455         i2c5: i2c@ff170000 {
 456                 compatible = "rockchip,rk3288-i2c";
 457                 reg = <0xff170000 0x1000>;
 458                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 clock-names = "i2c";
 462                 clocks = <&cru PCLK_I2C5>;
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&i2c5_xfer>;
 465                 status = "disabled";
 466         };
 467
 468         uart0: serial@ff180000 {
 469                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 470                 reg = <0xff180000 0x100>;
 471                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 472                 reg-shift = <2>;
 473                 reg-io-width = <4>;
 474                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 475                 clock-names = "baudclk", "apb_pclk";
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&uart0_xfer>;
 478                 status = "disabled";
 479         };
 480
 481         uart1: serial@ff190000 {
 482                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 483                 reg = <0xff190000 0x100>;
 484                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 485                 reg-shift = <2>;
 486                 reg-io-width = <4>;
 487                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 488                 clock-names = "baudclk", "apb_pclk";
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&uart1_xfer>;
 491                 status = "disabled";
 492         };
 493
 494         uart2: serial@ff690000 {
 495                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 496                 reg = <0xff690000 0x100>;
 497                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 498                 reg-shift = <2>;
 499                 reg-io-width = <4>;
 500                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 501                 clock-names = "baudclk", "apb_pclk";
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&uart2_xfer>;
 504                 status = "disabled";
 505         };
 506
 507         uart3: serial@ff1b0000 {
 508                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 509                 reg = <0xff1b0000 0x100>;
 510                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 511                 reg-shift = <2>;
 512                 reg-io-width = <4>;
 513                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 514                 clock-names = "baudclk", "apb_pclk";
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&uart3_xfer>;
 517                 status = "disabled";
 518         };
 519
 520         uart4: serial@ff1c0000 {
 521                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 522                 reg = <0xff1c0000 0x100>;
 523                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 524                 reg-shift = <2>;
 525                 reg-io-width = <4>;
 526                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 527                 clock-names = "baudclk", "apb_pclk";
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&uart4_xfer>;
 530                 status = "disabled";
 531         };
 532
 533         thermal_zones: thermal-zones {
 534                 soc_thermal: soc-thermal {
 535                         polling-delay-passive = <200>; /* milliseconds */
 536                         polling-delay = <1000>; /* milliseconds */
 537                         sustainable-power = <1200>; /* milliwatts */
 538
 539                         thermal-sensors = <&tsadc 1>;
 540                         trips {
 541                                 threshold: trip-point@0 {
 542                                         temperature = <75000>; /* millicelsius */
 543                                         hysteresis = <2000>; /* millicelsius */
 544                                         type = "passive";
 545                                 };
 546                                 target: trip-point@1 {
 547                                         temperature = <85000>; /* millicelsius */
 548                                         hysteresis = <2000>; /* millicelsius */
 549                                         type = "passive";
 550                                 };
 551                                 soc_crit: soc-crit {
 552                                         temperature = <90000>; /* millicelsius */
 553                                         hysteresis = <2000>; /* millicelsius */
 554                                         type = "critical";
 555                                 };
 556                         };
 557
 558                         cooling-maps {
 559                                 map0 {
 560                                         trip = <&target>;
 561                                         cooling-device =
 562                                         <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 563                                         contribution = <1024>;
 564                                 };
 565                                 map1 {
 566                                         trip = <&target>;
 567                                         cooling-device =
 568                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 569                                         contribution = <1024>;
 570                                 };
 571                         };
 572                 };
 573
 574                 gpu_thermal: gpu-thermal {
 575                         polling-delay-passive = <200>; /* milliseconds */
 576                         polling-delay = <1000>; /* milliseconds */
 577                         thermal-sensors = <&tsadc 2>;
 578                 };
 579         };
 580
 581         tsadc: tsadc@ff280000 {
 582                 compatible = "rockchip,rk3288-tsadc";
 583                 reg = <0xff280000 0x100>;
 584                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 585                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 586                 clock-names = "tsadc", "apb_pclk";
 587                 assigned-clocks = <&cru SCLK_TSADC>;
 588                 assigned-clock-rates = <10000>;
 589                 resets = <&cru SRST_TSADC>;
 590                 reset-names = "tsadc-apb";
 591                 pinctrl-names = "init", "default", "sleep";
 592                 pinctrl-0 = <&otp_gpio>;
 593                 pinctrl-1 = <&otp_out>;
 594                 pinctrl-2 = <&otp_gpio>;
 595                 #thermal-sensor-cells = <1>;
 596                 rockchip,hw-tshut-temp = <95000>;
 597                 status = "disabled";
 598         };
 599
 600         gmac: ethernet@ff290000 {
 601                 compatible = "rockchip,rk3288-gmac";
 602                 reg = <0xff290000 0x10000>;
 603                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 604                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 605                 interrupt-names = "macirq", "eth_wake_irq";
 606                 rockchip,grf = <&grf>;
 607                 clocks = <&cru SCLK_MAC>,
 608                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 609                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 610                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 611                 clock-names = "stmmaceth",
 612                         "mac_clk_rx", "mac_clk_tx",
 613                         "clk_mac_ref", "clk_mac_refout",
 614                         "aclk_mac", "pclk_mac";
 615                 resets = <&cru SRST_MAC>;
 616                 reset-names = "stmmaceth";
 617                 status = "disabled";
 618         };
 619
 620         usb_host0_ehci: usb@ff500000 {
 621                 compatible = "generic-ehci";
 622                 reg = <0xff500000 0x100>;
 623                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&cru HCLK_USBHOST0>;
 625                 clock-names = "usbhost";
 626                 phys = <&usbphy1>;
 627                 phy-names = "usb";
 628                 status = "disabled";
 629         };
 630
 631         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 632
 633         usb_host1: usb@ff540000 {
 634                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 635                                 "snps,dwc2";
 636                 reg = <0xff540000 0x40000>;
 637                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 638                 clocks = <&cru HCLK_USBHOST1>;
 639                 clock-names = "otg";
 640                 dr_mode = "host";
 641                 phys = <&usbphy2>;
 642                 phy-names = "usb2-phy";
 643                 status = "disabled";
 644         };
 645
 646         usb_otg: usb@ff580000 {
 647                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 648                                 "snps,dwc2";
 649                 reg = <0xff580000 0x40000>;
 650                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&cru HCLK_OTG0>;
 652                 clock-names = "otg";
 653                 dr_mode = "otg";
 654                 g-np-tx-fifo-size = <16>;
 655                 g-rx-fifo-size = <275>;
 656                 g-tx-fifo-size = <256 128 128 64 64 32>;
 657                 g-use-dma;
 658                 phys = <&usbphy0>;
 659                 phy-names = "usb2-phy";
 660                 status = "disabled";
 661         };
 662
 663         usb_hsic: usb@ff5c0000 {
 664                 compatible = "generic-ehci";
 665                 reg = <0xff5c0000 0x100>;
 666                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 667                 clocks = <&cru HCLK_HSIC>;
 668                 clock-names = "usbhost";
 669                 status = "disabled";
 670         };
 671
 672         dmc: dmc@ff610000 {
 673                 compatible = "rockchip,rk3288-dmc", "syscon";
 674                 rockchip,cru = <&cru>;
 675                 rockchip,grf = <&grf>;
 676                 rockchip,pmu = <&pmu>;
 677                 rockchip,sgrf = <&sgrf>;
 678                 rockchip,noc = <&noc>;
 679                 reg = <0xff610000 0x3fc
 680                        0xff620000 0x294
 681                        0xff630000 0x3fc
 682                        0xff640000 0x294>;
 683                 rockchip,sram = <&ddr_sram>;
 684                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 685                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 686                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 687                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 688                               "pclk_ddrupctl1", "pclk_publ1",
 689                               "arm_clk", "aclk_dmac1";
 690         };
 691
 692         i2c2: i2c@ff660000 {
 693                 compatible = "rockchip,rk3288-i2c";
 694                 reg = <0xff660000 0x1000>;
 695                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 696                 #address-cells = <1>;
 697                 #size-cells = <0>;
 698                 clock-names = "i2c";
 699                 clocks = <&cru PCLK_I2C2>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&i2c2_xfer>;
 702                 status = "disabled";
 703         };
 704
 705         pwm0: pwm@ff680000 {
 706                 compatible = "rockchip,rk3288-pwm";
 707                 reg = <0xff680000 0x10>;
 708                 #pwm-cells = <3>;
 709                 pinctrl-names = "default";
 710                 pinctrl-0 = <&pwm0_pin>;
 711                 clocks = <&cru PCLK_PWM>;
 712                 clock-names = "pwm";
 713                 status = "disabled";
 714         };
 715
 716         pwm1: pwm@ff680010 {
 717                 compatible = "rockchip,rk3288-pwm";
 718                 reg = <0xff680010 0x10>;
 719                 #pwm-cells = <3>;
 720                 pinctrl-names = "default";
 721                 pinctrl-0 = <&pwm1_pin>;
 722                 clocks = <&cru PCLK_PWM>;
 723                 clock-names = "pwm";
 724                 status = "disabled";
 725         };
 726
 727         pwm2: pwm@ff680020 {
 728                 compatible = "rockchip,rk3288-pwm";
 729                 reg = <0xff680020 0x10>;
 730                 #pwm-cells = <3>;
 731                 pinctrl-names = "default";
 732                 pinctrl-0 = <&pwm2_pin>;
 733                 clocks = <&cru PCLK_PWM>;
 734                 clock-names = "pwm";
 735                 status = "disabled";
 736         };
 737
 738         pwm3: pwm@ff680030 {
 739                 compatible = "rockchip,rk3288-pwm";
 740                 reg = <0xff680030 0x10>;
 741                 #pwm-cells = <2>;
 742                 pinctrl-names = "default";
 743                 pinctrl-0 = <&pwm3_pin>;
 744                 clocks = <&cru PCLK_PWM>;
 745                 clock-names = "pwm";
 746                 status = "disabled";
 747         };
 748
 749         bus_intmem@ff700000 {
 750                 compatible = "mmio-sram";
 751                 reg = <0xff700000 0x18000>;
 752                 #address-cells = <1>;
 753                 #size-cells = <1>;
 754                 ranges = <0 0xff700000 0x18000>;
 755                 smp-sram@0 {
 756                         compatible = "rockchip,rk3066-smp-sram";
 757                         reg = <0x00 0x10>;
 758                 };
 759                 ddr_sram: ddr-sram@1000 {
 760                         compatible = "rockchip,rk3288-ddr-sram";
 761                         reg = <0x1000 0x4000>;
 762                 };
 763         };
 764
 765         sram@ff720000 {
 766                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 767                 reg = <0xff720000 0x1000>;
 768         };
 769
 770         qos_gpu_r: qos@ffaa0000 {
 771                 compatible = "syscon";
 772                 reg = <0xffaa0000 0x20>;
 773         };
 774
 775         qos_gpu_w: qos@ffaa0080 {
 776                 compatible = "syscon";
 777                 reg = <0xffaa0080 0x20>;
 778         };
 779
 780         qos_vio1_vop: qos@ffad0000 {
 781                 compatible = "syscon";
 782                 reg = <0xffad0000 0x20>;
 783         };
 784
 785         qos_vio1_isp_w0: qos@ffad0100 {
 786                 compatible = "syscon";
 787                 reg = <0xffad0100 0x20>;
 788         };
 789
 790         qos_vio1_isp_w1: qos@ffad0180 {
 791                 compatible = "syscon";
 792                 reg = <0xffad0180 0x20>;
 793         };
 794
 795         qos_vio0_vop: qos@ffad0400 {
 796                 compatible = "syscon";
 797                 reg = <0xffad0400 0x20>;
 798         };
 799
 800         qos_vio0_vip: qos@ffad0480 {
 801                 compatible = "syscon";
 802                 reg = <0xffad0480 0x20>;
 803         };
 804
 805         qos_vio0_iep: qos@ffad0500 {
 806                 compatible = "syscon";
 807                 reg = <0xffad0500 0x20>;
 808         };
 809
 810         qos_vio2_rga_r: qos@ffad0800 {
 811                 compatible = "syscon";
 812                 reg = <0xffad0800 0x20>;
 813         };
 814
 815         qos_vio2_rga_w: qos@ffad0880 {
 816                 compatible = "syscon";
 817                 reg = <0xffad0880 0x20>;
 818         };
 819
 820         qos_vio1_isp_r: qos@ffad0900 {
 821                 compatible = "syscon";
 822                 reg = <0xffad0900 0x20>;
 823         };
 824
 825         qos_video: qos@ffae0000 {
 826                 compatible = "syscon";
 827                 reg = <0xffae0000 0x20>;
 828         };
 829
 830         qos_hevc_r: qos@ffaf0000 {
 831                 compatible = "syscon";
 832                 reg = <0xffaf0000 0x20>;
 833         };
 834
 835         qos_hevc_w: qos@ffaf0080 {
 836                 compatible = "syscon";
 837                 reg = <0xffaf0080 0x20>;
 838         };
 839
 840         pmu: power-management@ff730000 {
 841                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 842                 reg = <0xff730000 0x100>;
 843
 844                 power: power-controller {
 845                         compatible = "rockchip,rk3288-power-controller";
 846                         #power-domain-cells = <1>;
 847                         #address-cells = <1>;
 848                         #size-cells = <0>;
 849
 850                         /*
 851                          * Note: Although SCLK_* are the working clocks
 852                          * of device without including on the NOC, needed for
 853                          * synchronous reset.
 854                          *
 855                          * The clocks on the which NOC:
 856                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 857                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 858                          * ACLK_RGA is on ACLK_RGA_NIU.
 859                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 860                          *
 861                          * Which clock are device clocks:
 862                          *      clocks          devices
 863                          *      *_IEP           IEP:Image Enhancement Processor
 864                          *      *_ISP           ISP:Image Signal Processing
 865                          *      *_VIP           VIP:Video Input Processor
 866                          *      *_VOP*          VOP:Visual Output Processor
 867                          *      *_RGA           RGA
 868                          *      *_EDP*          EDP
 869                          *      *_LVDS_*        LVDS
 870                          *      *_HDMI          HDMI
 871                          *      *_MIPI_*        MIPI
 872                          */
 873                         pd_vio@RK3288_PD_VIO {
 874                                 reg = <RK3288_PD_VIO>;
 875                                 clocks = <&cru ACLK_IEP>,
 876                                          <&cru ACLK_ISP>,
 877                                          <&cru ACLK_RGA>,
 878                                          <&cru ACLK_VIP>,
 879                                          <&cru ACLK_VOP0>,
 880                                          <&cru ACLK_VOP1>,
 881                                          <&cru DCLK_VOP0>,
 882                                          <&cru DCLK_VOP1>,
 883                                          <&cru HCLK_IEP>,
 884                                          <&cru HCLK_ISP>,
 885                                          <&cru HCLK_RGA>,
 886                                          <&cru HCLK_VIP>,
 887                                          <&cru HCLK_VOP0>,
 888                                          <&cru HCLK_VOP1>,
 889                                          <&cru PCLK_EDP_CTRL>,
 890                                          <&cru PCLK_HDMI_CTRL>,
 891                                          <&cru PCLK_LVDS_PHY>,
 892                                          <&cru PCLK_MIPI_CSI>,
 893                                          <&cru PCLK_MIPI_DSI0>,
 894                                          <&cru PCLK_MIPI_DSI1>,
 895                                          <&cru SCLK_EDP_24M>,
 896                                          <&cru SCLK_EDP>,
 897                                          <&cru SCLK_ISP_JPE>,
 898                                          <&cru SCLK_ISP>,
 899                                          <&cru SCLK_RGA>;
 900                                 pm_qos = <&qos_vio0_iep>,
 901                                          <&qos_vio1_vop>,
 902                                          <&qos_vio1_isp_w0>,
 903                                          <&qos_vio1_isp_w1>,
 904                                          <&qos_vio0_vop>,
 905                                          <&qos_vio0_vip>,
 906                                          <&qos_vio2_rga_r>,
 907                                          <&qos_vio2_rga_w>,
 908                                          <&qos_vio1_isp_r>;
 909                         };
 910
 911                         /*
 912                          * Note: The following 3 are HEVC(H.265) clocks,
 913                          * and on the ACLK_HEVC_NIU (NOC).
 914                          */
 915                         pd_hevc@RK3288_PD_HEVC {
 916                                 reg = <RK3288_PD_HEVC>;
 917                                 clocks = <&cru ACLK_HEVC>,
 918                                          <&cru SCLK_HEVC_CABAC>,
 919                                          <&cru SCLK_HEVC_CORE>;
 920                                 pm_qos = <&qos_hevc_r>,
 921                                          <&qos_hevc_w>;
 922                         };
 923
 924                         /*
 925                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 926                          * (video endecoder & decoder) clocks that on the
 927                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 928                          */
 929                         pd_video@RK3288_PD_VIDEO {
 930                                 reg = <RK3288_PD_VIDEO>;
 931                                 clocks = <&cru ACLK_VCODEC>,
 932                                          <&cru HCLK_VCODEC>;
 933                                 pm_qos = <&qos_video>;
 934                         };
 935
 936                         /*
 937                          * Note: ACLK_GPU is the GPU clock,
 938                          * and on the ACLK_GPU_NIU (NOC).
 939                          */
 940                         pd_gpu@RK3288_PD_GPU {
 941                                 reg = <RK3288_PD_GPU>;
 942                                 clocks = <&cru ACLK_GPU>;
 943                                 pm_qos = <&qos_gpu_r>,
 944                                          <&qos_gpu_w>;
 945                         };
 946                 };
 947
 948                 reboot-mode {
 949                         compatible = "syscon-reboot-mode";
 950                         offset = <0x94>;
 951                         mode-normal = <BOOT_NORMAL>;
 952                         mode-recovery = <BOOT_RECOVERY>;
 953                         mode-bootloader = <BOOT_FASTBOOT>;
 954                         mode-loader = <BOOT_BL_DOWNLOAD>;
 955                         mode-ums = <BOOT_UMS>;
 956                 };
 957         };
 958
 959         sgrf: syscon@ff740000 {
 960                 compatible = "rockchip,rk3288-sgrf", "syscon";
 961                 reg = <0xff740000 0x1000>;
 962         };
 963
 964         cru: clock-controller@ff760000 {
 965                 compatible = "rockchip,rk3288-cru";
 966                 reg = <0xff760000 0x1000>;
 967                 rockchip,grf = <&grf>;
 968                 #clock-cells = <1>;
 969                 #reset-cells = <1>;
 970                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 971                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 972                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 973                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 974                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 975                                   <&cru PCLK_PERI>;
 976                 assigned-clock-rates = <0>, <0>,
 977                                        <594000000>, <400000000>,
 978                                        <500000000>, <300000000>,
 979                                        <150000000>, <75000000>,
 980                                        <300000000>, <150000000>,
 981                                        <75000000>;
 982                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 983         };
 984
 985         grf: syscon@ff770000 {
 986                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 987                 reg = <0xff770000 0x1000>;
 988
 989                 edp_phy: edp-phy {
 990                         compatible = "rockchip,rk3288-dp-phy";
 991                         clocks = <&cru SCLK_EDP_24M>;
 992                         clock-names = "24m";
 993                         #phy-cells = <0>;
 994                         status = "disabled";
 995                 };
 996
 997                 io_domains: io-domains {
 998                         compatible = "rockchip,rk3288-io-voltage-domain";
 999                         status = "disabled";
1000                 };
1001
1002                 usbphy: usbphy {
1003                         compatible = "rockchip,rk3288-usb-phy";
1004                         #address-cells = <1>;
1005                         #size-cells = <0>;
1006                         status = "disabled";
1007
1008                         usbphy0: usb-phy@320 {
1009                                 #phy-cells = <0>;
1010                                 reg = <0x320>;
1011                                 clocks = <&cru SCLK_OTGPHY0>;
1012                                 clock-names = "phyclk";
1013                                 #clock-cells = <0>;
1014                                 resets = <&cru SRST_USBOTG_PHY>;
1015                                 reset-names = "phy-reset";
1016                         };
1017
1018                         usbphy1: usb-phy@334 {
1019                                 #phy-cells = <0>;
1020                                 reg = <0x334>;
1021                                 clocks = <&cru SCLK_OTGPHY1>;
1022                                 clock-names = "phyclk";
1023                                 #clock-cells = <0>;
1024                         };
1025
1026                         usbphy2: usb-phy@348 {
1027                                 #phy-cells = <0>;
1028                                 reg = <0x348>;
1029                                 clocks = <&cru SCLK_OTGPHY2>;
1030                                 clock-names = "phyclk";
1031                                 #clock-cells = <0>;
1032                                 resets = <&cru SRST_USBHOST1_PHY>;
1033                                 reset-names = "phy-reset";
1034                         };
1035                 };
1036         };
1037
1038         wdt: watchdog@ff800000 {
1039                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1040                 reg = <0xff800000 0x100>;
1041                 clocks = <&cru PCLK_WDT>;
1042                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1043                 status = "disabled";
1044         };
1045
1046         spdif: sound@ff88b0000 {
1047                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1048                 reg = <0xff8b0000 0x10000>;
1049                 #sound-dai-cells = <0>;
1050                 clock-names = "hclk", "mclk";
1051                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1052                 dmas = <&dmac_bus_s 3>;
1053                 dma-names = "tx";
1054                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1055                 pinctrl-names = "default";
1056                 pinctrl-0 = <&spdif_tx>;
1057                 rockchip,grf = <&grf>;
1058                 status = "disabled";
1059         };
1060
1061         i2s: i2s@ff890000 {
1062                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1063                 reg = <0xff890000 0x10000>;
1064                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1065                 #address-cells = <1>;
1066                 #size-cells = <0>;
1067                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1068                 dma-names = "tx", "rx";
1069                 clock-names = "i2s_hclk", "i2s_clk";
1070                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1071                 pinctrl-names = "default";
1072                 pinctrl-0 = <&i2s0_bus>;
1073                 rockchip,playback-channels = <8>;
1074                 rockchip,capture-channels = <2>;
1075                 status = "disabled";
1076         };
1077
1078         cif_isp0: cif_isp@ff910000 {
1079                 compatible = "rockchip,rk3288-cif-isp";
1080                 rockchip,grf = <&grf>;
1081                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1082                 reg-names = "register", "csihost-register";
1083                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1084                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1085                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1086                         <&cru SCLK_MIPIDSI_24M>;
1087                 clock-names = "aclk_isp", "hclk_isp",
1088                         "sclk_isp", "sclk_isp_jpe",
1089                         "pclk_mipi_csi", "pclk_isp_in",
1090                         "sclk_mipidsi_24m";
1091                 resets = <&cru SRST_ISP>;
1092                 reset-names = "rst_isp";
1093                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1094                 interrupt-names = "cif_isp10_irq";
1095                 status = "disabled";
1096         };
1097
1098         rga: rga@ff920000 {
1099                 compatible = "rockchip,rk3288-rga";
1100                 reg = <0xff920000 0x180>;
1101                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1102                 interrupt-names = "rga";
1103                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1104                 clock-names = "aclk", "hclk", "sclk";
1105                 power-domains = <&power RK3288_PD_VIO>;
1106                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1107                 reset-names = "core", "axi", "ahb";
1108                 dma-coherent;
1109                 status = "disabled";
1110         };
1111
1112         vopb: vop@ff930000 {
1113                 compatible = "rockchip,rk3288-vop";
1114                 reg = <0xff930000 0x19c>;
1115                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1116                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1117                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1118                 power-domains = <&power RK3288_PD_VIO>;
1119                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1120                 reset-names = "axi", "ahb", "dclk";
1121                 iommus = <&vopb_mmu>;
1122                 status = "disabled";
1123
1124                 vopb_out: port {
1125                         #address-cells = <1>;
1126                         #size-cells = <0>;
1127
1128                         vopb_out_hdmi: endpoint@0 {
1129                                 reg = <0>;
1130                                 remote-endpoint = <&hdmi_in_vopb>;
1131                         };
1132
1133                         vopb_out_edp: endpoint@1 {
1134                                 reg = <1>;
1135                                 remote-endpoint = <&edp_in_vopb>;
1136                         };
1137
1138                         vopb_out_mipi: endpoint@2 {
1139                                 reg = <2>;
1140                                 remote-endpoint = <&mipi_in_vopb>;
1141                         };
1142
1143                         vopb_out_lvds: endpoint@3 {
1144                                 reg = <3>;
1145                                 remote-endpoint = <&lvds_in_vopb>;
1146                         };
1147                 };
1148         };
1149
1150         vopb_mmu: iommu@ff930300 {
1151                 compatible = "rockchip,iommu";
1152                 reg = <0xff930300 0x100>;
1153                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1154                 interrupt-names = "vopb_mmu";
1155                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1156                 clock-names = "aclk", "hclk";
1157                 power-domains = <&power RK3288_PD_VIO>;
1158                 #iommu-cells = <0>;
1159                 status = "disabled";
1160         };
1161
1162         vopl: vop@ff940000 {
1163                 compatible = "rockchip,rk3288-vop";
1164                 reg = <0xff940000 0x19c>;
1165                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1166                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1167                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1168                 power-domains = <&power RK3288_PD_VIO>;
1169                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1170                 reset-names = "axi", "ahb", "dclk";
1171                 iommus = <&vopl_mmu>;
1172                 status = "disabled";
1173
1174                 vopl_out: port {
1175                         #address-cells = <1>;
1176                         #size-cells = <0>;
1177
1178                         vopl_out_hdmi: endpoint@0 {
1179                                 reg = <0>;
1180                                 remote-endpoint = <&hdmi_in_vopl>;
1181                         };
1182
1183                         vopl_out_edp: endpoint@1 {
1184                                 reg = <1>;
1185                                 remote-endpoint = <&edp_in_vopl>;
1186                         };
1187
1188                         vopl_out_mipi: endpoint@2 {
1189                                 reg = <2>;
1190                                 remote-endpoint = <&mipi_in_vopl>;
1191                         };
1192
1193                         vopl_out_lvds: endpoint@3 {
1194                                 reg = <3>;
1195                                 remote-endpoint = <&lvds_in_vopl>;
1196                         };
1197
1198                 };
1199         };
1200
1201         vopl_mmu: iommu@ff940300 {
1202                 compatible = "rockchip,iommu";
1203                 reg = <0xff940300 0x100>;
1204                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1205                 interrupt-names = "vopl_mmu";
1206                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1207                 clock-names = "aclk", "hclk";
1208                 power-domains = <&power RK3288_PD_VIO>;
1209                 #iommu-cells = <0>;
1210                 status = "disabled";
1211         };
1212
1213         mipi_dsi: mipi@ff960000 {
1214                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1215                 reg = <0xff960000 0x4000>;
1216                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1217                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1218                 clock-names = "ref", "pclk";
1219                 power-domains = <&power RK3288_PD_VIO>;
1220                 rockchip,grf = <&grf>;
1221                 #address-cells = <1>;
1222                 #size-cells = <0>;
1223                 status = "disabled";
1224
1225                 ports {
1226                         mipi_in: port {
1227                                 #address-cells = <1>;
1228                                 #size-cells = <0>;
1229                                 mipi_in_vopb: endpoint@0 {
1230                                         reg = <0>;
1231                                         remote-endpoint = <&vopb_out_mipi>;
1232                                 };
1233                                 mipi_in_vopl: endpoint@1 {
1234                                         reg = <1>;
1235                                         remote-endpoint = <&vopl_out_mipi>;
1236                                 };
1237                         };
1238                 };
1239         };
1240
1241         edp: dp@ff970000 {
1242                 compatible = "rockchip,rk3288-dp";
1243                 reg = <0xff970000 0x4000>;
1244                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1245                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1246                 clock-names = "dp", "pclk";
1247                 power-domains = <&power RK3288_PD_VIO>;
1248                 phys = <&edp_phy>;
1249                 phy-names = "dp";
1250                 resets = <&cru SRST_EDP>;
1251                 reset-names = "dp";
1252                 rockchip,grf = <&grf>;
1253                 status = "disabled";
1254
1255                 ports {
1256                         #address-cells = <1>;
1257                         #size-cells = <0>;
1258                         edp_in: port@0 {
1259                                 reg = <0>;
1260                                 #address-cells = <1>;
1261                                 #size-cells = <0>;
1262                                 edp_in_vopb: endpoint@0 {
1263                                         reg = <0>;
1264                                         remote-endpoint = <&vopb_out_edp>;
1265                                 };
1266                                 edp_in_vopl: endpoint@1 {
1267                                         reg = <1>;
1268                                         remote-endpoint = <&vopl_out_edp>;
1269                                 };
1270                         };
1271                 };
1272         };
1273
1274         lvds: lvds@ff96c000 {
1275                 compatible = "rockchip,rk3288-lvds";
1276                 reg = <0xff96c000 0x4000>;
1277                 clocks = <&cru PCLK_LVDS_PHY>;
1278                 clock-names = "pclk_lvds";
1279                 pinctrl-names = "default";
1280                 pinctrl-0 = <&lcdc0_ctl>;
1281                 power-domains = <&power RK3288_PD_VIO>;
1282                 rockchip,grf = <&grf>;
1283                 status = "disabled";
1284
1285                 ports {
1286                         #address-cells = <1>;
1287                         #size-cells = <0>;
1288
1289                         lvds_in: port@0 {
1290                                 reg = <0>;
1291
1292                                 #address-cells = <1>;
1293                                 #size-cells = <0>;
1294
1295                                 lvds_in_vopb: endpoint@0 {
1296                                         reg = <0>;
1297                                         remote-endpoint = <&vopb_out_lvds>;
1298                                 };
1299                                 lvds_in_vopl: endpoint@1 {
1300                                         reg = <1>;
1301                                         remote-endpoint = <&vopl_out_lvds>;
1302                                 };
1303                         };
1304                 };
1305         };
1306
1307         hdmi: hdmi@ff980000 {
1308                 compatible = "rockchip,rk3288-dw-hdmi";
1309                 reg = <0xff980000 0x20000>;
1310                 reg-io-width = <4>;
1311                 rockchip,grf = <&grf>;
1312                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1313                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1314                 clock-names = "iahb", "isfr";
1315                 pinctrl-names = "default";
1316                 pinctrl-0 = <&hdmi_ddc>;
1317                 power-domains = <&power RK3288_PD_VIO>;
1318                 status = "disabled";
1319
1320                 ports {
1321                         hdmi_in: port {
1322                                 #address-cells = <1>;
1323                                 #size-cells = <0>;
1324                                 hdmi_in_vopb: endpoint@0 {
1325                                         reg = <0>;
1326                                         remote-endpoint = <&vopb_out_hdmi>;
1327                                 };
1328                                 hdmi_in_vopl: endpoint@1 {
1329                                         reg = <1>;
1330                                         remote-endpoint = <&vopl_out_hdmi>;
1331                                 };
1332                         };
1333                 };
1334         };
1335
1336         vpu: video-codec@ff9a0000 {
1337                 compatible = "rockchip,rk3288-vpu";
1338                 reg = <0xff9a0000 0x800>;
1339                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1340                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1341                 interrupt-names = "vepu", "vdpu";
1342                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1343                 clock-names = "aclk", "hclk";
1344                 power-domains = <&power RK3288_PD_VIDEO>;
1345                 iommus = <&vpu_mmu>;
1346                 assigned-clocks = <&cru ACLK_VCODEC>;
1347                 assigned-clock-rates = <400000000>;
1348                 status = "disabled";
1349         };
1350
1351         vpu_service: vpu-service@ff9a0000 {
1352                 compatible = "rockchip,vpu_service";
1353                 reg = <0xff9a0000 0x800>;
1354                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1355                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1356                 interrupt-names = "irq_enc", "irq_dec";
1357                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1358                 clock-names = "aclk_vcodec", "hclk_vcodec";
1359                 power-domains = <&power RK3288_PD_VIDEO>;
1360                 rockchip,grf = <&grf>;
1361                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1362                 reset-names = "video_a", "video_h";
1363                 iommus = <&vpu_mmu>;
1364                 iommu_enabled = <1>;
1365                 dev_mode = <0>;
1366                 status = "disabled";
1367                 /* 0 means ion, 1 means drm */
1368                 allocator = <1>;
1369         };
1370
1371         vpu_mmu: iommu@ff9a0800 {
1372                 compatible = "rockchip,iommu";
1373                 reg = <0xff9a0800 0x100>;
1374                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1375                 interrupt-names = "vpu_mmu";
1376                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1377                 clock-names = "aclk", "hclk";
1378                 power-domains = <&power RK3288_PD_VIDEO>;
1379                 #iommu-cells = <0>;
1380         };
1381
1382         hevc_service: hevc-service@ff9c0000 {
1383                 compatible = "rockchip,hevc_service";
1384                 reg = <0xff9c0000 0x400>;
1385                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1386                 interrupt-names = "irq_dec";
1387                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1388                         <&cru SCLK_HEVC_CORE>,
1389                         <&cru SCLK_HEVC_CABAC>;
1390                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1391                         "clk_cabac";
1392                 /*
1393                  * The 4K hevc would also work well with 500/125/300/300,
1394                  * no more err irq and reset request.
1395                  */
1396                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1397                                   <&cru SCLK_HEVC_CORE>,
1398                                   <&cru SCLK_HEVC_CABAC>;
1399                 assigned-clock-rates = <400000000>, <100000000>,
1400                                        <300000000>, <300000000>;
1401
1402                 resets = <&cru SRST_HEVC>;
1403                 reset-names = "video";
1404                 power-domains = <&power RK3288_PD_HEVC>;
1405                 rockchip,grf = <&grf>;
1406                 dev_mode = <1>;
1407                 iommus = <&hevc_mmu>;
1408                 iommu_enabled = <1>;
1409                 status = "disabled";
1410                 /* 0 means ion, 1 means drm */
1411                 allocator = <1>;
1412         };
1413
1414         hevc_mmu: iommu@ff9c0440 {
1415                 compatible = "rockchip,iommu";
1416                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1417                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1418                 interrupt-names = "hevc_mmu";
1419                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1420                         <&cru SCLK_HEVC_CORE>,
1421                         <&cru SCLK_HEVC_CABAC>;
1422                 clock-names = "aclk", "hclk", "clk_core",
1423                         "clk_cabac";
1424                 power-domains = <&power RK3288_PD_HEVC>;
1425                 #iommu-cells = <0>;
1426         };
1427
1428         gpu: gpu@ffa30000 {
1429                 compatible = "arm,malit764",
1430                              "arm,malit76x",
1431                              "arm,malit7xx",
1432                              "arm,mali-midgard";
1433                 reg = <0xffa30000 0x10000>;
1434                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1435                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1436                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1437                 interrupt-names = "JOB", "MMU", "GPU";
1438                 clocks = <&cru ACLK_GPU>;
1439                 clock-names = "clk_mali";
1440                 operating-points-v2 = <&gpu_opp_table>;
1441                 #cooling-cells = <2>; /* min followed by max */
1442                 power-domains = <&power RK3288_PD_GPU>;
1443                 status = "disabled";
1444
1445                 upthreshold = <75>;
1446                 downdifferential = <10>;
1447
1448                 gpu_power_model: power_model {
1449                         compatible = "arm,mali-simple-power-model";
1450                         voltage = <950>;
1451                         frequency = <500>;
1452                         static-power = <300>;
1453                         dynamic-power = <396>;
1454                         ts = <32000 4700 (-80) 2>;
1455                         thermal-zone = "gpu-thermal";
1456                 };
1457         };
1458
1459         gpu_opp_table: opp-table1 {
1460                 compatible = "operating-points-v2";
1461
1462                 opp@100000000 {
1463                         opp-hz = /bits/ 64 <100000000>;
1464                         opp-microvolt = <950000>;
1465                 };
1466                 opp@200000000 {
1467                         opp-hz = /bits/ 64 <200000000>;
1468                         opp-microvolt = <950000>;
1469                 };
1470                 opp@300000000 {
1471                         opp-hz = /bits/ 64 <300000000>;
1472                         opp-microvolt = <1000000>;
1473                 };
1474                 opp@400000000 {
1475                         opp-hz = /bits/ 64 <400000000>;
1476                         opp-microvolt = <1100000>;
1477                 };
1478                 opp@600000000 {
1479                         opp-hz = /bits/ 64 <600000000>;
1480                         opp-microvolt = <1250000>;
1481                 };
1482         };
1483
1484         noc: syscon@ffac0000 {
1485                 compatible = "rockchip,rk3288-noc", "syscon";
1486                 reg = <0xffac0000 0x2000>;
1487         };
1488
1489         efuse: efuse@ffb40000 {
1490                 compatible = "rockchip,rockchip-efuse";
1491                 reg = <0xffb40000 0x20>;
1492                 #address-cells = <1>;
1493                 #size-cells = <1>;
1494                 clocks = <&cru PCLK_EFUSE256>;
1495                 clock-names = "pclk_efuse";
1496
1497                 cpu_leakage: cpu_leakage@17 {
1498                         reg = <0x17 0x1>;
1499                 };
1500         };
1501
1502         gic: interrupt-controller@ffc01000 {
1503                 compatible = "arm,gic-400";
1504                 interrupt-controller;
1505                 #interrupt-cells = <3>;
1506                 #address-cells = <0>;
1507
1508                 reg = <0xffc01000 0x1000>,
1509                       <0xffc02000 0x1000>,
1510                       <0xffc04000 0x2000>,
1511                       <0xffc06000 0x2000>;
1512                 interrupts = <GIC_PPI 9 0xf04>;
1513         };
1514
1515         pinctrl: pinctrl {
1516                 compatible = "rockchip,rk3288-pinctrl";
1517                 rockchip,grf = <&grf>;
1518                 rockchip,pmu = <&pmu>;
1519                 #address-cells = <1>;
1520                 #size-cells = <1>;
1521                 ranges;
1522
1523                 gpio0: gpio0@ff750000 {
1524                         compatible = "rockchip,gpio-bank";
1525                         reg =   <0xff750000 0x100>;
1526                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1527                         clocks = <&cru PCLK_GPIO0>;
1528
1529                         gpio-controller;
1530                         #gpio-cells = <2>;
1531
1532                         interrupt-controller;
1533                         #interrupt-cells = <2>;
1534                 };
1535
1536                 gpio1: gpio1@ff780000 {
1537                         compatible = "rockchip,gpio-bank";
1538                         reg = <0xff780000 0x100>;
1539                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1540                         clocks = <&cru PCLK_GPIO1>;
1541
1542                         gpio-controller;
1543                         #gpio-cells = <2>;
1544
1545                         interrupt-controller;
1546                         #interrupt-cells = <2>;
1547                 };
1548
1549                 gpio2: gpio2@ff790000 {
1550                         compatible = "rockchip,gpio-bank";
1551                         reg = <0xff790000 0x100>;
1552                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1553                         clocks = <&cru PCLK_GPIO2>;
1554
1555                         gpio-controller;
1556                         #gpio-cells = <2>;
1557
1558                         interrupt-controller;
1559                         #interrupt-cells = <2>;
1560                 };
1561
1562                 gpio3: gpio3@ff7a0000 {
1563                         compatible = "rockchip,gpio-bank";
1564                         reg = <0xff7a0000 0x100>;
1565                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1566                         clocks = <&cru PCLK_GPIO3>;
1567
1568                         gpio-controller;
1569                         #gpio-cells = <2>;
1570
1571                         interrupt-controller;
1572                         #interrupt-cells = <2>;
1573                 };
1574
1575                 gpio4: gpio4@ff7b0000 {
1576                         compatible = "rockchip,gpio-bank";
1577                         reg = <0xff7b0000 0x100>;
1578                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1579                         clocks = <&cru PCLK_GPIO4>;
1580
1581                         gpio-controller;
1582                         #gpio-cells = <2>;
1583
1584                         interrupt-controller;
1585                         #interrupt-cells = <2>;
1586                 };
1587
1588                 gpio5: gpio5@ff7c0000 {
1589                         compatible = "rockchip,gpio-bank";
1590                         reg = <0xff7c0000 0x100>;
1591                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1592                         clocks = <&cru PCLK_GPIO5>;
1593
1594                         gpio-controller;
1595                         #gpio-cells = <2>;
1596
1597                         interrupt-controller;
1598                         #interrupt-cells = <2>;
1599                 };
1600
1601                 gpio6: gpio6@ff7d0000 {
1602                         compatible = "rockchip,gpio-bank";
1603                         reg = <0xff7d0000 0x100>;
1604                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1605                         clocks = <&cru PCLK_GPIO6>;
1606
1607                         gpio-controller;
1608                         #gpio-cells = <2>;
1609
1610                         interrupt-controller;
1611                         #interrupt-cells = <2>;
1612                 };
1613
1614                 gpio7: gpio7@ff7e0000 {
1615                         compatible = "rockchip,gpio-bank";
1616                         reg = <0xff7e0000 0x100>;
1617                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1618                         clocks = <&cru PCLK_GPIO7>;
1619
1620                         gpio-controller;
1621                         #gpio-cells = <2>;
1622
1623                         interrupt-controller;
1624                         #interrupt-cells = <2>;
1625                 };
1626
1627                 gpio8: gpio8@ff7f0000 {
1628                         compatible = "rockchip,gpio-bank";
1629                         reg = <0xff7f0000 0x100>;
1630                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1631                         clocks = <&cru PCLK_GPIO8>;
1632
1633                         gpio-controller;
1634                         #gpio-cells = <2>;
1635
1636                         interrupt-controller;
1637                         #interrupt-cells = <2>;
1638                 };
1639
1640                 hdmi {
1641                         hdmi_ddc: hdmi-ddc {
1642                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1643                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1644                         };
1645                 };
1646
1647                 pcfg_pull_up: pcfg-pull-up {
1648                         bias-pull-up;
1649                 };
1650
1651                 pcfg_pull_down: pcfg-pull-down {
1652                         bias-pull-down;
1653                 };
1654
1655                 pcfg_pull_none: pcfg-pull-none {
1656                         bias-disable;
1657                 };
1658
1659                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1660                         bias-disable;
1661                         drive-strength = <12>;
1662                 };
1663
1664                 sleep {
1665                         global_pwroff: global-pwroff {
1666                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1667                         };
1668
1669                         ddrio_pwroff: ddrio-pwroff {
1670                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1671                         };
1672
1673                         ddr0_retention: ddr0-retention {
1674                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1675                         };
1676
1677                         ddr1_retention: ddr1-retention {
1678                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1679                         };
1680                 };
1681
1682                 edp {
1683                         edp_hpd: edp-hpd {
1684                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1685                         };
1686                 };
1687
1688                 i2c0 {
1689                         i2c0_xfer: i2c0-xfer {
1690                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1691                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1692                         };
1693                 };
1694
1695                 i2c1 {
1696                         i2c1_xfer: i2c1-xfer {
1697                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1698                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1699                         };
1700                 };
1701
1702                 i2c2 {
1703                         i2c2_xfer: i2c2-xfer {
1704                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1705                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1706                         };
1707                 };
1708
1709                 i2c3 {
1710                         i2c3_xfer: i2c3-xfer {
1711                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1712                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1713                         };
1714                 };
1715
1716                 i2c4 {
1717                         i2c4_xfer: i2c4-xfer {
1718                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1719                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1720                         };
1721                 };
1722
1723                 i2c5 {
1724                         i2c5_xfer: i2c5-xfer {
1725                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1726                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1727                         };
1728                 };
1729
1730                 i2s0 {
1731                         i2s0_bus: i2s0-bus {
1732                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1733                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1734                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1735                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1736                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1737                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1738                         };
1739                 };
1740
1741                 lcdc0 {
1742                         lcdc0_ctl: lcdc0-ctl {
1743                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1744                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1745                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1746                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1747                         };
1748                 };
1749
1750                 sdmmc {
1751                         sdmmc_clk: sdmmc-clk {
1752                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1753                         };
1754
1755                         sdmmc_cmd: sdmmc-cmd {
1756                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1757                         };
1758
1759                         sdmmc_cd: sdmcc-cd {
1760                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1761                         };
1762
1763                         sdmmc_bus1: sdmmc-bus1 {
1764                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1765                         };
1766
1767                         sdmmc_bus4: sdmmc-bus4 {
1768                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1769                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1770                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1771                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1772                         };
1773                 };
1774
1775                 sdio0 {
1776                         sdio0_bus1: sdio0-bus1 {
1777                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1778                         };
1779
1780                         sdio0_bus4: sdio0-bus4 {
1781                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1782                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1783                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1784                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1785                         };
1786
1787                         sdio0_cmd: sdio0-cmd {
1788                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1789                         };
1790
1791                         sdio0_clk: sdio0-clk {
1792                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1793                         };
1794
1795                         sdio0_cd: sdio0-cd {
1796                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1797                         };
1798
1799                         sdio0_wp: sdio0-wp {
1800                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1801                         };
1802
1803                         sdio0_pwr: sdio0-pwr {
1804                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806
1807                         sdio0_bkpwr: sdio0-bkpwr {
1808                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1809                         };
1810
1811                         sdio0_int: sdio0-int {
1812                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814                 };
1815
1816                 sdio1 {
1817                         sdio1_bus1: sdio1-bus1 {
1818                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1819                         };
1820
1821                         sdio1_bus4: sdio1-bus4 {
1822                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1823                                                 <3 25 4 &pcfg_pull_up>,
1824                                                 <3 26 4 &pcfg_pull_up>,
1825                                                 <3 27 4 &pcfg_pull_up>;
1826                         };
1827
1828                         sdio1_cd: sdio1-cd {
1829                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1830                         };
1831
1832                         sdio1_wp: sdio1-wp {
1833                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1834                         };
1835
1836                         sdio1_bkpwr: sdio1-bkpwr {
1837                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1838                         };
1839
1840                         sdio1_int: sdio1-int {
1841                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1842                         };
1843
1844                         sdio1_cmd: sdio1-cmd {
1845                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1846                         };
1847
1848                         sdio1_clk: sdio1-clk {
1849                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1850                         };
1851
1852                         sdio1_pwr: sdio1-pwr {
1853                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1854                         };
1855                 };
1856
1857                 emmc {
1858                         emmc_clk: emmc-clk {
1859                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1860                         };
1861
1862                         emmc_cmd: emmc-cmd {
1863                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1864                         };
1865
1866                         emmc_pwr: emmc-pwr {
1867                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1868                         };
1869
1870                         emmc_bus1: emmc-bus1 {
1871                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1872                         };
1873
1874                         emmc_bus4: emmc-bus4 {
1875                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1876                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1877                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1878                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1879                         };
1880
1881                         emmc_bus8: emmc-bus8 {
1882                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1883                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1884                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1885                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1886                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1887                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1888                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1889                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1890                         };
1891                 };
1892
1893                 spi0 {
1894                         spi0_clk: spi0-clk {
1895                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1896                         };
1897                         spi0_cs0: spi0-cs0 {
1898                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1899                         };
1900                         spi0_tx: spi0-tx {
1901                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1902                         };
1903                         spi0_rx: spi0-rx {
1904                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1905                         };
1906                         spi0_cs1: spi0-cs1 {
1907                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1908                         };
1909                 };
1910                 spi1 {
1911                         spi1_clk: spi1-clk {
1912                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1913                         };
1914                         spi1_cs0: spi1-cs0 {
1915                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1916                         };
1917                         spi1_rx: spi1-rx {
1918                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1919                         };
1920                         spi1_tx: spi1-tx {
1921                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1922                         };
1923                 };
1924
1925                 spi2 {
1926                         spi2_cs1: spi2-cs1 {
1927                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1928                         };
1929                         spi2_clk: spi2-clk {
1930                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1931                         };
1932                         spi2_cs0: spi2-cs0 {
1933                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1934                         };
1935                         spi2_rx: spi2-rx {
1936                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1937                         };
1938                         spi2_tx: spi2-tx {
1939                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1940                         };
1941                 };
1942
1943                 uart0 {
1944                         uart0_xfer: uart0-xfer {
1945                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1946                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1947                         };
1948
1949                         uart0_cts: uart0-cts {
1950                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1951                         };
1952
1953                         uart0_rts: uart0-rts {
1954                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1955                         };
1956                 };
1957
1958                 uart1 {
1959                         uart1_xfer: uart1-xfer {
1960                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1961                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1962                         };
1963
1964                         uart1_cts: uart1-cts {
1965                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1966                         };
1967
1968                         uart1_rts: uart1-rts {
1969                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1970                         };
1971                 };
1972
1973                 uart2 {
1974                         uart2_xfer: uart2-xfer {
1975                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1976                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1977                         };
1978                         /* no rts / cts for uart2 */
1979                 };
1980
1981                 uart3 {
1982                         uart3_xfer: uart3-xfer {
1983                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1984                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1985                         };
1986
1987                         uart3_cts: uart3-cts {
1988                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1989                         };
1990
1991                         uart3_rts: uart3-rts {
1992                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1993                         };
1994                 };
1995
1996                 uart4 {
1997                         uart4_xfer: uart4-xfer {
1998                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1999                                                 <5 13 3 &pcfg_pull_none>;
2000                         };
2001
2002                         uart4_cts: uart4-cts {
2003                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2004                         };
2005
2006                         uart4_rts: uart4-rts {
2007                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2008                         };
2009                 };
2010
2011                 tsadc {
2012                         otp_gpio: otp-gpio {
2013                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2014                         };
2015
2016                         otp_out: otp-out {
2017                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2018                         };
2019                 };
2020
2021                 pwm0 {
2022                         pwm0_pin: pwm0-pin {
2023                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2024                         };
2025                 };
2026
2027                 pwm1 {
2028                         pwm1_pin: pwm1-pin {
2029                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2030                         };
2031                 };
2032
2033                 pwm2 {
2034                         pwm2_pin: pwm2-pin {
2035                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2036                         };
2037                 };
2038
2039                 pwm3 {
2040                         pwm3_pin: pwm3-pin {
2041                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2042                         };
2043                 };
2044
2045                 gmac {
2046                         rgmii_pins: rgmii-pins {
2047                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2048                                                 <3 31 3 &pcfg_pull_none>,
2049                                                 <3 26 3 &pcfg_pull_none>,
2050                                                 <3 27 3 &pcfg_pull_none>,
2051                                                 <3 28 3 &pcfg_pull_none_12ma>,
2052                                                 <3 29 3 &pcfg_pull_none_12ma>,
2053                                                 <3 24 3 &pcfg_pull_none_12ma>,
2054                                                 <3 25 3 &pcfg_pull_none_12ma>,
2055                                                 <4 0 3 &pcfg_pull_none>,
2056                                                 <4 5 3 &pcfg_pull_none>,
2057                                                 <4 6 3 &pcfg_pull_none>,
2058                                                 <4 9 3 &pcfg_pull_none_12ma>,
2059                                                 <4 4 3 &pcfg_pull_none_12ma>,
2060                                                 <4 1 3 &pcfg_pull_none>,
2061                                                 <4 3 3 &pcfg_pull_none>;
2062                         };
2063
2064                         rmii_pins: rmii-pins {
2065                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2066                                                 <3 31 3 &pcfg_pull_none>,
2067                                                 <3 28 3 &pcfg_pull_none>,
2068                                                 <3 29 3 &pcfg_pull_none>,
2069                                                 <4 0 3 &pcfg_pull_none>,
2070                                                 <4 5 3 &pcfg_pull_none>,
2071                                                 <4 4 3 &pcfg_pull_none>,
2072                                                 <4 1 3 &pcfg_pull_none>,
2073                                                 <4 2 3 &pcfg_pull_none>,
2074                                                 <4 3 3 &pcfg_pull_none>;
2075                         };
2076                 };
2077
2078                 spdif {
2079                         spdif_tx: spdif-tx {
2080                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2081                         };
2082                 };
2083
2084                 cif {
2085                         cif_dvp_d2d9: cif-dvp-d2d9 {
2086                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2087                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2088                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2089                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2090                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2091                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2092                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2093                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2094                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2095                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2096                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2097                         };
2098                 };
2099         };
2100 };