arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/suspend/rockchip-pm.h>
   5 #include <dt-bindings/sensor-dev.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk3288-pinctrl.dtsi"
   9 #include "rk3288-clocks.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk3288";
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart_bt;
  18                 serial1 = &uart_bb;
  19                 serial2 = &uart_dbg;
  20                 serial3 = &uart_gps;
  21                 serial4 = &uart_exp;
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 lcdc0 = &lcdc0;
  29                 lcdc1 = &lcdc1;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         cpu_axi_bus: cpu_axi_bus {
  72                 compatible = "rockchip,cpu_axi_bus";
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 ranges;
  76                 qos {
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79                         ranges;
  80                         /* service core */
  81                         cpup {
  82                                 reg = <0xffa80000 0x20>;
  83                         };
  84                         cpum_r {
  85                                 reg = <0xffa80080 0x20>;
  86                         };
  87                         cpum_w {
  88                                 reg = <0xffa80100 0x20>;
  89                         };
  90                         /* service dmac */
  91                         bus_dmac {
  92                                 reg = <0xffa90000 0x20>;
  93                         };
  94                         host {
  95                                 reg = <0xffa90080 0x20>;
  96                         };
  97                         crypto {
  98                                 reg = <0xffa90100 0x20>;
  99                         };
 100                         ccp {
 101                                 reg = <0xffa90180 0x20>;
 102                         };
 103                         ccs {
 104                                 reg = <0xffa90200 0x20>;
 105                         };
 106                         /* service gpu */
 107                         gpu_r {
 108                                 reg = <0xffaa0000 0x20>;
 109                         };
 110                         gpu_w {
 111                                 reg = <0xffaa0080 0x20>;
 112                         };
 113                         /* service peri */
 114                         peri {
 115                                 reg = <0xffab0000 0x20>;
 116                         };
 117                         /* service vio */
 118                         vio1_vop {
 119                                 reg = <0xffad0000 0x20>;
 120                         };
 121                         vio1_isp_w0 {
 122                                 reg = <0xffad0100 0x20>;
 123                         };
 124                         vio1_isp_w1 {
 125                                 reg = <0xffad0180 0x20>;
 126                         };
 127                         vio0_vop {
 128                                 reg = <0xffad0400 0x20>;
 129                         };
 130                         vio0_vip {
 131                                 reg = <0xffad0480 0x20>;
 132                         };
 133                         vio0_iep {
 134                                 reg = <0xffad0500 0x20>;
 135                         };
 136                         vio2_rga_r {
 137                                 reg = <0xffad0800 0x20>;
 138                         };
 139                         vio2_rga_w {
 140                                 reg = <0xffad0880 0x20>;
 141                         };
 142                         vio1_isp_r {
 143                                 reg = <0xffad0900 0x20>;
 144                         };
 145                         /* service video */
 146                         video {
 147                                 reg = <0xffae0000 0x20>;
 148                         };
 149                         /* service hevc */
 150                         hevc_r {
 151                                 reg = <0xffaf0000 0x20>;
 152                         };
 153                         hevc_w {
 154                                 reg = <0xffaf0080 0x20>;
 155                         };
 156                 };
 157                 msch {
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         ranges;
 161                         msch@0 {
 162                                 reg = <0xffac0000 0x40>;
 163                                 rockchip,read-latency = <0xff>;
 164                         };
 165                         msch@1 {
 166                                 reg = <0xffac0080 0x40>;
 167                                 rockchip,read-latency = <0xff>;
 168                         };
 169                 };
 170         };
 171
 172         sram: sram@ff710000 {
 173                 compatible = "mmio-sram";
 174                 reg = <0xff710000 0x8000>; /* 32k */
 175                 map-exec;
 176         };
 177
 178 /*
 179         timer {
 180                 compatible = "arm,armv7-timer";
 181                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 182                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 183                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 185                 clock-frequency = <24000000>;
 186         };
 187 */
 188
 189         timer@ff6b0000 {
 190                 compatible = "rockchip,timer";
 191                 reg = <0xff6b0000 0x20>;
 192                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 193                 rockchip,percpu = <0>;
 194         };
 195
 196         timer@ff6b0020 {
 197                 compatible = "rockchip,timer";
 198                 reg = <0xff6b0020 0x20>;
 199                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 200                 rockchip,percpu = <1>;
 201         };
 202
 203         timer@ff6b0040 {
 204                 compatible = "rockchip,timer";
 205                 reg = <0xff6b0040 0x20>;
 206                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 207                 rockchip,percpu = <2>;
 208         };
 209
 210         timer@ff6b0060 {
 211                 compatible = "rockchip,timer";
 212                 reg = <0xff6b0060 0x20>;
 213                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 214                 rockchip,percpu = <3>;
 215         };
 216
 217         timer@ff810000 {
 218                 compatible = "rockchip,timer";
 219                 reg = <0xff810000 0x20>;
 220                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 221                 rockchip,broadcast = <1>;
 222         };
 223
 224         timer@ff810020 {
 225                 compatible = "rockchip,timer";
 226                 reg = <0xff810020 0x20>;
 227                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 228                 rockchip,clocksource = <1>;
 229                 rockchip,count-up = <1>;
 230         };
 231
 232     amba {
 233                 #address-cells = <1>;
 234                 #size-cells = <1>;
 235                 compatible = "arm,amba-bus";
 236                 interrupt-parent = <&gic>;
 237                 ranges;
 238
 239                 pdma0: pdma@ffb20000 {
 240                         compatible = "arm,pl330", "arm,primecell";
 241                         reg = <0xffb20000 0x4000>;
 242                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 244                         #dma-cells = <1>;
 245                 };
 246
 247                 pdma1: pdma@ff250000 {
 248                         compatible = "arm,pl330", "arm,primecell";
 249                         reg = <0xff250000 0x4000>;
 250                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 252                         #dma-cells = <1>;
 253                 };
 254         };
 255
 256
 257         emmc: rksdmmc@ff0f0000 {
 258                 compatible = "rockchip,rk_mmc";
 259                 reg = <0xff0f0000 0x4000>;
 260                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 //pinctrl-names = "default",,"suspend";
 264                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 265
 266                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 267                 clock-names = "clk_mmc", "hclk_mmc";
 268                 num-slots = <1>;
 269                 fifo-depth = <0x80>;
 270                 bus-width = <4>;
 271         };
 272
 273         sdmmc: rksdmmc@ff0c0000 {
 274                 compatible = "rockchip,rk_mmc";
 275                 reg = <0xff0c0000 0x4000>;
 276                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279
 280                 //pinctrl-names = "default","suspend";
 281                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 282                 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 283
 284                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 285                 clock-names = "clk_mmc", "hclk_mmc";
 286                 num-slots = <1>;
 287                 fifo-depth = <0x100>;
 288                 bus-width = <4>;
 289
 290         };
 291
 292         sdio: rksdmmc@ff0d0000 {
 293                 compatible = "rockchip,rk_mmc";
 294                 reg = <0xff0d0000 0x4000>;
 295                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 //pinctrl-names = "default","suspend";
 299                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 300
 301                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 302                 clock-names = "clk_mmc", "hclk_mmc";
 303                 num-slots = <1>;
 304
 305                 fifo-depth = <0x100>;
 306                 bus-width = <4>;
 307         };
 308
 309         sdio1: rksdmmc@ff0e0000 {
 310                 compatible = "rockchip,rk_mmc";
 311                 reg = <0xff0e0000 0x4000>;
 312                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 //pinctrl-names = "default","suspend";
 316                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 317
 318                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 319                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 320                 clock-names = "clk_mmc", "hclk_mmc";
 321                 num-slots = <1>;
 322
 323                 fifo-depth = <0x100>;
 324                 bus-width = <4>;
 325                 status = "disabled";
 326         };
 327
 328         spi0: spi@ff110000 {
 329                 compatible = "rockchip,rockchip-spi";
 330                 reg = <0xff110000 0x1000>;
 331                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 336                 rockchip,spi-src-clk = <0>;
 337                 num-cs = <2>;
 338                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 339                 clock-names = "spi","pclk_spi0";
 340                 //dmas = <&pdma1 11>, <&pdma1 12>;
 341                 //#dma-cells = <2>;
 342                 //dma-names = "tx", "rx";
 343                 status = "disabled";
 344         };
 345
 346         spi1: spi@ff120000 {
 347                 compatible = "rockchip,rockchip-spi";
 348                 reg = <0xff120000 0x1000>;
 349                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 354                 rockchip,spi-src-clk = <1>;
 355                 num-cs = <1>;
 356                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 357                 clock-names = "spi","pclk_spi1";
 358                 //dmas = <&pdma1 13>, <&pdma1 14>;
 359                 //#dma-cells = <2>;
 360                 //dma-names = "tx", "rx";
 361                 status = "disabled";
 362         };
 363
 364         spi2: spi@ff130000 {
 365                 compatible = "rockchip,rockchip-spi";
 366                 reg = <0xff130000 0x1000>;
 367                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 372                 rockchip,spi-src-clk = <2>;
 373                 num-cs = <2>;
 374                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 375                 clock-names = "spi","pclk_spi2";
 376                 //dmas = <&pdma1 15>, <&pdma1 16>;
 377                 //#dma-cells = <2>;
 378                 //dma-names = "tx", "rx";
 379                 status = "disabled";
 380         };
 381
 382         uart_bt: serial@ff180000 {
 383                 compatible = "rockchip,serial";
 384                 reg = <0xff180000 0x100>;
 385                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 386                 clock-frequency = <24000000>;
 387                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 388                 clock-names = "sclk_uart", "pclk_uart";
 389                 reg-shift = <2>;
 390                 reg-io-width = <4>;
 391                 dmas = <&pdma1 1>, <&pdma1 2>;
 392                 #dma-cells = <2>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 395                 status = "disabled";
 396         };
 397
 398         uart_bb: serial@ff190000 {
 399                 compatible = "rockchip,serial";
 400                 reg = <0xff190000 0x100>;
 401                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 402                 clock-frequency = <24000000>;
 403                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 404                 clock-names = "sclk_uart", "pclk_uart";
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 dmas = <&pdma1 3>, <&pdma1 4>;
 408                 #dma-cells = <2>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 411                 status = "disabled";
 412         };
 413
 414         uart_dbg: serial@ff690000 {
 415                 compatible = "rockchip,serial";
 416                 reg = <0xff690000 0x100>;
 417                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 418                 clock-frequency = <24000000>;
 419                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 420                 clock-names = "sclk_uart", "pclk_uart";
 421                 reg-shift = <2>;
 422                 reg-io-width = <4>;
 423                 dmas = <&pdma0 4>, <&pdma0 5>;
 424                 #dma-cells = <2>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&uart2_xfer>;
 427                 status = "disabled";
 428         };
 429
 430         uart_gps: serial@ff1b0000 {
 431                 compatible = "rockchip,serial";
 432                 reg = <0xff1b0000 0x100>;
 433                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 434                 clock-frequency = <24000000>;
 435                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 436                 clock-names = "sclk_uart", "pclk_uart";
 437                 current-speed = <115200>;
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 dmas = <&pdma1 7>, <&pdma1 8>;
 441                 #dma-cells = <2>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 444                 status = "disabled";
 445         };
 446
 447         uart_exp: serial@ff1c0000 {
 448                 compatible = "rockchip,serial";
 449                 reg = <0xff1c0000 0x100>;
 450                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 451                 clock-frequency = <24000000>;
 452                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 453                 clock-names = "sclk_uart", "pclk_uart";
 454                 reg-shift = <2>;
 455                 reg-io-width = <4>;
 456                 dmas = <&pdma1 9>, <&pdma1 10>;
 457                 #dma-cells = <2>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 460                 status = "disabled";
 461         };
 462
 463         fiq-debugger {
 464                 compatible = "rockchip,fiq-debugger";
 465                 rockchip,serial-id = <2>;
 466                 rockchip,signal-irq = <106>;
 467                 rockchip,wake-irq = <0>;
 468                 status = "disabled";
 469         };
 470
 471         clocks-init{
 472                 compatible = "rockchip,clocks-init";
 473                 rockchip,clocks-init-parent =
 474                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 475                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 476                         <&clk_i2s_pll &clk_cpll>;
 477                 rockchip,clocks-init-rate =
 478                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 479                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 480                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 481                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 482                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 483                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 484                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 485                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 486                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 487                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 488                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 489                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 490                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 491                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 492                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 493                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 494         };
 495
 496         i2c0: i2c@ff650000 {
 497                 compatible = "rockchip,rk30-i2c";
 498                 reg = <0xff650000 0x1000>;
 499                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 500                 #address-cells = <1>;
 501                 #size-cells = <0>;
 502                 pinctrl-names = "default", "gpio";
 503                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 504                 pinctrl-1 = <&i2c0_gpio>;
 505                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 506                 clocks = <&clk_gates10 2>;
 507                 rockchip,check-idle = <1>;
 508                 status = "disabled";
 509         };
 510
 511         i2c1: i2c@ff140000 {
 512                 compatible = "rockchip,rk30-i2c";
 513                 reg = <0xff140000 0x1000>;
 514                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 515                 #address-cells = <1>;
 516                 #size-cells = <0>;
 517                 pinctrl-names = "default", "gpio";
 518                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 519                 pinctrl-1 = <&i2c1_gpio>;
 520                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 521                 clocks = <&clk_gates10 3>;
 522                 rockchip,check-idle = <1>;
 523                 status = "disabled";
 524         };
 525
 526         i2c2: i2c@ff660000 {
 527                 compatible = "rockchip,rk30-i2c";
 528                 reg = <0xff660000 0x1000>;
 529                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 pinctrl-names = "default", "gpio";
 533                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 534                 pinctrl-1 = <&i2c2_gpio>;
 535                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 536                 clocks = <&clk_gates6 13>;
 537                 rockchip,check-idle = <1>;
 538                 status = "disabled";
 539         };
 540
 541         i2c3: i2c@ff150000 {
 542                 compatible = "rockchip,rk30-i2c";
 543                 reg = <0xff150000 0x1000>;
 544                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 pinctrl-names = "default", "gpio";
 548                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 549                 pinctrl-1 = <&i2c3_gpio>;
 550                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 551                 clocks = <&clk_gates6 14>;
 552                 rockchip,check-idle = <1>;
 553                 status = "disabled";
 554         };
 555
 556         i2c4: i2c@ff160000 {
 557                 compatible = "rockchip,rk30-i2c";
 558                 reg = <0xff160000 0x1000>;
 559                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 pinctrl-names = "default", "gpio";
 563                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 564                 pinctrl-1 = <&i2c4_gpio>;
 565                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 566                 clocks = <&clk_gates6 15>;
 567                 rockchip,check-idle = <1>;
 568                 status = "disabled";
 569         };
 570
 571         i2c5: i2c@ff170000 {
 572                 compatible = "rockchip,rk30-i2c";
 573                 reg = <0xff170000 0x1000>;
 574                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 pinctrl-names = "default", "gpio";
 578                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 579                 pinctrl-1 = <&i2c5_gpio>;
 580                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 581                 clocks = <&clk_gates7 0>;
 582                 rockchip,check-idle = <1>;
 583                 status = "disabled";
 584         };
 585
 586
 587         fb: fb{
 588                 compatible = "rockchip,rk-fb";
 589                 rockchip,disp-mode = <DUAL>;
 590         };
 591
 592         rk_screen: rk_screen{
 593                         compatible = "rockchip,screen";
 594         };
 595
 596         lvds: lvds@ff96c000 {
 597                 compatible = "rockchip, rk32-lvds";
 598                 reg = <0xff96c000 0x4000>;
 599                 clocks = <&clk_gates16 7>;
 600                 clock-names = "pclk_lvds";
 601         };
 602
 603         edp: edp@ff970000 {
 604                 compatible = "rockchip, rk32-edp";
 605                 reg = <0xff970000 0x4000>;
 606                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 607                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 608                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 609         };
 610
 611         hdmi: hdmi@ff980000 {
 612                 compatible = "rockchip,rk3288-hdmi";
 613                 reg = <0xff980000 0x20000>;
 614                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 615                 pinctrl-names = "default", "gpio";
 616                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 617                 pinctrl-1 = <&i2c5_gpio>;
 618                 clocks = <&clk_gates16 9>;
 619                 clock-names = "pclk_hdmi";
 620                 status = "disabled";
 621         };
 622
 623         lcdc1: lcdc@ff940000 {
 624                 compatible = "rockchip,rk3288-lcdc";
 625                 rockchip,prop = <PRMRY>;
 626                 rochchip,pwr18 = <0>;
 627                 reg = <0xff940000 0x10000>;
 628                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 629                 pinctrl-names = "default", "gpio";
 630                 pinctrl-0 = <&lcdc0_lcdc>;
 631                 pinctrl-1 = <&lcdc0_gpio>;
 632                 status = "disabled";
 633                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>;
 634                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 635         };
 636
 637         lcdc0: lcdc@ff930000 {
 638                 compatible = "rockchip,rk3288-lcdc";
 639                 rockchip,prop = <EXTEND>;
 640                 rockchip,pwr18 = <0>;
 641                 reg = <0xff930000 0x10000>;
 642                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 643                 //pinctrl-names = "default", "gpio";
 644                 //pinctrl-0 = <&lcdc0_lcdc>;
 645                 //pinctrl-1 = <&lcdc0_gpio>;
 646                 status = "disabled";
 647                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>;
 648                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 649         };
 650
 651         adc: adc@ff100000 {
 652                 compatible = "rockchip,saradc";
 653                 reg = <0xff100000 0x100>;
 654                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 655                 #io-channel-cells = <1>;
 656                 io-channel-ranges;
 657                 rockchip,adc-vref = <1800>;
 658                 clock-frequency = <1000000>;
 659                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 660                 clock-names = "saradc", "pclk_saradc";
 661                 status = "disabled";
 662         };
 663
 664         rga@ff920000 {
 665                 compatible = "rockchip,rga";
 666                 reg = <0xff920000 0x1000>;
 667                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 669                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 670         };
 671
 672         i2s: rockchip-i2s@0xff890000 {
 673                 compatible = "rockchip-i2s";
 674                 reg = <0xff890000 0x10000>;
 675                 i2s-id = <0>;
 676                 clocks = <&clk_i2s>, <&clk_i2s_out>;
 677                 clock-names = "i2s_clk","i2s_mclk";
 678                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 679                 dmas = <&pdma0 0>,
 680                         <&pdma0 1>;
 681                 //#dma-cells = <2>;
 682                 dma-names = "tx", "rx";
 683                 pinctrl-names = "default", "sleep";
 684                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 685                 pinctrl-1 = <&i2s_gpio>;
 686         };
 687
 688         spdif: rockchip-spdif@0xff8b0000 {
 689                 compatible = "rockchip-spdif";
 690                 reg = <0xff8b0000 0x10000>;     //8channel
 691                 //reg = <ff880000 0x10000>;//2channel
 692                 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
 693                 clock-names = "spdif_mclk","spdif_8ch_mclk";
 694                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 695                 dmas = <&pdma0 3>;
 696                 //dmas = <&pdma0 2>; //2channel
 697                 //#dma-cells = <1>;
 698                 dma-names = "tx";
 699                 pinctrl-names = "default";
 700                 pinctrl-0 = <&spdif_tx>;
 701         };
 702
 703         pwm0: pwm@ff680000 {
 704                 compatible = "rockchip,rk-pwm";
 705                 reg = <0xff680000 0x10>;
 706                 #pwm-cells = <2>;
 707                 pinctrl-names = "default";
 708                 pinctrl-0 = <&pwm0_pin>;
 709                 clocks = <&clk_gates11 11>;
 710                 clock-names = "pclk_pwm";
 711                 status = "okay";
 712         };
 713
 714         pwm1: pwm@ff680010 {
 715                 compatible = "rockchip,rk-pwm";
 716                 reg = <0xff680010 0x10>;
 717                 #pwm-cells = <2>;
 718                 pinctrl-names = "default";
 719                 pinctrl-0 = <&pwm1_pin>;
 720                 clocks = <&clk_gates11 11>;
 721                 clock-names = "pclk_pwm";
 722                 status = "disabled";
 723         };
 724
 725         pwm2: pwm@ff680020 {
 726                 compatible = "rockchip,rk-pwm";
 727                 reg = <0xff680020 0x10>;
 728                 #pwm-cells = <2>;
 729                 pinctrl-names = "default";
 730                 pinctrl-0 = <&pwm2_pin>;
 731                 clocks = <&clk_gates11 11>;
 732                 clock-names = "pclk_pwm";
 733                 status = "disabled";
 734         };
 735
 736         pwm3: pwm@ff680030 {
 737                 compatible = "rockchip,rk-pwm";
 738                 reg = <0xff680030 0x10>;
 739                 #pwm-cells = <2>;
 740                 pinctrl-names = "default";
 741                 pinctrl-0 = <&pwm3_pin>;
 742                 clocks = <&clk_gates11 11>;
 743                 clock-names = "pclk_pwm";
 744                 status = "disabled";
 745         };
 746         dvfs {
 747                 vd_arm:
 748                 vd_arm {
 749                         regulator_name="vdd_arm";
 750                         suspend_volt=<1000>; //mV
 751                         pd_a12 {
 752                                 clk_core_dvfs_table:
 753                                 clk_core {
 754                                         operating-points = <
 755                                                 /* KHz    uV */
 756                                                 312000 1100000
 757                                                 504000 1100000
 758                                                 816000 1100000
 759                                                 1008000 1100000
 760                                                 >;
 761                                         status = "okay";
 762                                 };
 763                         };
 764                 };
 765
 766                 vd_logic:
 767                 vd_logic {
 768                         regulator_name="vdd_logic";
 769                         suspend_volt=<1000>; //mV
 770                         pd_ddr {
 771                                 clk_ddr_dvfs_table:
 772                                 clk_ddr {
 773                                         operating-points = <
 774                                                 /* KHz    uV */
 775                                                 200000 1200000
 776                                                 300000 1200000
 777                                                 400000 1200000
 778                                                 >;
 779                                         status = "disable";
 780                                 };
 781                         };
 782
 783                         pd_vpu {
 784                                 clk_ddr_vepu_table:
 785                                 clk_vepu {
 786                                         operating-points = <
 787                                                 /* KHz    uV */
 788                                                 200000 1300000
 789                                                 300000 1300000
 790                                                 400000 1300000
 791                                                 >;
 792                                         status = "okay";
 793                                 };
 794                         };
 795                 };
 796
 797                 vd_gpu:
 798                 vd_gpu {
 799                         regulator_name="vdd_gpu";
 800                         suspend_volt=<1000>; //mV
 801                         pd_gpu {
 802                                 clk_gpu_dvfs_table:
 803                                 clk_gpu {
 804                                         operating-points = <
 805                                                 /* KHz    uV */
 806                                                 200000 1200000
 807                                                 300000 1200000
 808                                                 400000 1200000
 809                                                 >;
 810                                         status = "okay";
 811                                 };
 812                         };
 813                 };
 814         };
 815
 816         ion {
 817                 compatible = "rockchip,ion";
 818                 #address-cells = <1>;
 819                 #size-cells = <0>;
 820                 rockchip,ion-heap@1 { /* CMA HEAP */
 821                         compatible = "rockchip,ion-reserve";
 822                         reg = <1>;
 823                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 824                 };
 825                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 826                         reg = <3>;
 827                 };
 828         };
 829
 830
 831         vpu: vpu_service@ff9a0000 {
 832                 compatible = "vpu_service";
 833                 reg = <0xff9a0000 0x800>;
 834                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 835                 interrupt-names = "irq_enc", "irq_dec";
 836                 clocks = <&clk_vepu>, <&hclk_vepu>;
 837                 clock-names = "aclk_vcodec", "hclk_vcodec";
 838                 name = "vpu_service";
 839                 //status = "disabled";
 840         };
 841
 842         hevc: hevc_service@ff9c0000 {
 843                 compatible = "rockchip,hevc_service";
 844                 reg = <0xff9c0000 0x800>;
 845                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 846                 interrupt-names = "irq_dec";
 847                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 848                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 849                 name = "hevc_service";
 850                 //status = "disabled";
 851         };
 852
 853         iep: iep@ff900000 {
 854                 compatible = "rockchip,iep";
 855                 reg = <0xff900000 0x800>;
 856                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 857                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 858                 clock_names = "aclk_iep", "hclk_iep";
 859                 status = "okay";
 860         };
 861
 862         dwc_control_usb: dwc-control-usb@ff770284 {
 863                 compatible = "rockchip,rk3288-dwc-control-usb";
 864                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 865                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 866                       <0xff770320 0x14>, <0xff770334 0x14>,
 867                       <0xff770348 0x10>, <0xff770358 0x08>,
 868                       <0xff770360 0x08>;
 869                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 870                     "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 871                     "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 872                     "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 873                     "GRF_UOC4_BASE";
 874                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 875                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 876                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 877                 interrupt-names = "otg_id", "otg_bvalid",
 878                           "otg_linestate", "host0_linestate",
 879                           "host1_linestate";
 880                 gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,/*HOST_VBUS_DRV*/
 881                         <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;/*OTG_VBUS_DRV*/
 882                 /*clocks = <&clk_gates7 9>;*/
 883                 /*clock-names = "hclk_usb_peri";*/
 884                 rockchip,remote_wakeup;
 885                 rockchip,usb_irq_wakeup;
 886
 887                 usb_bc{
 888                         compatible = "synopsys,phy";
 889                                         /* offset bit mask */
 890                         rk_usb,bvalid     = <0x288 14 1>;
 891                         rk_usb,dcdenb     = <0x328 14 1>;
 892                         rk_usb,vdatsrcenb = <0x328  7 1>;
 893                         rk_usb,vdatdetenb = <0x328  6 1>;
 894                         rk_usb,chrgsel    = <0x328  5 1>;
 895                         rk_usb,chgdet     = <0x2cc 23 1>;
 896                         rk_usb,fsvminus   = <0x2cc 25 1>;
 897                         rk_usb,fsvplus    = <0x2cc 24 1>;
 898                 };
 899         };
 900
 901         usb0: usb@ff580000 {
 902                 compatible = "rockchip,rk3288_usb20_otg";
 903                 reg = <0xff580000 0x40000>;
 904                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 905                 /*clocks = <&clk_gates13 4>, <&clk_gates7 4>;*/
 906                 /*clock-names = "clk_usbphy0", "hclk_usb0";*/
 907         };
 908
 909         usb1: usb@ff540000 {
 910                 compatible = "rockchip,rk3288_usb20_host";
 911                 reg = <0xff540000 0x40000>;
 912                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 913                 /*clocks = <&clk_gates13 5>, <&clk_gates7 6>;*/
 914                 /*clock-names = "clk_usbphy1", "hclk_usb1";*/
 915         };
 916
 917         usb2: usb@ff500000 {
 918                 compatible = "rockchip,rk3288_rk_ehci_host";
 919                 reg = <0xff500000 0x20000>;
 920                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 921                 /*clocks = <&clk_gates13 6>, <&clk_gates7 7>;*/
 922                 /*clock-names = "clk_usbphy2", "hclk_usb2";*/
 923         };
 924
 925         usb3: usb@ff520000 {
 926                 compatible = "rockchip,rk3288_rk_ohci_host";
 927                 reg = <0xff520000 0x20000>;
 928                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 929                 /*clocks = <&clk_gates13 6>, <&clk_gates7 7>;*/
 930                 /*clock-names = "clk_usbphy3", "hclk_usb3";*/
 931         };
 932
 933         hsic: hsic@ff5c0000 {
 934                 compatible = "rockchip,rk3288_rk_hsic_host";
 935                 reg = <0xff5c0000 0x40000>;
 936                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 937                 /*clocks = <&hsicphy_480m>, <&clk_gates7 8>,*/
 938                 /*         <&hsicphy_12m>, <&clk_otgphy1_480m>,*/
 939                 /*         <&clk_otgphy2_480m>;*/
 940                 /*clock-names = "hsicphy_480m", "hclk_hsic",*/
 941                 /*              "hsicphy_12m", "hsic_usbphy1",*/
 942                 /*              "hsic_usbphy2";*/
 943         };
 944
 945         gmac: eth@ff290000 {
 946                 compatible = "rockchip,gmac";
 947                 reg = <0xff290000 0x10000>;
 948                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 949                 interrupt-names = "macirq";
 950                 //phy-mode = "rmii";
 951                 phy-mode = "rgmii";
 952                 pinctrl-names = "default";
 953                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 954         };
 955     gpu{
 956         compatible = "arm,malit764",
 957                      "arm,malit76x",
 958                      "arm,malit7xx",
 959                      "arm,mali-midgard";
 960         reg = <0xffa30000 0x10000>;
 961         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 962                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 963                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 964         interrupt-names = "JOB",
 965                           "MMU",
 966                           "GPU";
 967     };
 968
 969     iep_mmu{
 970         dbgname = "iep";
 971         compatible = "iommu,iep_mmu";
 972         reg = <0xffa40000 0x10000>;
 973         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 974         interrupt-names = "iep_mmu";
 975     };
 976
 977     vip_mmu{
 978         dbgname = "vip";
 979         compatible = "iommu,vip_mmu";
 980         reg = <0xffa40000 0x10000>;
 981         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 982         interrupt-names = "vip_mmu";
 983     };
 984
 985     isp0_mmu{
 986         dbgname = "isp0";
 987         compatible = "iommu,isp0_mmu";
 988         reg = <0xffa40000 0x10000>;
 989         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 990         interrupt-names = "isp0_mmu";
 991     };
 992
 993     isp1_mmu{
 994         dbgname = "isp1";
 995         compatible = "iommu,isp1_mmu";
 996         reg = <0xffa40000 0x10000>;
 997         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 998         interrupt-names = "isp1_mmu";
 999     };
1000
1001     vopb_mmu{
1002         dbgname = "vopb";
1003         compatible = "iommu,vopb_mmu";
1004         reg = <0xffa40000 0x10000>;
1005         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1006         interrupt-names = "vopb_mmu";
1007     };
1008
1009     vopl_mmu{
1010         dbgname = "vopl";
1011         compatible = "iommu,vopl_mmu";
1012         reg = <0xffa40000 0x10000>;
1013         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1014         interrupt-names = "vopl_mmu";
1015     };
1016
1017     rockchip_suspend {
1018                     rockchip,ctrbits = <
1019                                     (0
1020                                     //|RKPM_CTR_PWR_DMNS
1021                                     //|RKPM_CTR_GTCLKS
1022                                     //|RKPM_CTR_PLLS
1023                                     //|RKPM_CTR_SYSCLK_DIV
1024                                     //|RKPM_CTR_NORIDLE_MD
1025                                     )
1026                                 >;
1027                   rockchip,pmic-gpios=<
1028                                                     RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1029                                                     RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1030                                                     >;
1031             };
1032
1033            isp:isp@0xFF910000{
1034                 compatible = "rockchip,isp";
1035                 reg = <0xFF910000 0x10000>;
1036                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1037                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&dummy>, <&clk_cif_out>;
1038                         clock_names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout";
1039                         pinctrl-names = "default", "isp_dvp8bit","isp_dvp10bit","isp_dvp12bit";
1040                         pinctrl-0 = <&isp_mipi>;
1041                         pinctrl-1 = <&isp_mipi &isp_dvp_sync_d2d9>;
1042                         pinctrl-2 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1>;
1043                         pinctrl-3 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1 &isp_dvpd10d11>;
1044
1045                         status = "disabled";
1046         };
1047
1048         tsadc: tsadc@ff280000{
1049                         compatible = "rockchip,tsadc";
1050                         reg = <0xff280000 0x100>;
1051                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1052                         #io-channel-cells = <1>;
1053                         io-channel-ranges;
1054                         clock-frequency = <50000>;
1055                         clocks = <&clk_tsadc>, <&clk_gates7 2>;
1056                         clock-names = "tsadc", "pclk_tsadc";
1057                         status = "okay";
1058         };
1059
1060
1061 };